1*d7272dd5SGatien Chevallier /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */ 2*d7272dd5SGatien Chevallier /* 3*d7272dd5SGatien Chevallier * Copyright (C) STMicroelectronics 2023-2025 - All Rights Reserved 4*d7272dd5SGatien Chevallier * Author: Gatien Chevallier <gatien.chevallier@foss.st.com> 5*d7272dd5SGatien Chevallier */ 6*d7272dd5SGatien Chevallier 7*d7272dd5SGatien Chevallier #ifndef _DT_BINDINGS_TAMPER_ST_STM32MP25_TAMP_H_ 8*d7272dd5SGatien Chevallier #define _DT_BINDINGS_TAMPER_ST_STM32MP25_TAMP_H_ 9*d7272dd5SGatien Chevallier 10*d7272dd5SGatien Chevallier /* Internal Tampers */ 11*d7272dd5SGatien Chevallier #define INT_TAMPER_BKUP_DOMAIN_THRESHOLD 1 12*d7272dd5SGatien Chevallier #define INT_TAMPER_TEMPERATURE_MONITORING 2 13*d7272dd5SGatien Chevallier #define INT_TAMPER_LSE_MONITORING 3 14*d7272dd5SGatien Chevallier #define INT_TAMPER_HSE_MONITORING 4 15*d7272dd5SGatien Chevallier #define INT_TAMPER_RTC_CALENDAR_OVERFLOW 5 16*d7272dd5SGatien Chevallier #define INT_TAMPER_JTAG_SWD_ACCESS 6 17*d7272dd5SGatien Chevallier #define INT_TAMPER_VDDCORE_MONITORING 7 18*d7272dd5SGatien Chevallier #define INT_TAMPER_MONOTONIC_COUNTER_1 8 19*d7272dd5SGatien Chevallier #define INT_TAMPER_CRYPTO_PERIPH_FAULT 9 20*d7272dd5SGatien Chevallier #define INT_TAMPER_MONOTONIC_COUNTER_2 10 21*d7272dd5SGatien Chevallier #define INT_TAMPER_IWDG3_RESET 11 22*d7272dd5SGatien Chevallier #define INT_TAMPER_VDDCPU_MONITORING 12 23*d7272dd5SGatien Chevallier /* No event linked to tamper13 */ 24*d7272dd5SGatien Chevallier #define INT_TAMPER_13 13 25*d7272dd5SGatien Chevallier #define INT_TAMPER_IWDG5_RESET 14 26*d7272dd5SGatien Chevallier #define INT_TAMPER_IWDG1_RESET 15 27*d7272dd5SGatien Chevallier 28*d7272dd5SGatien Chevallier /* External Tampers */ 29*d7272dd5SGatien Chevallier #define EXT_TAMPER_1 1 30*d7272dd5SGatien Chevallier #define EXT_TAMPER_2 2 31*d7272dd5SGatien Chevallier #define EXT_TAMPER_3 3 32*d7272dd5SGatien Chevallier #define EXT_TAMPER_4 4 33*d7272dd5SGatien Chevallier #define EXT_TAMPER_5 5 34*d7272dd5SGatien Chevallier #define EXT_TAMPER_6 6 35*d7272dd5SGatien Chevallier #define EXT_TAMPER_7 7 36*d7272dd5SGatien Chevallier #define EXT_TAMPER_8 8 37*d7272dd5SGatien Chevallier 38*d7272dd5SGatien Chevallier /* Tamper mode */ 39*d7272dd5SGatien Chevallier #define TAMPER_CONFIRMED_MODE 1 40*d7272dd5SGatien Chevallier #define TAMPER_POTENTIAL_MODE 2 41*d7272dd5SGatien Chevallier 42*d7272dd5SGatien Chevallier #endif /* _DT_BINDINGS_TAMPER_ST_STM32MP25_TAMP_H_ */ 43