1*12941fdcSEtienne Carriere /* SPDX-License-Identifier: GPL-2.0 OR MIT */ 2*12941fdcSEtienne Carriere /* 3*12941fdcSEtienne Carriere * This header provides constants for the ARM GIC. 4*12941fdcSEtienne Carriere */ 5*12941fdcSEtienne Carriere 6*12941fdcSEtienne Carriere #ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 7*12941fdcSEtienne Carriere #define _DT_BINDINGS_INTERRUPT_CONTROLLER_ARM_GIC_H 8*12941fdcSEtienne Carriere 9*12941fdcSEtienne Carriere #include <dt-bindings/interrupt-controller/irq.h> 10*12941fdcSEtienne Carriere 11*12941fdcSEtienne Carriere /* interrupt specifier cell 0 */ 12*12941fdcSEtienne Carriere 13*12941fdcSEtienne Carriere #define GIC_SPI 0 14*12941fdcSEtienne Carriere #define GIC_PPI 1 15*12941fdcSEtienne Carriere 16*12941fdcSEtienne Carriere /* 17*12941fdcSEtienne Carriere * Interrupt specifier cell 2. 18*12941fdcSEtienne Carriere * The flags in irq.h are valid, plus those below. 19*12941fdcSEtienne Carriere */ 20*12941fdcSEtienne Carriere #define GIC_CPU_MASK_RAW(x) ((x) << 8) 21*12941fdcSEtienne Carriere #define GIC_CPU_MASK_SIMPLE(num) GIC_CPU_MASK_RAW((1 << (num)) - 1) 22*12941fdcSEtienne Carriere 23*12941fdcSEtienne Carriere #endif 24