1*668c0368SGatien Chevallier /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*668c0368SGatien Chevallier /* 3*668c0368SGatien Chevallier * Copyright (C) 2020-2024, STMicroelectronics - All Rights Reserved 4*668c0368SGatien Chevallier */ 5*668c0368SGatien Chevallier 6*668c0368SGatien Chevallier #ifndef _DT_BINDINGS_FIREWALL_TZC400_H 7*668c0368SGatien Chevallier #define _DT_BINDINGS_FIREWALL_TZC400_H 8*668c0368SGatien Chevallier 9*668c0368SGatien Chevallier #define DT_TZC_REGION_S_NONE 0 10*668c0368SGatien Chevallier #define DT_TZC_REGION_S_RD 1 11*668c0368SGatien Chevallier #define DT_TZC_REGION_S_WR 2 12*668c0368SGatien Chevallier #define DT_TZC_REGION_S_RDWR 3 13*668c0368SGatien Chevallier 14*668c0368SGatien Chevallier #define DT_REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 15*668c0368SGatien Chevallier #define DT_REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 16*668c0368SGatien Chevallier #define DT_REGION_ID_ACCESS_NSAID_ID_MASK 0xf 17*668c0368SGatien Chevallier 18*668c0368SGatien Chevallier #define DT_TZC_REGION_ACCESS_RD(id) \ 19*668c0368SGatien Chevallier ((1 << ((id) & DT_REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 20*668c0368SGatien Chevallier DT_REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 21*668c0368SGatien Chevallier 22*668c0368SGatien Chevallier #define DT_TZC_REGION_ACCESS_WR(id) \ 23*668c0368SGatien Chevallier ((1 << ((id) & DT_REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 24*668c0368SGatien Chevallier DT_REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 25*668c0368SGatien Chevallier 26*668c0368SGatien Chevallier #define DT_TZC_REGION_ACCESS_RDWR(id) \ 27*668c0368SGatien Chevallier (DT_TZC_REGION_ACCESS_RD(id) | DT_TZC_REGION_ACCESS_WR(id)) 28*668c0368SGatien Chevallier 29*668c0368SGatien Chevallier #endif /* _DT_BINDINGS_FIREWALL_TZC400_H */ 30