1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2020-2024, STMicroelectronics 4 */ 5 6 #ifndef _DT_BINDINGS_FIREWALL_STM32MP25_RISAF_H 7 #define _DT_BINDINGS_FIREWALL_STM32MP25_RISAF_H 8 9 /* RISAF region IDs */ 10 #define RISAF_REG_ID(idx) (idx) 11 12 /* RISAF base region enable modes */ 13 #define RIF_BREN_DIS 0x0 14 #define RIF_BREN_EN 0x1 15 16 /* RISAF encryption modes */ 17 #define RIF_ENC_DIS 0x0 18 #define RIF_ENC_EN 0x2 19 20 #define DT_RISAF_EN_SHIFT 4 21 #define DT_RISAF_SEC_SHIFT 5 22 #define DT_RISAF_ENC_SHIFT 6 23 #define DT_RISAF_PRIV_SHIFT 8 24 #define DT_RISAF_READ_SHIFT 16 25 #define DT_RISAF_WRITE_SHIFT 24 26 27 #define DT_RISAF_REG_ID_MASK U(0xF) 28 #define DT_RISAF_EN_MASK BIT(DT_RISAF_EN_SHIFT) 29 #define DT_RISAF_SEC_MASK BIT(DT_RISAF_SEC_SHIFT) 30 #define DT_RISAF_ENC_MASK GENMASK_32(7, 6) 31 #define DT_RISAF_PRIV_MASK GENMASK_32(15, 8) 32 #define DT_RISAF_READ_MASK GENMASK_32(23, 16) 33 #define DT_RISAF_WRITE_MASK GENMASK_32(31, 24) 34 35 #define RISAFPROT(risaf_region, cid_read_list, cid_write_list, cid_priv_list, \ 36 sec, enc, enabled) \ 37 (((cid_write_list) << DT_RISAF_WRITE_SHIFT) | \ 38 ((cid_read_list) << DT_RISAF_READ_SHIFT) | \ 39 ((cid_priv_list) << DT_RISAF_PRIV_SHIFT) | \ 40 ((enc) << DT_RISAF_ENC_SHIFT) | \ 41 ((sec) << DT_RISAF_SEC_SHIFT) | \ 42 ((enabled) << DT_RISAF_EN_SHIFT) | \ 43 (risaf_region)) 44 45 #endif /* _DT_BINDINGS_FIREWALL_STM32MP25_RISAF_H */ 46