1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ 2 /* 3 * Copyright (C) 2020-2024, STMicroelectronics - All Rights Reserved 4 */ 5 6 #ifndef _DT_BINDINGS_FIREWALL_STM32MP25_RIF_H 7 #define _DT_BINDINGS_FIREWALL_STM32MP25_RIF_H 8 9 /* RIF CIDs */ 10 #define RIF_CID0 0x0 11 #define RIF_CID1 0x1 12 #define RIF_CID2 0x2 13 #define RIF_CID3 0x3 14 #define RIF_CID4 0x4 15 #define RIF_CID5 0x5 16 #define RIF_CID6 0x6 17 #define RIF_CID7 0x7 18 19 /* RIF semaphore list */ 20 #define EMPTY_SEMWL 0x0 21 #ifdef __ASSEMBLER__ 22 #define RIF_CID0_BF (1 << RIF_CID0) 23 #define RIF_CID1_BF (1 << RIF_CID1) 24 #define RIF_CID2_BF (1 << RIF_CID2) 25 #define RIF_CID3_BF (1 << RIF_CID3) 26 #define RIF_CID4_BF (1 << RIF_CID4) 27 #define RIF_CID5_BF (1 << RIF_CID5) 28 #define RIF_CID6_BF (1 << RIF_CID6) 29 #define RIF_CID7_BF (1 << RIF_CID7) 30 #else /* __ASSEMBLER__ */ 31 #define RIF_CID0_BF BIT(RIF_CID0) 32 #define RIF_CID1_BF BIT(RIF_CID1) 33 #define RIF_CID2_BF BIT(RIF_CID2) 34 #define RIF_CID3_BF BIT(RIF_CID3) 35 #define RIF_CID4_BF BIT(RIF_CID4) 36 #define RIF_CID5_BF BIT(RIF_CID5) 37 #define RIF_CID6_BF BIT(RIF_CID6) 38 #define RIF_CID7_BF BIT(RIF_CID7) 39 #endif /* __ASSEMBLER__ */ 40 41 /* RIF secure levels */ 42 #define RIF_NSEC 0x0 43 #define RIF_SEC 0x1 44 45 /* RIF privilege levels */ 46 #define RIF_NPRIV 0x0 47 #define RIF_PRIV 0x1 48 49 /* RIF semaphore modes */ 50 #define RIF_SEM_DIS 0x0 51 #define RIF_SEM_EN 0x1 52 53 /* RIF CID filtering modes */ 54 #define RIF_CFDIS 0x0 55 #define RIF_CFEN 0x1 56 57 /* RIF lock states */ 58 #define RIF_UNLOCK 0x0 59 #define RIF_LOCK 0x1 60 61 /* Used when a field in a macro has no impact */ 62 #define RIF_UNUSED 0x0 63 64 /* Most below macros aim to ease DTS files readability */ 65 #define RIF_EXTI1_RESOURCE(x) (x) 66 67 #define RIF_EXTI2_RESOURCE(x) (x) 68 69 #define RIF_FMC_CTRL(x) (x) 70 71 #define RIF_IOPORT_PIN(x) (x) 72 73 #define RIF_HPDMA_CHANNEL(x) (x) 74 75 #define RIF_IPCC_CPU1_CHANNEL(x) ((x) - 1) 76 77 #define RIF_IPCC_CPU2_CHANNEL(x) (((x) - 1) + 16) 78 79 #define RIF_PWR_RESOURCE(x) (x) 80 81 #define RIF_HSEM_RESOURCE(x) (x) 82 83 /* Shareable PWR resources, RIF_PWR_RESOURCE_WIO(0) doesn't exist */ 84 #define RIF_PWR_RESOURCE_WIO(x) ((x) + 6) 85 86 #define RIF_RCC_RESOURCE(x) (x) 87 88 #define RIF_RTC_RESOURCE(x) (x) 89 90 #define RIF_TAMP_RESOURCE(x) (x) 91 92 #define RIF_PER_ID_SHIFT 0 93 #define RIF_CFEN_SHIFT 8 94 #define RIF_SEM_EN_SHIFT 9 95 #define RIF_SCID_SHIFT 12 96 #define RIF_SEC_SHIFT 16 97 #define RIF_PRIV_SHIFT 17 98 #define RIF_LOCK_SHIFT 18 99 #define RIF_SEML_SHIFT 24 100 #define RIF_PERx_CID_SHIFT 8 101 #ifndef __ASSEMBLER__ 102 #define RIF_PER_ID_MASK GENMASK_32(7, 0) 103 #define RIF_SCID_MASK GENMASK_32(15, 12) 104 #define RIF_SEC_MASK BIT(16) 105 #define RIF_PRIV_MASK BIT(17) 106 #define RIF_LOCK_MASK BIT(18) 107 #define RIF_SEML_MASK GENMASK_32(31, 24) 108 #endif 109 110 #define RIF_PERx_CID_MASK (BIT(RIF_CFEN_SHIFT) | \ 111 BIT(RIF_SEM_EN_SHIFT) | \ 112 RIF_SCID_MASK | RIF_SEML_MASK) 113 114 #define RIFPROT(rifid, sem_list, lock, sec, priv, scid, sem_en, cfen) \ 115 (((sem_list) << RIF_SEML_SHIFT) | \ 116 ((lock) << RIF_LOCK_SHIFT) | \ 117 ((priv) << RIF_PRIV_SHIFT) | \ 118 ((sec) << RIF_SEC_SHIFT) | \ 119 ((scid) << RIF_SCID_SHIFT) | \ 120 ((sem_en) << RIF_SEM_EN_SHIFT) | \ 121 ((cfen) << RIF_CFEN_SHIFT) | \ 122 ((rifid) << RIF_PER_ID_SHIFT)) 123 124 #endif /* _DT_BINDINGS_FIREWALL_STM32MP25_RIF_H */ 125