1*ecbdfb72SGatien Chevallier /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2*ecbdfb72SGatien Chevallier /* 3*ecbdfb72SGatien Chevallier * Copyright (C) 2020-2024, STMicroelectronics - All Rights Reserved 4*ecbdfb72SGatien Chevallier */ 5*ecbdfb72SGatien Chevallier 6*ecbdfb72SGatien Chevallier #ifndef _DT_BINDINGS_FIREWALL_STM32MP15_TZC400_H 7*ecbdfb72SGatien Chevallier #define _DT_BINDINGS_FIREWALL_STM32MP15_TZC400_H 8*ecbdfb72SGatien Chevallier 9*ecbdfb72SGatien Chevallier #include <dt-bindings/firewall/tzc400.h> 10*ecbdfb72SGatien Chevallier 11*ecbdfb72SGatien Chevallier /* NSAID */ 12*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_A7_ID 0 13*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_M4_ID 1 14*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_LCD_ID 3 15*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_GPU_ID 4 16*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_MDMA_ID 5 17*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_DMA_ID 6 18*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_USB_HOST_ID 7 19*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_USB_OTG_ID 8 20*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_SDMMC_ID 9 21*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_ETH_ID 10 22*ecbdfb72SGatien Chevallier #define STM32MP1_TZC_DAP_ID 15 23*ecbdfb72SGatien Chevallier 24*ecbdfb72SGatien Chevallier #define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ 25*ecbdfb72SGatien Chevallier (TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ 26*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \ 27*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ 28*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \ 29*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ 30*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ 31*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ 32*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ 33*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ 34*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ 35*ecbdfb72SGatien Chevallier TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID)) 36*ecbdfb72SGatien Chevallier 37*ecbdfb72SGatien Chevallier #endif /* _DT_BINDINGS_FIREWALL_STM32MP15_TZC400_H */ 38