1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2022-2024, STMicroelectronics 4 */ 5 6 #ifndef _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H 7 #define _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H 8 9 /* define DECPROT modes */ 10 #define DECPROT_S_RW 0x0 11 #define DECPROT_NS_R_S_W 0x1 12 #define DECPROT_NS_RW 0x3 13 14 /* define DECPROT lock */ 15 #define DECPROT_UNLOCK 0x0 16 #define DECPROT_LOCK 0x1 17 18 /* define TZMA IDs*/ 19 #define ETZPC_TZMA0_ID 200 20 #define ETZPC_TZMA1_ID 201 21 22 /* define ETZPC ID */ 23 #define STM32MP1_ETZPC_VREFBUF_ID 0 24 #define STM32MP1_ETZPC_LPTIM2_ID 1 25 #define STM32MP1_ETZPC_LPTIM3_ID 2 26 #define STM32MP1_ETZPC_LTDC_ID 3 27 #define STM32MP1_ETZPC_DCMIPP_ID 4 28 #define STM32MP1_ETZPC_USBPHYCTRL_ID 5 29 #define STM32MP1_ETZPC_DDRCTRLPHY_ID 6 30 /* 7-11 Reserved */ 31 #define STM32MP1_ETZPC_IWDG1_ID 12 32 #define STM32MP1_ETZPC_STGENC_ID 13 33 /* 14-15 Reserved */ 34 #define STM32MP1_ETZPC_USART1_ID 16 35 #define STM32MP1_ETZPC_USART2_ID 17 36 #define STM32MP1_ETZPC_SPI4_ID 18 37 #define STM32MP1_ETZPC_SPI5_ID 19 38 #define STM32MP1_ETZPC_I2C3_ID 20 39 #define STM32MP1_ETZPC_I2C4_ID 21 40 #define STM32MP1_ETZPC_I2C5_ID 22 41 #define STM32MP1_ETZPC_TIM12_ID 23 42 #define STM32MP1_ETZPC_TIM13_ID 24 43 #define STM32MP1_ETZPC_TIM14_ID 25 44 #define STM32MP1_ETZPC_TIM15_ID 26 45 #define STM32MP1_ETZPC_TIM16_ID 27 46 #define STM32MP1_ETZPC_TIM17_ID 28 47 /* 29-31 Reserved */ 48 #define STM32MP1_ETZPC_ADC1_ID 32 49 #define STM32MP1_ETZPC_ADC2_ID 33 50 #define STM32MP1_ETZPC_OTG_ID 34 51 #define STM32MP1_ETZPC_TSC_ID 37 52 /* 38-39 Reserved */ 53 #define STM32MP1_ETZPC_RNG_ID 40 54 #define STM32MP1_ETZPC_HASH_ID 41 55 #define STM32MP1_ETZPC_CRYP_ID 42 56 #define STM32MP1_ETZPC_SAES_ID 43 57 #define STM32MP1_ETZPC_PKA_ID 44 58 #define STM32MP1_ETZPC_BKPSRAM_ID 45 59 /* 46-47 Reserved */ 60 #define STM32MP1_ETZPC_ETH1_ID 48 61 #define STM32MP1_ETZPC_ETH2_ID 49 62 #define STM32MP1_ETZPC_SDMMC1_ID 50 63 #define STM32MP1_ETZPC_SDMMC2_ID 51 64 /* 52 Reserved */ 65 #define STM32MP1_ETZPC_MCE_ID 53 66 #define STM32MP1_ETZPC_FMC_ID 54 67 #define STM32MP1_ETZPC_QSPI_ID 55 68 /* 56-59 Reserved */ 69 #define STM32MP1_ETZPC_SRAM1_ID 60 70 #define STM32MP1_ETZPC_SRAM2_ID 61 71 #define STM32MP1_ETZPC_SRAM3_ID 62 72 /* 63 Reserved */ 73 74 #define STM32MP1_ETZPC_MAX_ID 64 75 76 #define DECPROT(id, mode, lock) ((id) | ((mode) << ETZPC_MODE_SHIFT) | \ 77 ((lock) << ETZPC_LOCK_SHIFT)) 78 79 #define ETZPC_ID_MASK GENMASK_32(7, 0) 80 #define ETZPC_LOCK_MASK BIT(8) 81 #define ETZPC_LOCK_SHIFT 8 82 #define ETZPC_MODE_SHIFT 9 83 #define ETZPC_MODE_MASK GENMASK_32(31, 9) 84 85 #endif /* _DT_BINDINGS_FIREWALL_STM32MP13_ETZPC_H */ 86