1 /* 2 * Copyright (c) 2015, Linaro Limited 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, 12 * this list of conditions and the following disclaimer in the documentation 13 * and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 /* 28 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 29 * 30 * Redistribution and use in source and binary forms, with or without 31 * modification, are permitted provided that the following conditions are met: 32 * 33 * Redistributions of source code must retain the above copyright notice, this 34 * list of conditions and the following disclaimer. 35 * 36 * Redistributions in binary form must reproduce the above copyright notice, 37 * this list of conditions and the following disclaimer in the documentation 38 * and/or other materials provided with the distribution. 39 * 40 * Neither the name of ARM nor the names of its contributors may be used 41 * to endorse or promote products derived from this software without specific 42 * prior written permission. 43 * 44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 48 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 54 * POSSIBILITY OF SUCH DAMAGE. 55 */ 56 57 #ifndef __DRIVERS_TZC400_H 58 #define __DRIVERS_TZC400_H 59 60 #include <stdint.h> 61 #include <types_ext.h> 62 #include <trace_levels.h> 63 64 #define TZC400_REG_SIZE 0x1000 65 66 #define BUILD_CONFIG_OFF 0x000 67 #define ACTION_OFF 0x004 68 #define GATE_KEEPER_OFF 0x008 69 #define SPECULATION_CTRL_OFF 0x00c 70 #define INT_STATUS 0x010 71 #define INT_CLEAR 0x014 72 73 #define FAIL_ADDRESS_LOW_OFF 0x020 74 #define FAIL_ADDRESS_HIGH_OFF 0x024 75 #define FAIL_CONTROL_OFF 0x028 76 #define FAIL_ID 0x02c 77 78 #define REGION_BASE_LOW_OFF 0x100 79 #define REGION_BASE_HIGH_OFF 0x104 80 #define REGION_TOP_LOW_OFF 0x108 81 #define REGION_TOP_HIGH_OFF 0x10c 82 #define REGION_ATTRIBUTES_OFF 0x110 83 #define REGION_ID_ACCESS_OFF 0x114 84 #define REGION_NUM_OFF(region) (0x20 * region) 85 86 /* ID Registers */ 87 #define PID0_OFF 0xfe0 88 #define PID1_OFF 0xfe4 89 #define PID2_OFF 0xfe8 90 #define PID3_OFF 0xfec 91 #define PID4_OFF 0xfd0 92 #define PID5_OFF 0xfd4 93 #define PID6_OFF 0xfd8 94 #define PID7_OFF 0xfdc 95 #define CID0_OFF 0xff0 96 #define CID1_OFF 0xff4 97 #define CID2_OFF 0xff8 98 #define CID3_OFF 0xffc 99 100 #define BUILD_CONFIG_NF_SHIFT 24 101 #define BUILD_CONFIG_NF_MASK 0x3 102 #define BUILD_CONFIG_AW_SHIFT 8 103 #define BUILD_CONFIG_AW_MASK 0x3f 104 #define BUILD_CONFIG_NR_SHIFT 0 105 #define BUILD_CONFIG_NR_MASK 0x1f 106 107 /* Not describing the case where regions 1 to 8 overlap */ 108 #define ACTION_RV_SHIFT 0 109 #define ACTION_RV_MASK 0x3 110 #define ACTION_RV_LOWOK 0x0 111 #define ACTION_RV_LOWERR 0x1 112 #define ACTION_RV_HIGHOK 0x2 113 #define ACTION_RV_HIGHERR 0x3 114 115 /* 116 * Number of gate keepers is implementation defined. But we know the max for 117 * this device is 4. Get implementation details from BUILD_CONFIG. 118 */ 119 #define GATE_KEEPER_OS_SHIFT 16 120 #define GATE_KEEPER_OS_MASK 0xf 121 #define GATE_KEEPER_OR_SHIFT 0 122 #define GATE_KEEPER_OR_MASK 0xf 123 #define GATE_KEEPER_FILTER_MASK 0x1 124 125 /* Speculation is enabled by default. */ 126 #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) 127 #define SPECULATION_CTRL_READ_DISABLE (1 << 0) 128 129 /* Max number of filters allowed is 4. */ 130 #define INT_STATUS_OVERLAP_SHIFT 16 131 #define INT_STATUS_OVERLAP_MASK 0xf 132 #define INT_STATUS_OVERRUN_SHIFT 8 133 #define INT_STATUS_OVERRUN_MASK 0xf 134 #define INT_STATUS_STATUS_SHIFT 0 135 #define INT_STATUS_STATUS_MASK 0xf 136 137 #define INT_CLEAR_CLEAR_SHIFT 0 138 #define INT_CLEAR_CLEAR_MASK 0xf 139 140 #define FAIL_CONTROL_DIR_SHIFT (1 << 24) 141 #define FAIL_CONTROL_DIR_READ 0x0 142 #define FAIL_CONTROL_DIR_WRITE 0x1 143 #define FAIL_CONTROL_NS_SHIFT (1 << 21) 144 #define FAIL_CONTROL_NS_SECURE 0x0 145 #define FAIL_CONTROL_NS_NONSECURE 0x1 146 #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) 147 #define FAIL_CONTROL_PRIV_PRIV 0x0 148 #define FAIL_CONTROL_PRIV_UNPRIV 0x1 149 150 /* 151 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 152 * Platform should provide the value on initialisation. 153 */ 154 #define FAIL_ID_VNET_SHIFT 24 155 #define FAIL_ID_VNET_MASK 0xf 156 #define FAIL_ID_ID_SHIFT 0 157 158 /* Used along with 'enum tzc_region_attributes' below */ 159 #define REG_ATTR_SEC_SHIFT 30 160 #define REG_ATTR_F_EN_SHIFT 0 161 #define REG_ATTR_F_EN_MASK 0xf 162 #define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) 163 #define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ 164 REG_ATTR_F_EN_SHIFT) 165 166 #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 167 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 168 #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf 169 170 171 /* Macros for setting Region ID access permissions based on NSAID */ 172 #define TZC_REGION_ACCESS_RD(id) \ 173 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 174 REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 175 #define TZC_REGION_ACCESS_WR(id) \ 176 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 177 REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 178 #define TZC_REGION_ACCESS_RDWR(id) \ 179 (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) 180 181 /* Filters are bit mapped 0 to 3. */ 182 #define TZC400_COMPONENT_ID 0xb105f00d 183 184 /******************************************************************************* 185 * Function & variable prototypes 186 ******************************************************************************/ 187 188 /* 189 * What type of action is expected when an access violation occurs. 190 * The memory requested is zeroed. But we can also raise and event to 191 * let the system know it happened. 192 * We can raise an interrupt(INT) and/or cause an exception(ERR). 193 * TZC_ACTION_NONE - No interrupt, no Exception 194 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 195 * data abort 196 * TZC_ACTION_INT - Raise interrupt, no exception 197 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 198 * external data abort 199 */ 200 enum tzc_action { 201 TZC_ACTION_NONE = 0, 202 TZC_ACTION_ERR = 1, 203 TZC_ACTION_INT = 2, 204 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 205 }; 206 207 /* 208 * Controls secure access to a region. If not enabled secure access is not 209 * allowed to region. 210 */ 211 enum tzc_region_attributes { 212 TZC_REGION_S_NONE = 0, 213 TZC_REGION_S_RD = 1, 214 TZC_REGION_S_WR = 2, 215 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 216 }; 217 218 219 void tzc_init(vaddr_t base); 220 void tzc_configure_region(uint32_t filters, uint8_t region, 221 vaddr_t region_base, vaddr_t region_top, 222 enum tzc_region_attributes sec_attr, 223 uint32_t ns_device_access); 224 void tzc_enable_filters(void); 225 void tzc_disable_filters(void); 226 void tzc_set_action(enum tzc_action action); 227 228 #if TRACE_LEVEL >= TRACE_DEBUG 229 void tzc_dump_state(void); 230 #else 231 static inline void tzc_dump_state(void) 232 { 233 } 234 #endif 235 236 #endif /* __DRIVERS_TZC400_H */ 237