1 /* SPDX-License-Identifier: (BSD-2-Clause AND BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2015, Linaro Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 /* 29 * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 30 * 31 * Redistribution and use in source and binary forms, with or without 32 * modification, are permitted provided that the following conditions are met: 33 * 34 * Redistributions of source code must retain the above copyright notice, this 35 * list of conditions and the following disclaimer. 36 * 37 * Redistributions in binary form must reproduce the above copyright notice, 38 * this list of conditions and the following disclaimer in the documentation 39 * and/or other materials provided with the distribution. 40 * 41 * Neither the name of ARM nor the names of its contributors may be used 42 * to endorse or promote products derived from this software without specific 43 * prior written permission. 44 * 45 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 46 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 47 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 48 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 49 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 50 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 51 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 52 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 53 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 54 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 55 * POSSIBILITY OF SUCH DAMAGE. 56 */ 57 58 #ifndef __DRIVERS_TZC400_H 59 #define __DRIVERS_TZC400_H 60 61 #include <stdint.h> 62 #include <types_ext.h> 63 #include <trace_levels.h> 64 65 #define TZC400_REG_SIZE 0x1000 66 67 #define BUILD_CONFIG_OFF 0x000 68 #define ACTION_OFF 0x004 69 #define GATE_KEEPER_OFF 0x008 70 #define SPECULATION_CTRL_OFF 0x00c 71 #define INT_STATUS 0x010 72 #define INT_CLEAR 0x014 73 74 #define FAIL_ADDRESS_LOW_OFF 0x020 75 #define FAIL_ADDRESS_HIGH_OFF 0x024 76 #define FAIL_CONTROL_OFF 0x028 77 #define FAIL_ID 0x02c 78 79 #define REGION_BASE_LOW_OFF 0x100 80 #define REGION_BASE_HIGH_OFF 0x104 81 #define REGION_TOP_LOW_OFF 0x108 82 #define REGION_TOP_HIGH_OFF 0x10c 83 #define REGION_ATTRIBUTES_OFF 0x110 84 #define REGION_ID_ACCESS_OFF 0x114 85 #define REGION_NUM_OFF(region) (0x20 * region) 86 87 /* ID Registers */ 88 #define PID0_OFF 0xfe0 89 #define PID1_OFF 0xfe4 90 #define PID2_OFF 0xfe8 91 #define PID3_OFF 0xfec 92 #define PID4_OFF 0xfd0 93 #define PID5_OFF 0xfd4 94 #define PID6_OFF 0xfd8 95 #define PID7_OFF 0xfdc 96 #define CID0_OFF 0xff0 97 #define CID1_OFF 0xff4 98 #define CID2_OFF 0xff8 99 #define CID3_OFF 0xffc 100 101 #define BUILD_CONFIG_NF_SHIFT 24 102 #define BUILD_CONFIG_NF_MASK 0x3 103 #define BUILD_CONFIG_AW_SHIFT 8 104 #define BUILD_CONFIG_AW_MASK 0x3f 105 #define BUILD_CONFIG_NR_SHIFT 0 106 #define BUILD_CONFIG_NR_MASK 0x1f 107 108 /* Not describing the case where regions 1 to 8 overlap */ 109 #define ACTION_RV_SHIFT 0 110 #define ACTION_RV_MASK 0x3 111 #define ACTION_RV_LOWOK 0x0 112 #define ACTION_RV_LOWERR 0x1 113 #define ACTION_RV_HIGHOK 0x2 114 #define ACTION_RV_HIGHERR 0x3 115 116 /* 117 * Number of gate keepers is implementation defined. But we know the max for 118 * this device is 4. Get implementation details from BUILD_CONFIG. 119 */ 120 #define GATE_KEEPER_OS_SHIFT 16 121 #define GATE_KEEPER_OS_MASK 0xf 122 #define GATE_KEEPER_OR_SHIFT 0 123 #define GATE_KEEPER_OR_MASK 0xf 124 #define GATE_KEEPER_FILTER_MASK 0x1 125 126 /* Speculation is enabled by default. */ 127 #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) 128 #define SPECULATION_CTRL_READ_DISABLE (1 << 0) 129 130 /* Max number of filters allowed is 4. */ 131 #define INT_STATUS_OVERLAP_SHIFT 16 132 #define INT_STATUS_OVERLAP_MASK 0xf 133 #define INT_STATUS_OVERRUN_SHIFT 8 134 #define INT_STATUS_OVERRUN_MASK 0xf 135 #define INT_STATUS_STATUS_SHIFT 0 136 #define INT_STATUS_STATUS_MASK 0xf 137 138 #define INT_CLEAR_CLEAR_SHIFT 0 139 #define INT_CLEAR_CLEAR_MASK 0xf 140 141 #define FAIL_CONTROL_DIR_SHIFT (1 << 24) 142 #define FAIL_CONTROL_DIR_READ 0x0 143 #define FAIL_CONTROL_DIR_WRITE 0x1 144 #define FAIL_CONTROL_NS_SHIFT (1 << 21) 145 #define FAIL_CONTROL_NS_SECURE 0x0 146 #define FAIL_CONTROL_NS_NONSECURE 0x1 147 #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) 148 #define FAIL_CONTROL_PRIV_PRIV 0x0 149 #define FAIL_CONTROL_PRIV_UNPRIV 0x1 150 151 /* 152 * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 153 * Platform should provide the value on initialisation. 154 */ 155 #define FAIL_ID_VNET_SHIFT 24 156 #define FAIL_ID_VNET_MASK 0xf 157 #define FAIL_ID_ID_SHIFT 0 158 159 /* Used along with 'enum tzc_region_attributes' below */ 160 #define REG_ATTR_SEC_SHIFT 30 161 #define REG_ATTR_F_EN_SHIFT 0 162 #define REG_ATTR_F_EN_MASK 0xf 163 #define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) 164 #define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ 165 REG_ATTR_F_EN_SHIFT) 166 167 #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 168 #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 169 #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf 170 171 172 /* Macros for setting Region ID access permissions based on NSAID */ 173 #define TZC_REGION_ACCESS_RD(id) \ 174 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 175 REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 176 #define TZC_REGION_ACCESS_WR(id) \ 177 ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 178 REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 179 #define TZC_REGION_ACCESS_RDWR(id) \ 180 (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) 181 182 /* Filters are bit mapped 0 to 3. */ 183 #define TZC400_COMPONENT_ID 0xb105f00d 184 185 /******************************************************************************* 186 * Function & variable prototypes 187 ******************************************************************************/ 188 189 /* 190 * What type of action is expected when an access violation occurs. 191 * The memory requested is zeroed. But we can also raise and event to 192 * let the system know it happened. 193 * We can raise an interrupt(INT) and/or cause an exception(ERR). 194 * TZC_ACTION_NONE - No interrupt, no Exception 195 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 196 * data abort 197 * TZC_ACTION_INT - Raise interrupt, no exception 198 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 199 * external data abort 200 */ 201 enum tzc_action { 202 TZC_ACTION_NONE = 0, 203 TZC_ACTION_ERR = 1, 204 TZC_ACTION_INT = 2, 205 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 206 }; 207 208 /* 209 * Controls secure access to a region. If not enabled secure access is not 210 * allowed to region. 211 */ 212 enum tzc_region_attributes { 213 TZC_REGION_S_NONE = 0, 214 TZC_REGION_S_RD = 1, 215 TZC_REGION_S_WR = 2, 216 TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 217 }; 218 219 220 void tzc_init(vaddr_t base); 221 void tzc_configure_region(uint32_t filters, uint8_t region, 222 vaddr_t region_base, vaddr_t region_top, 223 enum tzc_region_attributes sec_attr, 224 uint32_t ns_device_access); 225 void tzc_enable_filters(void); 226 void tzc_disable_filters(void); 227 void tzc_set_action(enum tzc_action action); 228 229 #if TRACE_LEVEL >= TRACE_DEBUG 230 void tzc_dump_state(void); 231 #else 232 static inline void tzc_dump_state(void) 233 { 234 } 235 #endif 236 237 #endif /* __DRIVERS_TZC400_H */ 238