1*5d1638f3SJens Wiklander /* 2*5d1638f3SJens Wiklander * Copyright (c) 2015, Linaro Limited 3*5d1638f3SJens Wiklander * All rights reserved. 4*5d1638f3SJens Wiklander * 5*5d1638f3SJens Wiklander * Redistribution and use in source and binary forms, with or without 6*5d1638f3SJens Wiklander * modification, are permitted provided that the following conditions are met: 7*5d1638f3SJens Wiklander * 8*5d1638f3SJens Wiklander * 1. Redistributions of source code must retain the above copyright notice, 9*5d1638f3SJens Wiklander * this list of conditions and the following disclaimer. 10*5d1638f3SJens Wiklander * 11*5d1638f3SJens Wiklander * 2. Redistributions in binary form must reproduce the above copyright notice, 12*5d1638f3SJens Wiklander * this list of conditions and the following disclaimer in the documentation 13*5d1638f3SJens Wiklander * and/or other materials provided with the distribution. 14*5d1638f3SJens Wiklander * 15*5d1638f3SJens Wiklander * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16*5d1638f3SJens Wiklander * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17*5d1638f3SJens Wiklander * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18*5d1638f3SJens Wiklander * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 19*5d1638f3SJens Wiklander * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20*5d1638f3SJens Wiklander * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21*5d1638f3SJens Wiklander * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22*5d1638f3SJens Wiklander * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23*5d1638f3SJens Wiklander * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24*5d1638f3SJens Wiklander * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25*5d1638f3SJens Wiklander * POSSIBILITY OF SUCH DAMAGE. 26*5d1638f3SJens Wiklander */ 27*5d1638f3SJens Wiklander /* 28*5d1638f3SJens Wiklander * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. 29*5d1638f3SJens Wiklander * 30*5d1638f3SJens Wiklander * Redistribution and use in source and binary forms, with or without 31*5d1638f3SJens Wiklander * modification, are permitted provided that the following conditions are met: 32*5d1638f3SJens Wiklander * 33*5d1638f3SJens Wiklander * Redistributions of source code must retain the above copyright notice, this 34*5d1638f3SJens Wiklander * list of conditions and the following disclaimer. 35*5d1638f3SJens Wiklander * 36*5d1638f3SJens Wiklander * Redistributions in binary form must reproduce the above copyright notice, 37*5d1638f3SJens Wiklander * this list of conditions and the following disclaimer in the documentation 38*5d1638f3SJens Wiklander * and/or other materials provided with the distribution. 39*5d1638f3SJens Wiklander * 40*5d1638f3SJens Wiklander * Neither the name of ARM nor the names of its contributors may be used 41*5d1638f3SJens Wiklander * to endorse or promote products derived from this software without specific 42*5d1638f3SJens Wiklander * prior written permission. 43*5d1638f3SJens Wiklander * 44*5d1638f3SJens Wiklander * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 45*5d1638f3SJens Wiklander * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 46*5d1638f3SJens Wiklander * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 47*5d1638f3SJens Wiklander * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 48*5d1638f3SJens Wiklander * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 49*5d1638f3SJens Wiklander * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 50*5d1638f3SJens Wiklander * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 51*5d1638f3SJens Wiklander * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 52*5d1638f3SJens Wiklander * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 53*5d1638f3SJens Wiklander * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 54*5d1638f3SJens Wiklander * POSSIBILITY OF SUCH DAMAGE. 55*5d1638f3SJens Wiklander */ 56*5d1638f3SJens Wiklander 57*5d1638f3SJens Wiklander #ifndef __DRIVERS_TZC400_H 58*5d1638f3SJens Wiklander #define __DRIVERS_TZC400_H 59*5d1638f3SJens Wiklander 60*5d1638f3SJens Wiklander #include <stdint.h> 61*5d1638f3SJens Wiklander #include <types_ext.h> 62*5d1638f3SJens Wiklander #include <trace_levels.h> 63*5d1638f3SJens Wiklander 64*5d1638f3SJens Wiklander #define TZC400_REG_SIZE 0x1000 65*5d1638f3SJens Wiklander 66*5d1638f3SJens Wiklander #define BUILD_CONFIG_OFF 0x000 67*5d1638f3SJens Wiklander #define ACTION_OFF 0x004 68*5d1638f3SJens Wiklander #define GATE_KEEPER_OFF 0x008 69*5d1638f3SJens Wiklander #define SPECULATION_CTRL_OFF 0x00c 70*5d1638f3SJens Wiklander #define INT_STATUS 0x010 71*5d1638f3SJens Wiklander #define INT_CLEAR 0x014 72*5d1638f3SJens Wiklander 73*5d1638f3SJens Wiklander #define FAIL_ADDRESS_LOW_OFF 0x020 74*5d1638f3SJens Wiklander #define FAIL_ADDRESS_HIGH_OFF 0x024 75*5d1638f3SJens Wiklander #define FAIL_CONTROL_OFF 0x028 76*5d1638f3SJens Wiklander #define FAIL_ID 0x02c 77*5d1638f3SJens Wiklander 78*5d1638f3SJens Wiklander #define REGION_BASE_LOW_OFF 0x100 79*5d1638f3SJens Wiklander #define REGION_BASE_HIGH_OFF 0x104 80*5d1638f3SJens Wiklander #define REGION_TOP_LOW_OFF 0x108 81*5d1638f3SJens Wiklander #define REGION_TOP_HIGH_OFF 0x10c 82*5d1638f3SJens Wiklander #define REGION_ATTRIBUTES_OFF 0x110 83*5d1638f3SJens Wiklander #define REGION_ID_ACCESS_OFF 0x114 84*5d1638f3SJens Wiklander #define REGION_NUM_OFF(region) (0x20 * region) 85*5d1638f3SJens Wiklander 86*5d1638f3SJens Wiklander /* ID Registers */ 87*5d1638f3SJens Wiklander #define PID0_OFF 0xfe0 88*5d1638f3SJens Wiklander #define PID1_OFF 0xfe4 89*5d1638f3SJens Wiklander #define PID2_OFF 0xfe8 90*5d1638f3SJens Wiklander #define PID3_OFF 0xfec 91*5d1638f3SJens Wiklander #define PID4_OFF 0xfd0 92*5d1638f3SJens Wiklander #define PID5_OFF 0xfd4 93*5d1638f3SJens Wiklander #define PID6_OFF 0xfd8 94*5d1638f3SJens Wiklander #define PID7_OFF 0xfdc 95*5d1638f3SJens Wiklander #define CID0_OFF 0xff0 96*5d1638f3SJens Wiklander #define CID1_OFF 0xff4 97*5d1638f3SJens Wiklander #define CID2_OFF 0xff8 98*5d1638f3SJens Wiklander #define CID3_OFF 0xffc 99*5d1638f3SJens Wiklander 100*5d1638f3SJens Wiklander #define BUILD_CONFIG_NF_SHIFT 24 101*5d1638f3SJens Wiklander #define BUILD_CONFIG_NF_MASK 0x3 102*5d1638f3SJens Wiklander #define BUILD_CONFIG_AW_SHIFT 8 103*5d1638f3SJens Wiklander #define BUILD_CONFIG_AW_MASK 0x3f 104*5d1638f3SJens Wiklander #define BUILD_CONFIG_NR_SHIFT 0 105*5d1638f3SJens Wiklander #define BUILD_CONFIG_NR_MASK 0x1f 106*5d1638f3SJens Wiklander 107*5d1638f3SJens Wiklander /* Not describing the case where regions 1 to 8 overlap */ 108*5d1638f3SJens Wiklander #define ACTION_RV_SHIFT 0 109*5d1638f3SJens Wiklander #define ACTION_RV_MASK 0x3 110*5d1638f3SJens Wiklander #define ACTION_RV_LOWOK 0x0 111*5d1638f3SJens Wiklander #define ACTION_RV_LOWERR 0x1 112*5d1638f3SJens Wiklander #define ACTION_RV_HIGHOK 0x2 113*5d1638f3SJens Wiklander #define ACTION_RV_HIGHERR 0x3 114*5d1638f3SJens Wiklander 115*5d1638f3SJens Wiklander /* 116*5d1638f3SJens Wiklander * Number of gate keepers is implementation defined. But we know the max for 117*5d1638f3SJens Wiklander * this device is 4. Get implementation details from BUILD_CONFIG. 118*5d1638f3SJens Wiklander */ 119*5d1638f3SJens Wiklander #define GATE_KEEPER_OS_SHIFT 16 120*5d1638f3SJens Wiklander #define GATE_KEEPER_OS_MASK 0xf 121*5d1638f3SJens Wiklander #define GATE_KEEPER_OR_SHIFT 0 122*5d1638f3SJens Wiklander #define GATE_KEEPER_OR_MASK 0xf 123*5d1638f3SJens Wiklander #define GATE_KEEPER_FILTER_MASK 0x1 124*5d1638f3SJens Wiklander 125*5d1638f3SJens Wiklander /* Speculation is enabled by default. */ 126*5d1638f3SJens Wiklander #define SPECULATION_CTRL_WRITE_DISABLE (1 << 1) 127*5d1638f3SJens Wiklander #define SPECULATION_CTRL_READ_DISABLE (1 << 0) 128*5d1638f3SJens Wiklander 129*5d1638f3SJens Wiklander /* Max number of filters allowed is 4. */ 130*5d1638f3SJens Wiklander #define INT_STATUS_OVERLAP_SHIFT 16 131*5d1638f3SJens Wiklander #define INT_STATUS_OVERLAP_MASK 0xf 132*5d1638f3SJens Wiklander #define INT_STATUS_OVERRUN_SHIFT 8 133*5d1638f3SJens Wiklander #define INT_STATUS_OVERRUN_MASK 0xf 134*5d1638f3SJens Wiklander #define INT_STATUS_STATUS_SHIFT 0 135*5d1638f3SJens Wiklander #define INT_STATUS_STATUS_MASK 0xf 136*5d1638f3SJens Wiklander 137*5d1638f3SJens Wiklander #define INT_CLEAR_CLEAR_SHIFT 0 138*5d1638f3SJens Wiklander #define INT_CLEAR_CLEAR_MASK 0xf 139*5d1638f3SJens Wiklander 140*5d1638f3SJens Wiklander #define FAIL_CONTROL_DIR_SHIFT (1 << 24) 141*5d1638f3SJens Wiklander #define FAIL_CONTROL_DIR_READ 0x0 142*5d1638f3SJens Wiklander #define FAIL_CONTROL_DIR_WRITE 0x1 143*5d1638f3SJens Wiklander #define FAIL_CONTROL_NS_SHIFT (1 << 21) 144*5d1638f3SJens Wiklander #define FAIL_CONTROL_NS_SECURE 0x0 145*5d1638f3SJens Wiklander #define FAIL_CONTROL_NS_NONSECURE 0x1 146*5d1638f3SJens Wiklander #define FAIL_CONTROL_PRIV_SHIFT (1 << 20) 147*5d1638f3SJens Wiklander #define FAIL_CONTROL_PRIV_PRIV 0x0 148*5d1638f3SJens Wiklander #define FAIL_CONTROL_PRIV_UNPRIV 0x1 149*5d1638f3SJens Wiklander 150*5d1638f3SJens Wiklander /* 151*5d1638f3SJens Wiklander * FAIL_ID_ID_MASK depends on AID_WIDTH which is platform specific. 152*5d1638f3SJens Wiklander * Platform should provide the value on initialisation. 153*5d1638f3SJens Wiklander */ 154*5d1638f3SJens Wiklander #define FAIL_ID_VNET_SHIFT 24 155*5d1638f3SJens Wiklander #define FAIL_ID_VNET_MASK 0xf 156*5d1638f3SJens Wiklander #define FAIL_ID_ID_SHIFT 0 157*5d1638f3SJens Wiklander 158*5d1638f3SJens Wiklander /* Used along with 'enum tzc_region_attributes' below */ 159*5d1638f3SJens Wiklander #define REG_ATTR_SEC_SHIFT 30 160*5d1638f3SJens Wiklander #define REG_ATTR_F_EN_SHIFT 0 161*5d1638f3SJens Wiklander #define REG_ATTR_F_EN_MASK 0xf 162*5d1638f3SJens Wiklander #define REG_ATTR_FILTER_BIT(x) ((1 << x) << REG_ATTR_F_EN_SHIFT) 163*5d1638f3SJens Wiklander #define REG_ATTR_FILTER_BIT_ALL (REG_ATTR_F_EN_MASK << \ 164*5d1638f3SJens Wiklander REG_ATTR_F_EN_SHIFT) 165*5d1638f3SJens Wiklander 166*5d1638f3SJens Wiklander #define REGION_ID_ACCESS_NSAID_WR_EN_SHIFT 16 167*5d1638f3SJens Wiklander #define REGION_ID_ACCESS_NSAID_RD_EN_SHIFT 0 168*5d1638f3SJens Wiklander #define REGION_ID_ACCESS_NSAID_ID_MASK 0xf 169*5d1638f3SJens Wiklander 170*5d1638f3SJens Wiklander 171*5d1638f3SJens Wiklander /* Macros for setting Region ID access permissions based on NSAID */ 172*5d1638f3SJens Wiklander #define TZC_REGION_ACCESS_RD(id) \ 173*5d1638f3SJens Wiklander ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 174*5d1638f3SJens Wiklander REGION_ID_ACCESS_NSAID_RD_EN_SHIFT) 175*5d1638f3SJens Wiklander #define TZC_REGION_ACCESS_WR(id) \ 176*5d1638f3SJens Wiklander ((1 << (id & REGION_ID_ACCESS_NSAID_ID_MASK)) << \ 177*5d1638f3SJens Wiklander REGION_ID_ACCESS_NSAID_WR_EN_SHIFT) 178*5d1638f3SJens Wiklander #define TZC_REGION_ACCESS_RDWR(id) \ 179*5d1638f3SJens Wiklander (TZC_REGION_ACCESS_RD(id) | TZC_REGION_ACCESS_WR(id)) 180*5d1638f3SJens Wiklander 181*5d1638f3SJens Wiklander /* Filters are bit mapped 0 to 3. */ 182*5d1638f3SJens Wiklander #define TZC400_COMPONENT_ID 0xb105f00d 183*5d1638f3SJens Wiklander 184*5d1638f3SJens Wiklander /******************************************************************************* 185*5d1638f3SJens Wiklander * Function & variable prototypes 186*5d1638f3SJens Wiklander ******************************************************************************/ 187*5d1638f3SJens Wiklander 188*5d1638f3SJens Wiklander /* 189*5d1638f3SJens Wiklander * What type of action is expected when an access violation occurs. 190*5d1638f3SJens Wiklander * The memory requested is zeroed. But we can also raise and event to 191*5d1638f3SJens Wiklander * let the system know it happened. 192*5d1638f3SJens Wiklander * We can raise an interrupt(INT) and/or cause an exception(ERR). 193*5d1638f3SJens Wiklander * TZC_ACTION_NONE - No interrupt, no Exception 194*5d1638f3SJens Wiklander * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 195*5d1638f3SJens Wiklander * data abort 196*5d1638f3SJens Wiklander * TZC_ACTION_INT - Raise interrupt, no exception 197*5d1638f3SJens Wiklander * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 198*5d1638f3SJens Wiklander * external data abort 199*5d1638f3SJens Wiklander */ 200*5d1638f3SJens Wiklander enum tzc_action { 201*5d1638f3SJens Wiklander TZC_ACTION_NONE = 0, 202*5d1638f3SJens Wiklander TZC_ACTION_ERR = 1, 203*5d1638f3SJens Wiklander TZC_ACTION_INT = 2, 204*5d1638f3SJens Wiklander TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 205*5d1638f3SJens Wiklander }; 206*5d1638f3SJens Wiklander 207*5d1638f3SJens Wiklander /* 208*5d1638f3SJens Wiklander * Controls secure access to a region. If not enabled secure access is not 209*5d1638f3SJens Wiklander * allowed to region. 210*5d1638f3SJens Wiklander */ 211*5d1638f3SJens Wiklander enum tzc_region_attributes { 212*5d1638f3SJens Wiklander TZC_REGION_S_NONE = 0, 213*5d1638f3SJens Wiklander TZC_REGION_S_RD = 1, 214*5d1638f3SJens Wiklander TZC_REGION_S_WR = 2, 215*5d1638f3SJens Wiklander TZC_REGION_S_RDWR = (TZC_REGION_S_RD | TZC_REGION_S_WR) 216*5d1638f3SJens Wiklander }; 217*5d1638f3SJens Wiklander 218*5d1638f3SJens Wiklander 219*5d1638f3SJens Wiklander void tzc_init(vaddr_t base); 220*5d1638f3SJens Wiklander void tzc_configure_region(uint32_t filters, uint8_t region, 221*5d1638f3SJens Wiklander vaddr_t region_base, vaddr_t region_top, 222*5d1638f3SJens Wiklander enum tzc_region_attributes sec_attr, 223*5d1638f3SJens Wiklander uint32_t ns_device_access); 224*5d1638f3SJens Wiklander void tzc_enable_filters(void); 225*5d1638f3SJens Wiklander void tzc_disable_filters(void); 226*5d1638f3SJens Wiklander void tzc_set_action(enum tzc_action action); 227*5d1638f3SJens Wiklander 228*5d1638f3SJens Wiklander #if TRACE_LEVEL >= TRACE_DEBUG 229*5d1638f3SJens Wiklander void tzc_dump_state(void); 230*5d1638f3SJens Wiklander #else 231*5d1638f3SJens Wiklander static inline void tzc_dump_state(void) 232*5d1638f3SJens Wiklander { 233*5d1638f3SJens Wiklander } 234*5d1638f3SJens Wiklander #endif 235*5d1638f3SJens Wiklander 236*5d1638f3SJens Wiklander #endif /* __DRIVERS_TZC400_H */ 237