1 /* 2 * Copyright 2017 NXP 3 * All rights reserved. 4 * 5 * Peng Fan <peng.fan@nxp.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 12 * 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation 15 * and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 21 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 * POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #ifndef __DRIVERS_TZC380_H 31 #define __DRIVERS_TZC380_H 32 33 #include <stdint.h> 34 #include <trace_levels.h> 35 #include <types_ext.h> 36 #include <util.h> 37 38 #define TZC400_REG_SIZE 0x1000 39 40 #define BUILD_CONFIG_OFF 0x000 41 #define ACTION_OFF 0x004 42 #define LOCKDOWN_RANGE_OFF 0x008 43 #define LOCKDOWN_SELECT_OFF 0x00C 44 #define INT_STATUS 0x010 45 #define INT_CLEAR 0x014 46 47 #define FAIL_ADDRESS_LOW_OFF 0x020 48 #define FAIL_ADDRESS_HIGH_OFF 0x024 49 #define FAIL_CONTROL_OFF 0x028 50 #define FAIL_ID 0x02c 51 52 #define SPECULATION_CTRL_OFF 0x030 53 #define SECURITY_INV_EN_OFF 0x034 54 55 #define REGION_SETUP_LOW_OFF(n) (0x100 + n * 0x10) 56 #define REGION_SETUP_HIGH_OFF(n) (0x104 + n * 0x10) 57 #define REGION_ATTRIBUTES_OFF(n) (0x108 + n * 0x10) 58 59 /* ID Registers */ 60 #define PID0_OFF 0xfe0 61 #define PID1_OFF 0xfe4 62 #define PID2_OFF 0xfe8 63 #define PID3_OFF 0xfec 64 #define PID4_OFF 0xfd0 65 #define CID0_OFF 0xff0 66 #define CID1_OFF 0xff4 67 #define CID2_OFF 0xff8 68 #define CID3_OFF 0xffc 69 70 #define BUILD_CONFIG_AW_SHIFT 8 71 #define BUILD_CONFIG_AW_MASK 0x3f 72 #define BUILD_CONFIG_NR_SHIFT 0 73 #define BUILD_CONFIG_NR_MASK 0xf 74 75 #define ACTION_RV_SHIFT 0 76 #define ACTION_RV_MASK 0x3 77 #define ACTION_RV_LOWOK 0x0 78 #define ACTION_RV_LOWERR 0x1 79 #define ACTION_RV_HIGHOK 0x2 80 #define ACTION_RV_HIGHERR 0x3 81 82 /* Speculation is enabled by default. */ 83 #define SPECULATION_CTRL_WRITE_DISABLE BIT(1) 84 #define SPECULATION_CTRL_READ_DISABLE BIT(0) 85 86 #define INT_STATUS_OVERRUN_SHIFT 1 87 #define INT_STATUS_OVERRUN_MASK 0x1 88 #define INT_STATUS_STATUS_SHIFT 0 89 #define INT_STATUS_STATUS_MASK 0x1 90 91 #define INT_CLEAR_CLEAR_SHIFT 0 92 #define INT_CLEAR_CLEAR_MASK 0x1 93 94 #define TZC380_COMPONENT_ID 0xb105f00d 95 #define TZC380_PERIPH_ID_LOW 0x001bb380 96 #define TZC380_PERIPH_ID_HIGH 0x00000004 97 98 /******************************************************************************* 99 * Function & variable prototypes 100 ******************************************************************************/ 101 102 /* 103 * What type of action is expected when an access violation occurs. 104 * The memory requested is zeroed. But we can also raise and event to 105 * let the system know it happened. 106 * We can raise an interrupt(INT) and/or cause an exception(ERR). 107 * TZC_ACTION_NONE - No interrupt, no Exception 108 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 109 * data abort 110 * TZC_ACTION_INT - Raise interrupt, no exception 111 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 112 * external data abort 113 */ 114 enum tzc_action { 115 TZC_ACTION_NONE = 0, 116 TZC_ACTION_ERR = 1, 117 TZC_ACTION_INT = 2, 118 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 119 }; 120 121 122 #define TZC_SP_NS_W BIT(0) 123 #define TZC_SP_NS_R BIT(1) 124 #define TZC_SP_S_W BIT(2) 125 #define TZC_SP_S_R BIT(3) 126 127 #define TZC_ATTR_SP_SHIFT 28 128 #define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \ 129 TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT) 130 #define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \ 131 TZC_ATTR_SP_SHIFT) 132 #define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \ 133 TZC_ATTR_SP_SHIFT) 134 135 #define TZC_REGION_SIZE_32K 0xe 136 #define TZC_REGION_SIZE_64K 0xf 137 #define TZC_REGION_SIZE_128K 0x10 138 #define TZC_REGION_SIZE_256K 0x11 139 #define TZC_REGION_SIZE_512K 0x12 140 #define TZC_REGION_SIZE_1M 0x13 141 #define TZC_REGION_SIZE_2M 0x14 142 #define TZC_REGION_SIZE_4M 0x15 143 #define TZC_REGION_SIZE_8M 0x16 144 #define TZC_REGION_SIZE_16M 0x17 145 #define TZC_REGION_SIZE_32M 0x18 146 #define TZC_REGION_SIZE_64M 0x19 147 #define TZC_REGION_SIZE_128M 0x1a 148 #define TZC_REGION_SIZE_256M 0x1b 149 #define TZC_REGION_SIZE_512M 0x1c 150 #define TZC_REGION_SIZE_1G 0x1d 151 #define TZC_REGION_SIZE_2G 0x1e 152 #define TZC_REGION_SIZE_4G 0x1f 153 #define TZC_REGION_SIZE_8G 0x20 154 #define TZC_REGION_SIZE_16G 0x21 155 #define TZC_REGION_SIZE_32G 0x22 156 #define TZC_REGION_SIZE_64G 0x23 157 #define TZC_REGION_SIZE_128G 0x24 158 #define TZC_REGION_SIZE_256G 0x25 159 #define TZC_REGION_SIZE_512G 0x26 160 #define TZC_REGION_SIZE_1T 0x27 161 #define TZC_REGION_SIZE_2T 0x28 162 #define TZC_REGION_SIZE_4T 0x29 163 #define TZC_REGION_SIZE_8T 0x2a 164 #define TZC_REGION_SIZE_16T 0x2b 165 #define TZC_REGION_SIZE_32T 0x2c 166 #define TZC_REGION_SIZE_64T 0x2d 167 #define TZC_REGION_SIZE_128T 0x2e 168 #define TZC_REGION_SIZE_256T 0x2f 169 #define TZC_REGION_SIZE_512T 0x30 170 #define TZC_REGION_SIZE_1P 0x31 171 #define TZC_REGION_SIZE_2P 0x32 172 #define TZC_REGION_SIZE_4P 0x33 173 #define TZC_REGION_SIZE_8P 0x34 174 #define TZC_REGION_SIZE_16P 0x35 175 #define TZC_REGION_SIZE_32P 0x36 176 #define TZC_REGION_SIZE_64P 0x37 177 #define TZC_REGION_SIZE_128P 0x38 178 #define TZC_REGION_SIZE_256P 0x39 179 #define TZC_REGION_SIZE_512P 0x3a 180 #define TZC_REGION_SIZE_1E 0x3b 181 #define TZC_REGION_SIZE_2E 0x3c 182 #define TZC_REGION_SIZE_4E 0x3d 183 #define TZC_REGION_SIZE_8E 0x3e 184 #define TZC_REGION_SIZE_16E 0x3f 185 186 #define TZC_REGION_SIZE_SHIFT 0x1 187 #define TZC_REGION_SIZE_MASK GENMASK_32(6, 1) 188 #define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT) 189 190 #define TZC_ATTR_REGION_EN_SHIFT 0x0 191 #define TZC_ATTR_REGION_EN_MASK 0x1 192 193 #define TZC_ATTR_REGION_EN 194 #define TZC_ATTR_REGION_ENABLE 0x1 195 #define TZC_ATTR_REGION_DISABLE 0x0 196 197 void tzc_init(vaddr_t base); 198 void tzc_configure_region(uint8_t region, vaddr_t region_base, size_t size); 199 void tzc_set_action(enum tzc_action action); 200 201 #if TRACE_LEVEL >= TRACE_DEBUG 202 void tzc_dump_state(void); 203 #else 204 static inline void tzc_dump_state(void) 205 { 206 } 207 #endif 208 209 #endif /* __DRIVERS_TZC400_H */ 210