1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright 2017 NXP 4 * All rights reserved. 5 * 6 * Peng Fan <peng.fan@nxp.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 14 * 2. Redistributions in binary form must reproduce the above copyright notice, 15 * this list of conditions and the following disclaimer in the documentation 16 * and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __DRIVERS_TZC380_H 32 #define __DRIVERS_TZC380_H 33 34 #include <stdint.h> 35 #include <tee_api_types.h> 36 #include <trace_levels.h> 37 #include <types_ext.h> 38 #include <util.h> 39 40 #define TZC400_REG_SIZE 0x1000 41 42 #define BUILD_CONFIG_OFF 0x000 43 #define ACTION_OFF 0x004 44 #define LOCKDOWN_RANGE_OFF 0x008 45 #define LOCKDOWN_SELECT_OFF 0x00C 46 #define INT_STATUS 0x010 47 #define INT_CLEAR 0x014 48 49 #define FAIL_ADDRESS_LOW_OFF 0x020 50 #define FAIL_ADDRESS_HIGH_OFF 0x024 51 #define FAIL_CONTROL_OFF 0x028 52 #define FAIL_ID 0x02c 53 54 #define SPECULATION_CTRL_OFF 0x030 55 #define SECURITY_INV_EN_OFF 0x034 56 57 #define REGION_SETUP_LOW_OFF(n) (0x100 + n * 0x10) 58 #define REGION_SETUP_HIGH_OFF(n) (0x104 + n * 0x10) 59 #define REGION_ATTRIBUTES_OFF(n) (0x108 + n * 0x10) 60 61 /* ID Registers */ 62 #define PID0_OFF 0xfe0 63 #define PID1_OFF 0xfe4 64 #define PID2_OFF 0xfe8 65 #define PID3_OFF 0xfec 66 #define PID4_OFF 0xfd0 67 #define CID0_OFF 0xff0 68 #define CID1_OFF 0xff4 69 #define CID2_OFF 0xff8 70 #define CID3_OFF 0xffc 71 72 #define BUILD_CONFIG_AW_SHIFT 8 73 #define BUILD_CONFIG_AW_MASK 0x3f 74 #define BUILD_CONFIG_NR_SHIFT 0 75 #define BUILD_CONFIG_NR_MASK 0xf 76 77 #define ACTION_RV_SHIFT 0 78 #define ACTION_RV_MASK 0x3 79 #define ACTION_RV_LOWOK 0x0 80 #define ACTION_RV_LOWERR 0x1 81 #define ACTION_RV_HIGHOK 0x2 82 #define ACTION_RV_HIGHERR 0x3 83 84 /* Speculation is enabled by default. */ 85 #define SPECULATION_CTRL_WRITE_DISABLE BIT(1) 86 #define SPECULATION_CTRL_READ_DISABLE BIT(0) 87 88 #define INT_STATUS_OVERRUN_SHIFT 1 89 #define INT_STATUS_OVERRUN_MASK 0x1 90 #define INT_STATUS_STATUS_SHIFT 0 91 #define INT_STATUS_STATUS_MASK 0x1 92 93 #define INT_CLEAR_CLEAR_SHIFT 0 94 #define INT_CLEAR_CLEAR_MASK 0x1 95 96 #define TZC380_COMPONENT_ID 0xb105f00d 97 #define TZC380_PERIPH_ID_LOW 0x001bb380 98 #define TZC380_PERIPH_ID_HIGH 0x00000004 99 100 /******************************************************************************* 101 * Function & variable prototypes 102 ******************************************************************************/ 103 104 /* 105 * What type of action is expected when an access violation occurs. 106 * The memory requested is zeroed. But we can also raise and event to 107 * let the system know it happened. 108 * We can raise an interrupt(INT) and/or cause an exception(ERR). 109 * TZC_ACTION_NONE - No interrupt, no Exception 110 * TZC_ACTION_ERR - No interrupt, raise exception -> sync external 111 * data abort 112 * TZC_ACTION_INT - Raise interrupt, no exception 113 * TZC_ACTION_ERR_INT - Raise interrupt, raise exception -> sync 114 * external data abort 115 */ 116 enum tzc_action { 117 TZC_ACTION_NONE = 0, 118 TZC_ACTION_ERR = 1, 119 TZC_ACTION_INT = 2, 120 TZC_ACTION_ERR_INT = (TZC_ACTION_ERR | TZC_ACTION_INT) 121 }; 122 123 124 #define TZC_SP_NS_W BIT(0) 125 #define TZC_SP_NS_R BIT(1) 126 #define TZC_SP_S_W BIT(2) 127 #define TZC_SP_S_R BIT(3) 128 129 #define TZC_ATTR_SP_SHIFT 28 130 #define TZC_ATTR_SP_MASK GENMASK_32(31, 28) 131 #define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \ 132 TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT) 133 #define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \ 134 TZC_ATTR_SP_SHIFT) 135 #define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \ 136 TZC_ATTR_SP_SHIFT) 137 138 #define TZC_REGION_SIZE_32K 0xe 139 #define TZC_REGION_SIZE_64K 0xf 140 #define TZC_REGION_SIZE_128K 0x10 141 #define TZC_REGION_SIZE_256K 0x11 142 #define TZC_REGION_SIZE_512K 0x12 143 #define TZC_REGION_SIZE_1M 0x13 144 #define TZC_REGION_SIZE_2M 0x14 145 #define TZC_REGION_SIZE_4M 0x15 146 #define TZC_REGION_SIZE_8M 0x16 147 #define TZC_REGION_SIZE_16M 0x17 148 #define TZC_REGION_SIZE_32M 0x18 149 #define TZC_REGION_SIZE_64M 0x19 150 #define TZC_REGION_SIZE_128M 0x1a 151 #define TZC_REGION_SIZE_256M 0x1b 152 #define TZC_REGION_SIZE_512M 0x1c 153 #define TZC_REGION_SIZE_1G 0x1d 154 #define TZC_REGION_SIZE_2G 0x1e 155 #define TZC_REGION_SIZE_4G 0x1f 156 #define TZC_REGION_SIZE_8G 0x20 157 #define TZC_REGION_SIZE_16G 0x21 158 #define TZC_REGION_SIZE_32G 0x22 159 #define TZC_REGION_SIZE_64G 0x23 160 #define TZC_REGION_SIZE_128G 0x24 161 #define TZC_REGION_SIZE_256G 0x25 162 #define TZC_REGION_SIZE_512G 0x26 163 #define TZC_REGION_SIZE_1T 0x27 164 #define TZC_REGION_SIZE_2T 0x28 165 #define TZC_REGION_SIZE_4T 0x29 166 #define TZC_REGION_SIZE_8T 0x2a 167 #define TZC_REGION_SIZE_16T 0x2b 168 #define TZC_REGION_SIZE_32T 0x2c 169 #define TZC_REGION_SIZE_64T 0x2d 170 #define TZC_REGION_SIZE_128T 0x2e 171 #define TZC_REGION_SIZE_256T 0x2f 172 #define TZC_REGION_SIZE_512T 0x30 173 #define TZC_REGION_SIZE_1P 0x31 174 #define TZC_REGION_SIZE_2P 0x32 175 #define TZC_REGION_SIZE_4P 0x33 176 #define TZC_REGION_SIZE_8P 0x34 177 #define TZC_REGION_SIZE_16P 0x35 178 #define TZC_REGION_SIZE_32P 0x36 179 #define TZC_REGION_SIZE_64P 0x37 180 #define TZC_REGION_SIZE_128P 0x38 181 #define TZC_REGION_SIZE_256P 0x39 182 #define TZC_REGION_SIZE_512P 0x3a 183 #define TZC_REGION_SIZE_1E 0x3b 184 #define TZC_REGION_SIZE_2E 0x3c 185 #define TZC_REGION_SIZE_4E 0x3d 186 #define TZC_REGION_SIZE_8E 0x3e 187 #define TZC_REGION_SIZE_16E 0x3f 188 189 #define TZC_REGION_SIZE_SHIFT 0x1 190 #define TZC_REGION_SIZE_MASK GENMASK_32(6, 1) 191 #define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT) 192 193 #define TZC_SUBREGION_DIS_SHIFT 8 194 #define TZC_SUBREGION_DIS_MASK GENMASK_32(15, 8) 195 #define TZC_ATTR_SUBREGION_DIS(subreg) \ 196 (BIT((subreg) + TZC_SUBREGION_DIS_SHIFT) & \ 197 TZC_SUBREGION_DIS_MASK) 198 199 #define TZC_ATTR_REGION_EN_SHIFT 0x0 200 #define TZC_ATTR_REGION_EN_MASK 0x1 201 202 #define TZC_ATTR_REGION_EN 203 #define TZC_ATTR_REGION_ENABLE 0x1 204 #define TZC_ATTR_REGION_DISABLE 0x0 205 206 #define LOCKDOWN_RANGE_ENABLE BIT(31) 207 208 #define LOCKDOWN_SELECT_RANGE_ENABLE BIT(0) 209 210 void tzc_init(vaddr_t base); 211 void tzc_configure_region(uint8_t region, vaddr_t region_base, uint32_t attr); 212 void tzc_region_enable(uint8_t region); 213 void tzc_security_inversion_en(vaddr_t base); 214 void tzc_set_action(enum tzc_action action); 215 uint32_t tzc_get_action(void); 216 void tzc_fail_dump(void); 217 void tzc_int_clear(void); 218 int tzc_auto_configure(vaddr_t addr, vaddr_t rsize, uint32_t attr, 219 uint8_t region); 220 TEE_Result tzc_regions_lockdown(void); 221 222 #if TRACE_LEVEL >= TRACE_DEBUG 223 void tzc_dump_state(void); 224 #else 225 static inline void tzc_dump_state(void) 226 { 227 } 228 #endif 229 230 #endif /* __DRIVERS_TZC400_H */ 231