1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2025, STMicroelectronics 4 */ 5 6 #ifndef __DRIVERS_STM32MP21_RCC_H 7 #define __DRIVERS_STM32MP21_RCC_H 8 9 #include <util.h> 10 11 #define RCC_SECCFGR0 U(0x0) 12 #define RCC_SECCFGR1 U(0x4) 13 #define RCC_SECCFGR2 U(0x8) 14 #define RCC_SECCFGR3 U(0xC) 15 #define RCC_PRIVCFGR0 U(0x10) 16 #define RCC_PRIVCFGR1 U(0x14) 17 #define RCC_PRIVCFGR2 U(0x18) 18 #define RCC_PRIVCFGR3 U(0x1C) 19 #define RCC_RCFGLOCKR0 U(0x20) 20 #define RCC_RCFGLOCKR1 U(0x24) 21 #define RCC_RCFGLOCKR2 U(0x28) 22 #define RCC_RCFGLOCKR3 U(0x2C) 23 #define RCC_R0CIDCFGR U(0x30) 24 #define RCC_R0SEMCR U(0x34) 25 #define RCC_R1CIDCFGR U(0x38) 26 #define RCC_R1SEMCR U(0x3C) 27 #define RCC_R2CIDCFGR U(0x40) 28 #define RCC_R2SEMCR U(0x44) 29 #define RCC_R3CIDCFGR U(0x48) 30 #define RCC_R3SEMCR U(0x4C) 31 #define RCC_R4CIDCFGR U(0x50) 32 #define RCC_R4SEMCR U(0x54) 33 #define RCC_R5CIDCFGR U(0x58) 34 #define RCC_R5SEMCR U(0x5C) 35 #define RCC_R6CIDCFGR U(0x60) 36 #define RCC_R6SEMCR U(0x64) 37 #define RCC_R7CIDCFGR U(0x68) 38 #define RCC_R7SEMCR U(0x6C) 39 #define RCC_R8CIDCFGR U(0x70) 40 #define RCC_R8SEMCR U(0x74) 41 #define RCC_R9CIDCFGR U(0x78) 42 #define RCC_R9SEMCR U(0x7C) 43 #define RCC_R10CIDCFGR U(0x80) 44 #define RCC_R10SEMCR U(0x84) 45 #define RCC_R11CIDCFGR U(0x88) 46 #define RCC_R11SEMCR U(0x8C) 47 #define RCC_R12CIDCFGR U(0x90) 48 #define RCC_R12SEMCR U(0x94) 49 #define RCC_R13CIDCFGR U(0x98) 50 #define RCC_R13SEMCR U(0x9C) 51 #define RCC_R14CIDCFGR U(0xA0) 52 #define RCC_R14SEMCR U(0xA4) 53 #define RCC_R15CIDCFGR U(0xA8) 54 #define RCC_R15SEMCR U(0xAC) 55 #define RCC_R16CIDCFGR U(0xB0) 56 #define RCC_R16SEMCR U(0xB4) 57 #define RCC_R17CIDCFGR U(0xB8) 58 #define RCC_R17SEMCR U(0xBC) 59 #define RCC_R18CIDCFGR U(0xC0) 60 #define RCC_R18SEMCR U(0xC4) 61 #define RCC_R19CIDCFGR U(0xC8) 62 #define RCC_R19SEMCR U(0xCC) 63 #define RCC_R20CIDCFGR U(0xD0) 64 #define RCC_R20SEMCR U(0xD4) 65 #define RCC_R21CIDCFGR U(0xD8) 66 #define RCC_R21SEMCR U(0xDC) 67 #define RCC_R22CIDCFGR U(0xE0) 68 #define RCC_R22SEMCR U(0xE4) 69 #define RCC_R23CIDCFGR U(0xE8) 70 #define RCC_R23SEMCR U(0xEC) 71 #define RCC_R24CIDCFGR U(0xF0) 72 #define RCC_R24SEMCR U(0xF4) 73 #define RCC_R25CIDCFGR U(0xF8) 74 #define RCC_R25SEMCR U(0xFC) 75 #define RCC_R26CIDCFGR U(0x100) 76 #define RCC_R26SEMCR U(0x104) 77 #define RCC_R27CIDCFGR U(0x108) 78 #define RCC_R27SEMCR U(0x10C) 79 #define RCC_R28CIDCFGR U(0x110) 80 #define RCC_R28SEMCR U(0x114) 81 #define RCC_R29CIDCFGR U(0x118) 82 #define RCC_R29SEMCR U(0x11C) 83 #define RCC_R30CIDCFGR U(0x120) 84 #define RCC_R30SEMCR U(0x124) 85 #define RCC_R31CIDCFGR U(0x128) 86 #define RCC_R31SEMCR U(0x12C) 87 #define RCC_R32CIDCFGR U(0x130) 88 #define RCC_R32SEMCR U(0x134) 89 #define RCC_R33CIDCFGR U(0x138) 90 #define RCC_R33SEMCR U(0x13C) 91 #define RCC_R34CIDCFGR U(0x140) 92 #define RCC_R34SEMCR U(0x144) 93 #define RCC_R35CIDCFGR U(0x148) 94 #define RCC_R35SEMCR U(0x14C) 95 #define RCC_R36CIDCFGR U(0x150) 96 #define RCC_R36SEMCR U(0x154) 97 #define RCC_R37CIDCFGR U(0x158) 98 #define RCC_R37SEMCR U(0x15C) 99 #define RCC_R38CIDCFGR U(0x160) 100 #define RCC_R38SEMCR U(0x164) 101 #define RCC_R39CIDCFGR U(0x168) 102 #define RCC_R39SEMCR U(0x16C) 103 #define RCC_R40CIDCFGR U(0x170) 104 #define RCC_R40SEMCR U(0x174) 105 #define RCC_R41CIDCFGR U(0x178) 106 #define RCC_R41SEMCR U(0x17C) 107 #define RCC_R42CIDCFGR U(0x180) 108 #define RCC_R42SEMCR U(0x184) 109 #define RCC_R43CIDCFGR U(0x188) 110 #define RCC_R43SEMCR U(0x18C) 111 #define RCC_R44CIDCFGR U(0x190) 112 #define RCC_R44SEMCR U(0x194) 113 #define RCC_R45CIDCFGR U(0x198) 114 #define RCC_R45SEMCR U(0x19C) 115 #define RCC_R46CIDCFGR U(0x1A0) 116 #define RCC_R46SEMCR U(0x1A4) 117 #define RCC_R47CIDCFGR U(0x1A8) 118 #define RCC_R47SEMCR U(0x1AC) 119 #define RCC_R48CIDCFGR U(0x1B0) 120 #define RCC_R48SEMCR U(0x1B4) 121 #define RCC_R49CIDCFGR U(0x1B8) 122 #define RCC_R49SEMCR U(0x1BC) 123 #define RCC_R50CIDCFGR U(0x1C0) 124 #define RCC_R50SEMCR U(0x1C4) 125 #define RCC_R51CIDCFGR U(0x1C8) 126 #define RCC_R51SEMCR U(0x1CC) 127 #define RCC_R52CIDCFGR U(0x1D0) 128 #define RCC_R52SEMCR U(0x1D4) 129 #define RCC_R53CIDCFGR U(0x1D8) 130 #define RCC_R53SEMCR U(0x1DC) 131 #define RCC_R54CIDCFGR U(0x1E0) 132 #define RCC_R54SEMCR U(0x1E4) 133 #define RCC_R55CIDCFGR U(0x1E8) 134 #define RCC_R55SEMCR U(0x1EC) 135 #define RCC_R56CIDCFGR U(0x1F0) 136 #define RCC_R56SEMCR U(0x1F4) 137 #define RCC_R57CIDCFGR U(0x1F8) 138 #define RCC_R57SEMCR U(0x1FC) 139 #define RCC_R58CIDCFGR U(0x200) 140 #define RCC_R58SEMCR U(0x204) 141 #define RCC_R59CIDCFGR U(0x208) 142 #define RCC_R59SEMCR U(0x20C) 143 #define RCC_R60CIDCFGR U(0x210) 144 #define RCC_R60SEMCR U(0x214) 145 #define RCC_R61CIDCFGR U(0x218) 146 #define RCC_R61SEMCR U(0x21C) 147 #define RCC_R62CIDCFGR U(0x220) 148 #define RCC_R62SEMCR U(0x224) 149 #define RCC_R63CIDCFGR U(0x228) 150 #define RCC_R63SEMCR U(0x22C) 151 #define RCC_R64CIDCFGR U(0x230) 152 #define RCC_R64SEMCR U(0x234) 153 #define RCC_R65CIDCFGR U(0x238) 154 #define RCC_R65SEMCR U(0x23C) 155 #define RCC_R66CIDCFGR U(0x240) 156 #define RCC_R66SEMCR U(0x244) 157 #define RCC_R67CIDCFGR U(0x248) 158 #define RCC_R67SEMCR U(0x24C) 159 #define RCC_R68CIDCFGR U(0x250) 160 #define RCC_R68SEMCR U(0x254) 161 #define RCC_R69CIDCFGR U(0x258) 162 #define RCC_R69SEMCR U(0x25C) 163 #define RCC_R70CIDCFGR U(0x260) 164 #define RCC_R70SEMCR U(0x264) 165 #define RCC_R71CIDCFGR U(0x268) 166 #define RCC_R71SEMCR U(0x26C) 167 #define RCC_R73CIDCFGR U(0x278) 168 #define RCC_R73SEMCR U(0x27C) 169 #define RCC_R74CIDCFGR U(0x280) 170 #define RCC_R74SEMCR U(0x284) 171 #define RCC_R75CIDCFGR U(0x288) 172 #define RCC_R75SEMCR U(0x28C) 173 #define RCC_R76CIDCFGR U(0x290) 174 #define RCC_R76SEMCR U(0x294) 175 #define RCC_R77CIDCFGR U(0x298) 176 #define RCC_R77SEMCR U(0x29C) 177 #define RCC_R78CIDCFGR U(0x2A0) 178 #define RCC_R78SEMCR U(0x2A4) 179 #define RCC_R79CIDCFGR U(0x2A8) 180 #define RCC_R79SEMCR U(0x2AC) 181 #define RCC_R83CIDCFGR U(0x2C8) 182 #define RCC_R83SEMCR U(0x2CC) 183 #define RCC_R84CIDCFGR U(0x2D0) 184 #define RCC_R84SEMCR U(0x2D4) 185 #define RCC_R85CIDCFGR U(0x2D8) 186 #define RCC_R85SEMCR U(0x2DC) 187 #define RCC_R86CIDCFGR U(0x2E0) 188 #define RCC_R86SEMCR U(0x2E4) 189 #define RCC_R87CIDCFGR U(0x2E8) 190 #define RCC_R87SEMCR U(0x2EC) 191 #define RCC_R88CIDCFGR U(0x2F0) 192 #define RCC_R88SEMCR U(0x2F4) 193 #define RCC_R90CIDCFGR U(0x300) 194 #define RCC_R90SEMCR U(0x304) 195 #define RCC_R91CIDCFGR U(0x308) 196 #define RCC_R91SEMCR U(0x30C) 197 #define RCC_R92CIDCFGR U(0x310) 198 #define RCC_R92SEMCR U(0x314) 199 #define RCC_R93CIDCFGR U(0x318) 200 #define RCC_R93SEMCR U(0x31C) 201 #define RCC_R94CIDCFGR U(0x320) 202 #define RCC_R94SEMCR U(0x324) 203 #define RCC_R95CIDCFGR U(0x328) 204 #define RCC_R95SEMCR U(0x32C) 205 #define RCC_R96CIDCFGR U(0x330) 206 #define RCC_R96SEMCR U(0x334) 207 #define RCC_R97CIDCFGR U(0x338) 208 #define RCC_R97SEMCR U(0x33C) 209 #define RCC_R98CIDCFGR U(0x340) 210 #define RCC_R98SEMCR U(0x344) 211 #define RCC_R101CIDCFGR U(0x358) 212 #define RCC_R101SEMCR U(0x35C) 213 #define RCC_R102CIDCFGR U(0x360) 214 #define RCC_R102SEMCR U(0x364) 215 #define RCC_R103CIDCFGR U(0x368) 216 #define RCC_R103SEMCR U(0x36C) 217 #define RCC_R104CIDCFGR U(0x370) 218 #define RCC_R104SEMCR U(0x374) 219 #define RCC_R105CIDCFGR U(0x378) 220 #define RCC_R105SEMCR U(0x37C) 221 #define RCC_R106CIDCFGR U(0x380) 222 #define RCC_R106SEMCR U(0x384) 223 #define RCC_R108CIDCFGR U(0x390) 224 #define RCC_R108SEMCR U(0x394) 225 #define RCC_R109CIDCFGR U(0x398) 226 #define RCC_R109SEMCR U(0x39C) 227 #define RCC_R110CIDCFGR U(0x3A0) 228 #define RCC_R110SEMCR U(0x3A4) 229 #define RCC_R111CIDCFGR U(0x3A8) 230 #define RCC_R111SEMCR U(0x3AC) 231 #define RCC_R112CIDCFGR U(0x3B0) 232 #define RCC_R112SEMCR U(0x3B4) 233 #define RCC_R113CIDCFGR U(0x3B8) 234 #define RCC_R113SEMCR U(0x3BC) 235 #define RCC_GRSTCSETR U(0x400) 236 #define RCC_C1RSTCSETR U(0x404) 237 #define RCC_C2RSTCSETR U(0x40C) 238 #define RCC_HWRSTSCLRR U(0x410) 239 #define RCC_C1HWRSTSCLRR U(0x414) 240 #define RCC_C2HWRSTSCLRR U(0x418) 241 #define RCC_C1BOOTRSTSSETR U(0x41C) 242 #define RCC_C1BOOTRSTSCLRR U(0x420) 243 #define RCC_C2BOOTRSTSSETR U(0x424) 244 #define RCC_C2BOOTRSTSCLRR U(0x428) 245 #define RCC_C1SREQSETR U(0x42C) 246 #define RCC_C1SREQCLRR U(0x430) 247 #define RCC_CPUBOOTCR U(0x434) 248 #define RCC_STBYBOOTCR U(0x438) 249 #define RCC_LEGBOOTCR U(0x43C) 250 #define RCC_BDCR U(0x440) 251 #define RCC_RDCR U(0x44C) 252 #define RCC_C1MSRDCR U(0x450) 253 #define RCC_PWRLPDLYCR U(0x454) 254 #define RCC_C1CIESETR U(0x458) 255 #define RCC_C1CIFCLRR U(0x45C) 256 #define RCC_C2CIESETR U(0x460) 257 #define RCC_C2CIFCLRR U(0x464) 258 #define RCC_IWDGC1FZSETR U(0x468) 259 #define RCC_IWDGC1FZCLRR U(0x46C) 260 #define RCC_IWDGC1CFGSETR U(0x470) 261 #define RCC_IWDGC1CFGCLRR U(0x474) 262 #define RCC_IWDGC2FZSETR U(0x478) 263 #define RCC_IWDGC2FZCLRR U(0x47C) 264 #define RCC_IWDGC2CFGSETR U(0x480) 265 #define RCC_IWDGC2CFGCLRR U(0x484) 266 #define RCC_MCO1CFGR U(0x488) 267 #define RCC_MCO2CFGR U(0x48C) 268 #define RCC_OCENSETR U(0x490) 269 #define RCC_OCENCLRR U(0x494) 270 #define RCC_OCRDYR U(0x498) 271 #define RCC_HSICFGR U(0x49C) 272 #define RCC_MSICFGR U(0x4A0) 273 #define RCC_LSICR U(0x4A4) 274 #define RCC_RTCDIVR U(0x4A8) 275 #define RCC_APB1DIVR U(0x4AC) 276 #define RCC_APB2DIVR U(0x4B0) 277 #define RCC_APB3DIVR U(0x4B4) 278 #define RCC_APB4DIVR U(0x4B8) 279 #define RCC_APB5DIVR U(0x4BC) 280 #define RCC_APBDBGDIVR U(0x4C0) 281 #define RCC_TIMG1PRER U(0x4C8) 282 #define RCC_TIMG2PRER U(0x4CC) 283 #define RCC_LSMCUDIVR U(0x4D0) 284 #define RCC_DDRCPCFGR U(0x4D4) 285 #define RCC_DDRCAPBCFGR U(0x4D8) 286 #define RCC_DDRPHYCAPBCFGR U(0x4DC) 287 #define RCC_DDRPHYCCFGR U(0x4E0) 288 #define RCC_DDRCFGR U(0x4E4) 289 #define RCC_DDRITFCFGR U(0x4E8) 290 #define RCC_SYSRAMCFGR U(0x4F0) 291 #define RCC_SRAM1CFGR U(0x4F8) 292 #define RCC_RETRAMCFGR U(0x500) 293 #define RCC_BKPSRAMCFGR U(0x504) 294 #define RCC_OSPI1CFGR U(0x514) 295 #define RCC_FMCCFGR U(0x51C) 296 #define RCC_DBGCFGR U(0x520) 297 #define RCC_STMCFGR U(0x524) 298 #define RCC_ETRCFGR U(0x528) 299 #define RCC_GPIOACFGR U(0x52C) 300 #define RCC_GPIOBCFGR U(0x530) 301 #define RCC_GPIOCCFGR U(0x534) 302 #define RCC_GPIODCFGR U(0x538) 303 #define RCC_GPIOECFGR U(0x53C) 304 #define RCC_GPIOFCFGR U(0x540) 305 #define RCC_GPIOGCFGR U(0x544) 306 #define RCC_GPIOHCFGR U(0x548) 307 #define RCC_GPIOICFGR U(0x54C) 308 #define RCC_GPIOZCFGR U(0x558) 309 #define RCC_HPDMA1CFGR U(0x55C) 310 #define RCC_HPDMA2CFGR U(0x560) 311 #define RCC_HPDMA3CFGR U(0x564) 312 #define RCC_IPCC1CFGR U(0x570) 313 #define RCC_RTCCFGR U(0x578) 314 #define RCC_SYSCPU1CFGR U(0x580) 315 #define RCC_BSECCFGR U(0x584) 316 #define RCC_PLL2CFGR1 U(0x590) 317 #define RCC_PLL2CFGR2 U(0x594) 318 #define RCC_PLL2CFGR3 U(0x598) 319 #define RCC_PLL2CFGR4 U(0x59C) 320 #define RCC_PLL2CFGR5 U(0x5A0) 321 #define RCC_PLL2CFGR6 U(0x5A8) 322 #define RCC_PLL2CFGR7 U(0x5AC) 323 #define RCC_HSIFMONCR U(0x5E0) 324 #define RCC_HSIFVALR U(0x5E4) 325 #define RCC_MSIFMONCR U(0x5E8) 326 #define RCC_MSIFVALR U(0x5EC) 327 #define RCC_TIM1CFGR U(0x700) 328 #define RCC_TIM2CFGR U(0x704) 329 #define RCC_TIM3CFGR U(0x708) 330 #define RCC_TIM4CFGR U(0x70C) 331 #define RCC_TIM5CFGR U(0x710) 332 #define RCC_TIM6CFGR U(0x714) 333 #define RCC_TIM7CFGR U(0x718) 334 #define RCC_TIM8CFGR U(0x71C) 335 #define RCC_TIM10CFGR U(0x720) 336 #define RCC_TIM11CFGR U(0x724) 337 #define RCC_TIM12CFGR U(0x728) 338 #define RCC_TIM13CFGR U(0x72C) 339 #define RCC_TIM14CFGR U(0x730) 340 #define RCC_TIM15CFGR U(0x734) 341 #define RCC_TIM16CFGR U(0x738) 342 #define RCC_TIM17CFGR U(0x73C) 343 #define RCC_LPTIM1CFGR U(0x744) 344 #define RCC_LPTIM2CFGR U(0x748) 345 #define RCC_LPTIM3CFGR U(0x74C) 346 #define RCC_LPTIM4CFGR U(0x750) 347 #define RCC_LPTIM5CFGR U(0x754) 348 #define RCC_SPI1CFGR U(0x758) 349 #define RCC_SPI2CFGR U(0x75C) 350 #define RCC_SPI3CFGR U(0x760) 351 #define RCC_SPI4CFGR U(0x764) 352 #define RCC_SPI5CFGR U(0x768) 353 #define RCC_SPI6CFGR U(0x76C) 354 #define RCC_SPDIFRXCFGR U(0x778) 355 #define RCC_USART1CFGR U(0x77C) 356 #define RCC_USART2CFGR U(0x780) 357 #define RCC_USART3CFGR U(0x784) 358 #define RCC_UART4CFGR U(0x788) 359 #define RCC_UART5CFGR U(0x78C) 360 #define RCC_USART6CFGR U(0x790) 361 #define RCC_UART7CFGR U(0x794) 362 #define RCC_LPUART1CFGR U(0x7A0) 363 #define RCC_I2C1CFGR U(0x7A4) 364 #define RCC_I2C2CFGR U(0x7A8) 365 #define RCC_I2C3CFGR U(0x7AC) 366 #define RCC_SAI1CFGR U(0x7C4) 367 #define RCC_SAI2CFGR U(0x7C8) 368 #define RCC_SAI3CFGR U(0x7CC) 369 #define RCC_SAI4CFGR U(0x7D0) 370 #define RCC_MDF1CFGR U(0x7D8) 371 #define RCC_FDCANCFGR U(0x7E0) 372 #define RCC_HDPCFGR U(0x7E4) 373 #define RCC_ADC1CFGR U(0x7E8) 374 #define RCC_ADC2CFGR U(0x7EC) 375 #define RCC_ETH1CFGR U(0x7F0) 376 #define RCC_ETH2CFGR U(0x7F4) 377 #define RCC_USBHCFGR U(0x7FC) 378 #define RCC_USB2PHY1CFGR U(0x800) 379 #define RCC_OTGCFGR U(0x808) 380 #define RCC_USB2PHY2CFGR U(0x80C) 381 #define RCC_STGENCFGR U(0x824) 382 #define RCC_SDMMC1CFGR U(0x830) 383 #define RCC_SDMMC2CFGR U(0x834) 384 #define RCC_SDMMC3CFGR U(0x838) 385 #define RCC_LTDCCFGR U(0x840) 386 #define RCC_CSICFGR U(0x858) 387 #define RCC_DCMIPPCFGR U(0x85C) 388 #define RCC_DCMIPSSICFGR U(0x860) 389 #define RCC_RNG1CFGR U(0x870) 390 #define RCC_RNG2CFGR U(0x874) 391 #define RCC_PKACFGR U(0x878) 392 #define RCC_SAESCFGR U(0x87C) 393 #define RCC_HASH1CFGR U(0x880) 394 #define RCC_HASH2CFGR U(0x884) 395 #define RCC_CRYP1CFGR U(0x888) 396 #define RCC_CRYP2CFGR U(0x88C) 397 #define RCC_IWDG1CFGR U(0x894) 398 #define RCC_IWDG2CFGR U(0x898) 399 #define RCC_IWDG3CFGR U(0x89C) 400 #define RCC_IWDG4CFGR U(0x8A0) 401 #define RCC_WWDG1CFGR U(0x8A4) 402 #define RCC_VREFCFGR U(0x8AC) 403 #define RCC_DTSCFGR U(0x8B0) 404 #define RCC_CRCCFGR U(0x8B4) 405 #define RCC_SERCCFGR U(0x8B8) 406 #define RCC_DDRPERFMCFGR U(0x8C0) 407 #define RCC_I3C1CFGR U(0x8C8) 408 #define RCC_I3C2CFGR U(0x8CC) 409 #define RCC_I3C3CFGR U(0x8D0) 410 #define RCC_MUXSELCFGR U(0x1000) 411 #define RCC_XBAR0CFGR U(0x1018) 412 #define RCC_XBAR1CFGR U(0x101C) 413 #define RCC_XBAR2CFGR U(0x1020) 414 #define RCC_XBAR3CFGR U(0x1024) 415 #define RCC_XBAR4CFGR U(0x1028) 416 #define RCC_XBAR5CFGR U(0x102C) 417 #define RCC_XBAR6CFGR U(0x1030) 418 #define RCC_XBAR7CFGR U(0x1034) 419 #define RCC_XBAR8CFGR U(0x1038) 420 #define RCC_XBAR9CFGR U(0x103C) 421 #define RCC_XBAR10CFGR U(0x1040) 422 #define RCC_XBAR11CFGR U(0x1044) 423 #define RCC_XBAR12CFGR U(0x1048) 424 #define RCC_XBAR13CFGR U(0x104C) 425 #define RCC_XBAR14CFGR U(0x1050) 426 #define RCC_XBAR15CFGR U(0x1054) 427 #define RCC_XBAR16CFGR U(0x1058) 428 #define RCC_XBAR17CFGR U(0x105C) 429 #define RCC_XBAR18CFGR U(0x1060) 430 #define RCC_XBAR19CFGR U(0x1064) 431 #define RCC_XBAR20CFGR U(0x1068) 432 #define RCC_XBAR21CFGR U(0x106C) 433 #define RCC_XBAR22CFGR U(0x1070) 434 #define RCC_XBAR23CFGR U(0x1074) 435 #define RCC_XBAR24CFGR U(0x1078) 436 #define RCC_XBAR25CFGR U(0x107C) 437 #define RCC_XBAR26CFGR U(0x1080) 438 #define RCC_XBAR27CFGR U(0x1084) 439 #define RCC_XBAR28CFGR U(0x1088) 440 #define RCC_XBAR29CFGR U(0x108C) 441 #define RCC_XBAR30CFGR U(0x1090) 442 #define RCC_XBAR31CFGR U(0x1094) 443 #define RCC_XBAR32CFGR U(0x1098) 444 #define RCC_XBAR33CFGR U(0x109C) 445 #define RCC_XBAR34CFGR U(0x10A0) 446 #define RCC_XBAR35CFGR U(0x10A4) 447 #define RCC_XBAR36CFGR U(0x10A8) 448 #define RCC_XBAR37CFGR U(0x10AC) 449 #define RCC_XBAR38CFGR U(0x10B0) 450 #define RCC_XBAR39CFGR U(0x10B4) 451 #define RCC_XBAR40CFGR U(0x10B8) 452 #define RCC_XBAR41CFGR U(0x10BC) 453 #define RCC_XBAR42CFGR U(0x10C0) 454 #define RCC_XBAR43CFGR U(0x10C4) 455 #define RCC_XBAR44CFGR U(0x10C8) 456 #define RCC_XBAR45CFGR U(0x10CC) 457 #define RCC_XBAR46CFGR U(0x10D0) 458 #define RCC_XBAR47CFGR U(0x10D4) 459 #define RCC_XBAR48CFGR U(0x10D8) 460 #define RCC_XBAR49CFGR U(0x10DC) 461 #define RCC_XBAR50CFGR U(0x10E0) 462 #define RCC_XBAR51CFGR U(0x10E4) 463 #define RCC_XBAR52CFGR U(0x10E8) 464 #define RCC_XBAR53CFGR U(0x10EC) 465 #define RCC_XBAR54CFGR U(0x10F0) 466 #define RCC_XBAR55CFGR U(0x10F4) 467 #define RCC_XBAR56CFGR U(0x10F8) 468 #define RCC_XBAR57CFGR U(0x10FC) 469 #define RCC_XBAR58CFGR U(0x1100) 470 #define RCC_XBAR59CFGR U(0x1104) 471 #define RCC_XBAR60CFGR U(0x1108) 472 #define RCC_XBAR61CFGR U(0x110C) 473 #define RCC_XBAR62CFGR U(0x1110) 474 #define RCC_XBAR63CFGR U(0x1114) 475 #define RCC_PREDIV0CFGR U(0x1118) 476 #define RCC_PREDIV1CFGR U(0x111C) 477 #define RCC_PREDIV2CFGR U(0x1120) 478 #define RCC_PREDIV3CFGR U(0x1124) 479 #define RCC_PREDIV4CFGR U(0x1128) 480 #define RCC_PREDIV5CFGR U(0x112C) 481 #define RCC_PREDIV6CFGR U(0x1130) 482 #define RCC_PREDIV7CFGR U(0x1134) 483 #define RCC_PREDIV8CFGR U(0x1138) 484 #define RCC_PREDIV9CFGR U(0x113C) 485 #define RCC_PREDIV10CFGR U(0x1140) 486 #define RCC_PREDIV11CFGR U(0x1144) 487 #define RCC_PREDIV12CFGR U(0x1148) 488 #define RCC_PREDIV13CFGR U(0x114C) 489 #define RCC_PREDIV14CFGR U(0x1150) 490 #define RCC_PREDIV15CFGR U(0x1154) 491 #define RCC_PREDIV16CFGR U(0x1158) 492 #define RCC_PREDIV17CFGR U(0x115C) 493 #define RCC_PREDIV18CFGR U(0x1160) 494 #define RCC_PREDIV19CFGR U(0x1164) 495 #define RCC_PREDIV20CFGR U(0x1168) 496 #define RCC_PREDIV21CFGR U(0x116C) 497 #define RCC_PREDIV22CFGR U(0x1170) 498 #define RCC_PREDIV23CFGR U(0x1174) 499 #define RCC_PREDIV24CFGR U(0x1178) 500 #define RCC_PREDIV25CFGR U(0x117C) 501 #define RCC_PREDIV26CFGR U(0x1180) 502 #define RCC_PREDIV27CFGR U(0x1184) 503 #define RCC_PREDIV28CFGR U(0x1188) 504 #define RCC_PREDIV29CFGR U(0x118C) 505 #define RCC_PREDIV30CFGR U(0x1190) 506 #define RCC_PREDIV31CFGR U(0x1194) 507 #define RCC_PREDIV32CFGR U(0x1198) 508 #define RCC_PREDIV33CFGR U(0x119C) 509 #define RCC_PREDIV34CFGR U(0x11A0) 510 #define RCC_PREDIV35CFGR U(0x11A4) 511 #define RCC_PREDIV36CFGR U(0x11A8) 512 #define RCC_PREDIV37CFGR U(0x11AC) 513 #define RCC_PREDIV38CFGR U(0x11B0) 514 #define RCC_PREDIV39CFGR U(0x11B4) 515 #define RCC_PREDIV40CFGR U(0x11B8) 516 #define RCC_PREDIV41CFGR U(0x11BC) 517 #define RCC_PREDIV42CFGR U(0x11C0) 518 #define RCC_PREDIV43CFGR U(0x11C4) 519 #define RCC_PREDIV44CFGR U(0x11C8) 520 #define RCC_PREDIV45CFGR U(0x11CC) 521 #define RCC_PREDIV46CFGR U(0x11D0) 522 #define RCC_PREDIV47CFGR U(0x11D4) 523 #define RCC_PREDIV48CFGR U(0x11D8) 524 #define RCC_PREDIV49CFGR U(0x11DC) 525 #define RCC_PREDIV50CFGR U(0x11E0) 526 #define RCC_PREDIV51CFGR U(0x11E4) 527 #define RCC_PREDIV52CFGR U(0x11E8) 528 #define RCC_PREDIV53CFGR U(0x11EC) 529 #define RCC_PREDIV54CFGR U(0x11F0) 530 #define RCC_PREDIV55CFGR U(0x11F4) 531 #define RCC_PREDIV56CFGR U(0x11F8) 532 #define RCC_PREDIV57CFGR U(0x11FC) 533 #define RCC_PREDIV58CFGR U(0x1200) 534 #define RCC_PREDIV59CFGR U(0x1204) 535 #define RCC_PREDIV60CFGR U(0x1208) 536 #define RCC_PREDIV61CFGR U(0x120C) 537 #define RCC_PREDIV62CFGR U(0x1210) 538 #define RCC_PREDIV63CFGR U(0x1214) 539 #define RCC_PREDIVSR1 U(0x1218) 540 #define RCC_PREDIVSR2 U(0x121C) 541 #define RCC_FINDIV0CFGR U(0x1224) 542 #define RCC_FINDIV1CFGR U(0x1228) 543 #define RCC_FINDIV2CFGR U(0x122C) 544 #define RCC_FINDIV3CFGR U(0x1230) 545 #define RCC_FINDIV4CFGR U(0x1234) 546 #define RCC_FINDIV5CFGR U(0x1238) 547 #define RCC_FINDIV6CFGR U(0x123C) 548 #define RCC_FINDIV7CFGR U(0x1240) 549 #define RCC_FINDIV8CFGR U(0x1244) 550 #define RCC_FINDIV9CFGR U(0x1248) 551 #define RCC_FINDIV10CFGR U(0x124C) 552 #define RCC_FINDIV11CFGR U(0x1250) 553 #define RCC_FINDIV12CFGR U(0x1254) 554 #define RCC_FINDIV13CFGR U(0x1258) 555 #define RCC_FINDIV14CFGR U(0x125C) 556 #define RCC_FINDIV15CFGR U(0x1260) 557 #define RCC_FINDIV16CFGR U(0x1264) 558 #define RCC_FINDIV17CFGR U(0x1268) 559 #define RCC_FINDIV18CFGR U(0x126C) 560 #define RCC_FINDIV19CFGR U(0x1270) 561 #define RCC_FINDIV20CFGR U(0x1274) 562 #define RCC_FINDIV21CFGR U(0x1278) 563 #define RCC_FINDIV22CFGR U(0x127C) 564 #define RCC_FINDIV23CFGR U(0x1280) 565 #define RCC_FINDIV24CFGR U(0x1284) 566 #define RCC_FINDIV25CFGR U(0x1288) 567 #define RCC_FINDIV26CFGR U(0x128C) 568 #define RCC_FINDIV27CFGR U(0x1290) 569 #define RCC_FINDIV28CFGR U(0x1294) 570 #define RCC_FINDIV29CFGR U(0x1298) 571 #define RCC_FINDIV30CFGR U(0x129C) 572 #define RCC_FINDIV31CFGR U(0x12A0) 573 #define RCC_FINDIV32CFGR U(0x12A4) 574 #define RCC_FINDIV33CFGR U(0x12A8) 575 #define RCC_FINDIV34CFGR U(0x12AC) 576 #define RCC_FINDIV35CFGR U(0x12B0) 577 #define RCC_FINDIV36CFGR U(0x12B4) 578 #define RCC_FINDIV37CFGR U(0x12B8) 579 #define RCC_FINDIV38CFGR U(0x12BC) 580 #define RCC_FINDIV39CFGR U(0x12C0) 581 #define RCC_FINDIV40CFGR U(0x12C4) 582 #define RCC_FINDIV41CFGR U(0x12C8) 583 #define RCC_FINDIV42CFGR U(0x12CC) 584 #define RCC_FINDIV43CFGR U(0x12D0) 585 #define RCC_FINDIV44CFGR U(0x12D4) 586 #define RCC_FINDIV45CFGR U(0x12D8) 587 #define RCC_FINDIV46CFGR U(0x12DC) 588 #define RCC_FINDIV47CFGR U(0x12E0) 589 #define RCC_FINDIV48CFGR U(0x12E4) 590 #define RCC_FINDIV49CFGR U(0x12E8) 591 #define RCC_FINDIV50CFGR U(0x12EC) 592 #define RCC_FINDIV51CFGR U(0x12F0) 593 #define RCC_FINDIV52CFGR U(0x12F4) 594 #define RCC_FINDIV53CFGR U(0x12F8) 595 #define RCC_FINDIV54CFGR U(0x12FC) 596 #define RCC_FINDIV55CFGR U(0x1300) 597 #define RCC_FINDIV56CFGR U(0x1304) 598 #define RCC_FINDIV57CFGR U(0x1308) 599 #define RCC_FINDIV58CFGR U(0x130C) 600 #define RCC_FINDIV59CFGR U(0x1310) 601 #define RCC_FINDIV60CFGR U(0x1314) 602 #define RCC_FINDIV61CFGR U(0x1318) 603 #define RCC_FINDIV62CFGR U(0x131C) 604 #define RCC_FINDIV63CFGR U(0x1320) 605 #define RCC_FINDIVSR1 U(0x1324) 606 #define RCC_FINDIVSR2 U(0x1328) 607 #define RCC_FCALCOBS0CFGR U(0x1340) 608 #define RCC_FCALCOBS1CFGR U(0x1344) 609 #define RCC_FCALCREFCFGR U(0x1348) 610 #define RCC_FCALCCR1 U(0x134C) 611 #define RCC_FCALCCR2 U(0x1354) 612 #define RCC_FCALCSR U(0x1358) 613 #define RCC_PLL4CFGR1 U(0x1360) 614 #define RCC_PLL4CFGR2 U(0x1364) 615 #define RCC_PLL4CFGR3 U(0x1368) 616 #define RCC_PLL4CFGR4 U(0x136C) 617 #define RCC_PLL4CFGR5 U(0x1370) 618 #define RCC_PLL4CFGR6 U(0x1378) 619 #define RCC_PLL4CFGR7 U(0x137C) 620 #define RCC_PLL5CFGR1 U(0x1388) 621 #define RCC_PLL5CFGR2 U(0x138C) 622 #define RCC_PLL5CFGR3 U(0x1390) 623 #define RCC_PLL5CFGR4 U(0x1394) 624 #define RCC_PLL5CFGR5 U(0x1398) 625 #define RCC_PLL5CFGR6 U(0x13A0) 626 #define RCC_PLL5CFGR7 U(0x13A4) 627 #define RCC_PLL6CFGR1 U(0x13B0) 628 #define RCC_PLL6CFGR2 U(0x13B4) 629 #define RCC_PLL6CFGR3 U(0x13B8) 630 #define RCC_PLL6CFGR4 U(0x13BC) 631 #define RCC_PLL6CFGR5 U(0x13C0) 632 #define RCC_PLL6CFGR6 U(0x13C8) 633 #define RCC_PLL6CFGR7 U(0x13CC) 634 #define RCC_PLL7CFGR1 U(0x13D8) 635 #define RCC_PLL7CFGR2 U(0x13DC) 636 #define RCC_PLL7CFGR3 U(0x13E0) 637 #define RCC_PLL7CFGR4 U(0x13E4) 638 #define RCC_PLL7CFGR5 U(0x13E8) 639 #define RCC_PLL7CFGR6 U(0x13F0) 640 #define RCC_PLL7CFGR7 U(0x13F4) 641 #define RCC_PLL8CFGR1 U(0x1400) 642 #define RCC_PLL8CFGR2 U(0x1404) 643 #define RCC_PLL8CFGR3 U(0x1408) 644 #define RCC_PLL8CFGR4 U(0x140C) 645 #define RCC_PLL8CFGR5 U(0x1410) 646 #define RCC_PLL8CFGR6 U(0x1418) 647 #define RCC_PLL8CFGR7 U(0x141C) 648 #define RCC_VERR U(0xFFF4) 649 #define RCC_IDR U(0xFFF8) 650 #define RCC_SIDR U(0xFFFC) 651 652 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 653 #define RCC_MP_ENCLRR_OFFSET U(4) 654 655 /* RCC_GRSTCSETR register fields */ 656 #define RCC_GRSTCSETR_SYSRST BIT(0) 657 658 /* RCC_C1RSTCSETR register fields */ 659 #define RCC_C1RSTCSETR_C1RST BIT(0) 660 661 /* RCC_C2RSTCSETR register fields */ 662 #define RCC_C2RSTCSETR_C2RST BIT(0) 663 664 /* RCC_HWRSTSCLRR register fields */ 665 #define RCC_HWRSTSCLRR_PORRSTF BIT(0) 666 #define RCC_HWRSTSCLRR_BORRSTF BIT(1) 667 #define RCC_HWRSTSCLRR_PADRSTF BIT(2) 668 #define RCC_HWRSTSCLRR_HCSSRSTF BIT(3) 669 #define RCC_HWRSTSCLRR_VCORERSTF BIT(4) 670 #define RCC_HWRSTSCLRR_SYSC1RSTF BIT(5) 671 #define RCC_HWRSTSCLRR_SYSC2RSTF BIT(6) 672 #define RCC_HWRSTSCLRR_IWDG1SYSRSTF BIT(7) 673 #define RCC_HWRSTSCLRR_IWDG2SYSRSTF BIT(8) 674 #define RCC_HWRSTSCLRR_IWDG3SYSRSTF BIT(9) 675 #define RCC_HWRSTSCLRR_IWDG4SYSRSTF BIT(10) 676 #define RCC_HWRSTSCLRR_RETCRCERRRSTF BIT(12) 677 #define RCC_HWRSTSCLRR_RETECCFAILCRCRSTF BIT(13) 678 #define RCC_HWRSTSCLRR_RETECCFAILRESTRSTF BIT(14) 679 680 /* RCC_C1HWRSTSCLRR register fields */ 681 #define RCC_C1HWRSTSCLRR_VCPURSTF BIT(0) 682 #define RCC_C1HWRSTSCLRR_C1RSTF BIT(1) 683 684 /* RCC_C2HWRSTSCLRR register fields */ 685 #define RCC_C2HWRSTSCLRR_C2RSTF BIT(0) 686 687 /* RCC_C1BOOTRSTSSETR register fields */ 688 #define RCC_C1BOOTRSTSSETR_PORRSTF BIT(0) 689 #define RCC_C1BOOTRSTSSETR_BORRSTF BIT(1) 690 #define RCC_C1BOOTRSTSSETR_PADRSTF BIT(2) 691 #define RCC_C1BOOTRSTSSETR_HCSSRSTF BIT(3) 692 #define RCC_C1BOOTRSTSSETR_VCORERSTF BIT(4) 693 #define RCC_C1BOOTRSTSSETR_VCPURSTF BIT(5) 694 #define RCC_C1BOOTRSTSSETR_SYSC1RSTF BIT(6) 695 #define RCC_C1BOOTRSTSSETR_SYSC2RSTF BIT(7) 696 #define RCC_C1BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 697 #define RCC_C1BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 698 #define RCC_C1BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 699 #define RCC_C1BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 700 #define RCC_C1BOOTRSTSSETR_C1RSTF BIT(13) 701 #define RCC_C1BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 702 #define RCC_C1BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 703 #define RCC_C1BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 704 #define RCC_C1BOOTRSTSSETR_STBYC1RSTF BIT(20) 705 #define RCC_C1BOOTRSTSSETR_D1STBYRSTF BIT(22) 706 #define RCC_C1BOOTRSTSSETR_D2STBYRSTF BIT(23) 707 708 /* RCC_C1BOOTRSTSCLRR register fields */ 709 #define RCC_C1BOOTRSTSCLRR_PORRSTF BIT(0) 710 #define RCC_C1BOOTRSTSCLRR_BORRSTF BIT(1) 711 #define RCC_C1BOOTRSTSCLRR_PADRSTF BIT(2) 712 #define RCC_C1BOOTRSTSCLRR_HCSSRSTF BIT(3) 713 #define RCC_C1BOOTRSTSCLRR_VCORERSTF BIT(4) 714 #define RCC_C1BOOTRSTSCLRR_VCPURSTF BIT(5) 715 #define RCC_C1BOOTRSTSCLRR_SYSC1RSTF BIT(6) 716 #define RCC_C1BOOTRSTSCLRR_SYSC2RSTF BIT(7) 717 #define RCC_C1BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 718 #define RCC_C1BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 719 #define RCC_C1BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 720 #define RCC_C1BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 721 #define RCC_C1BOOTRSTSCLRR_C1RSTF BIT(13) 722 #define RCC_C1BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 723 #define RCC_C1BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 724 #define RCC_C1BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 725 #define RCC_C1BOOTRSTSCLRR_STBYC1RSTF BIT(20) 726 #define RCC_C1BOOTRSTSCLRR_D1STBYRSTF BIT(22) 727 #define RCC_C1BOOTRSTSCLRR_D2STBYRSTF BIT(23) 728 729 /* RCC_C2BOOTRSTSSETR register fields */ 730 #define RCC_C2BOOTRSTSSETR_PORRSTF BIT(0) 731 #define RCC_C2BOOTRSTSSETR_BORRSTF BIT(1) 732 #define RCC_C2BOOTRSTSSETR_PADRSTF BIT(2) 733 #define RCC_C2BOOTRSTSSETR_HCSSRSTF BIT(3) 734 #define RCC_C2BOOTRSTSSETR_VCORERSTF BIT(4) 735 #define RCC_C2BOOTRSTSSETR_SYSC1RSTF BIT(6) 736 #define RCC_C2BOOTRSTSSETR_SYSC2RSTF BIT(7) 737 #define RCC_C2BOOTRSTSSETR_IWDG1SYSRSTF BIT(8) 738 #define RCC_C2BOOTRSTSSETR_IWDG2SYSRSTF BIT(9) 739 #define RCC_C2BOOTRSTSSETR_IWDG3SYSRSTF BIT(10) 740 #define RCC_C2BOOTRSTSSETR_IWDG4SYSRSTF BIT(11) 741 #define RCC_C2BOOTRSTSSETR_C2RSTF BIT(14) 742 #define RCC_C2BOOTRSTSSETR_RETCRCERRRSTF BIT(17) 743 #define RCC_C2BOOTRSTSSETR_RETECCFAILCRCRSTF BIT(18) 744 #define RCC_C2BOOTRSTSSETR_RETECCFAILRESTRSTF BIT(19) 745 #define RCC_C2BOOTRSTSSETR_STBYC2RSTF BIT(21) 746 #define RCC_C2BOOTRSTSSETR_D2STBYRSTF BIT(23) 747 748 /* RCC_C2BOOTRSTSCLRR register fields */ 749 #define RCC_C2BOOTRSTSCLRR_PORRSTF BIT(0) 750 #define RCC_C2BOOTRSTSCLRR_BORRSTF BIT(1) 751 #define RCC_C2BOOTRSTSCLRR_PADRSTF BIT(2) 752 #define RCC_C2BOOTRSTSCLRR_HCSSRSTF BIT(3) 753 #define RCC_C2BOOTRSTSCLRR_VCORERSTF BIT(4) 754 #define RCC_C2BOOTRSTSCLRR_SYSC1RSTF BIT(6) 755 #define RCC_C2BOOTRSTSCLRR_SYSC2RSTF BIT(7) 756 #define RCC_C2BOOTRSTSCLRR_IWDG1SYSRSTF BIT(8) 757 #define RCC_C2BOOTRSTSCLRR_IWDG2SYSRSTF BIT(9) 758 #define RCC_C2BOOTRSTSCLRR_IWDG3SYSRSTF BIT(10) 759 #define RCC_C2BOOTRSTSCLRR_IWDG4SYSRSTF BIT(11) 760 #define RCC_C2BOOTRSTSCLRR_C2RSTF BIT(14) 761 #define RCC_C2BOOTRSTSCLRR_RETCRCERRRSTF BIT(17) 762 #define RCC_C2BOOTRSTSCLRR_RETECCFAILCRCRSTF BIT(18) 763 #define RCC_C2BOOTRSTSCLRR_RETECCFAILRESTRSTF BIT(19) 764 #define RCC_C2BOOTRSTSCLRR_STBYC2RSTF BIT(21) 765 #define RCC_C2BOOTRSTSCLRR_D2STBYRSTF BIT(23) 766 767 /* RCC_C1SREQSETR register fields */ 768 #define RCC_C1SREQSETR_STPREQ_P0 BIT(0) 769 #define RCC_C1SREQSETR_ESLPREQ BIT(16) 770 771 /* RCC_C1SREQCLRR register fields */ 772 #define RCC_C1SREQCLRR_STPREQ_P0 BIT(0) 773 #define RCC_C1SREQCLRR_ESLPREQ BIT(16) 774 775 /* RCC_CPUBOOTCR register fields */ 776 #define RCC_CPUBOOTCR_BOOT_CPU2 BIT(0) 777 #define RCC_CPUBOOTCR_BOOT_CPU1 BIT(1) 778 779 /* RCC_STBYBOOTCR register fields */ 780 #define RCC_STBYBOOTCR_CPU_BEN_SEL BIT(1) 781 #define RCC_STBYBOOTCR_COLD_CPU2 BIT(2) 782 #define RCC_STBYBOOTCR_CPU2_HW_BEN BIT(4) 783 #define RCC_STBYBOOTCR_CPU1_HW_BEN BIT(5) 784 #define RCC_STBYBOOTCR_RET_CRCERR_RSTEN BIT(8) 785 786 /* RCC_LEGBOOTCR register fields */ 787 #define RCC_LEGBOOTCR_LEGACY_BEN BIT(0) 788 789 /* RCC_BDCR register fields */ 790 #define RCC_BDCR_LSEON BIT(0) 791 #define RCC_BDCR_LSEBYP BIT(1) 792 #define RCC_BDCR_LSERDY BIT(2) 793 #define RCC_BDCR_LSEDIGBYP BIT(3) 794 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) 795 #define RCC_BDCR_LSEDRV_SHIFT 4 796 #define RCC_BDCR_LSEDRV_WIDTH 2 797 #define RCC_BDCR_LSECSSON BIT(6) 798 #define RCC_BDCR_LSEGFON BIT(7) 799 #define RCC_BDCR_LSECSSD BIT(8) 800 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) 801 #define RCC_BDCR_RTCSRC_SHIFT 16 802 #define RCC_BDCR_RTCCKEN BIT(20) 803 #define RCC_BDCR_VSWRST BIT(31) 804 #define RCC_BDCR_LSEBYP_BIT 1 805 #define RCC_BDCR_LSEDIGBYP_BIT 3 806 #define RCC_BDCR_LSECSSON_BIT 6 807 808 /* RCC_RDCR register fields */ 809 #define RCC_RDCR_MRD_MASK GENMASK_32(20, 16) 810 #define RCC_RDCR_EADLY_MASK GENMASK_32(27, 24) 811 812 /* RCC_C1MSRDCR register fields */ 813 #define RCC_C1MSRDCR_C1MSRD_MASK GENMASK_32(4, 0) 814 #define RCC_C1MSRDCR_C1MSRST BIT(8) 815 816 /* RCC_PWRLPDLYCR register fields */ 817 #define RCC_PWRLPDLYCR_PWRLP_DLY_MASK GENMASK_32(21, 0) 818 #define RCC_PWRLPDLYCR_CPU2TMPSKP BIT(24) 819 820 /* RCC_C1CIESETR register fields */ 821 #define RCC_C1CIESETR_LSIRDYIE BIT(0) 822 #define RCC_C1CIESETR_LSERDYIE BIT(1) 823 #define RCC_C1CIESETR_HSIRDYIE BIT(2) 824 #define RCC_C1CIESETR_HSERDYIE BIT(3) 825 #define RCC_C1CIESETR_MSIRDYIE BIT(4) 826 #define RCC_C1CIESETR_PLL1RDYIE BIT(5) 827 #define RCC_C1CIESETR_PLL2RDYIE BIT(6) 828 #define RCC_C1CIESETR_PLL4RDYIE BIT(8) 829 #define RCC_C1CIESETR_PLL5RDYIE BIT(9) 830 #define RCC_C1CIESETR_PLL6RDYIE BIT(10) 831 #define RCC_C1CIESETR_PLL7RDYIE BIT(11) 832 #define RCC_C1CIESETR_PLL8RDYIE BIT(12) 833 #define RCC_C1CIESETR_LSECSSIE BIT(16) 834 #define RCC_C1CIESETR_WKUPIE BIT(20) 835 836 /* RCC_C1CIFCLRR register fields */ 837 #define RCC_C1CIFCLRR_LSIRDYF BIT(0) 838 #define RCC_C1CIFCLRR_LSERDYF BIT(1) 839 #define RCC_C1CIFCLRR_HSIRDYF BIT(2) 840 #define RCC_C1CIFCLRR_HSERDYF BIT(3) 841 #define RCC_C1CIFCLRR_MSIRDYF BIT(4) 842 #define RCC_C1CIFCLRR_PLL1RDYF BIT(5) 843 #define RCC_C1CIFCLRR_PLL2RDYF BIT(6) 844 #define RCC_C1CIFCLRR_PLL4RDYF BIT(8) 845 #define RCC_C1CIFCLRR_PLL5RDYF BIT(9) 846 #define RCC_C1CIFCLRR_PLL6RDYF BIT(10) 847 #define RCC_C1CIFCLRR_PLL7RDYF BIT(11) 848 #define RCC_C1CIFCLRR_PLL8RDYF BIT(12) 849 #define RCC_C1CIFCLRR_LSECSSF BIT(16) 850 #define RCC_C1CIFCLRR_WKUPF BIT(20) 851 852 /* RCC_C2CIESETR register fields */ 853 #define RCC_C2CIESETR_LSIRDYIE BIT(0) 854 #define RCC_C2CIESETR_LSERDYIE BIT(1) 855 #define RCC_C2CIESETR_HSIRDYIE BIT(2) 856 #define RCC_C2CIESETR_HSERDYIE BIT(3) 857 #define RCC_C2CIESETR_MSIRDYIE BIT(4) 858 #define RCC_C2CIESETR_PLL1RDYIE BIT(5) 859 #define RCC_C2CIESETR_PLL2RDYIE BIT(6) 860 #define RCC_C2CIESETR_PLL4RDYIE BIT(8) 861 #define RCC_C2CIESETR_PLL5RDYIE BIT(9) 862 #define RCC_C2CIESETR_PLL6RDYIE BIT(10) 863 #define RCC_C2CIESETR_PLL7RDYIE BIT(11) 864 #define RCC_C2CIESETR_PLL8RDYIE BIT(12) 865 #define RCC_C2CIESETR_LSECSSIE BIT(16) 866 #define RCC_C2CIESETR_WKUPIE BIT(20) 867 868 /* RCC_C2CIFCLRR register fields */ 869 #define RCC_C2CIFCLRR_LSIRDYF BIT(0) 870 #define RCC_C2CIFCLRR_LSERDYF BIT(1) 871 #define RCC_C2CIFCLRR_HSIRDYF BIT(2) 872 #define RCC_C2CIFCLRR_HSERDYF BIT(3) 873 #define RCC_C2CIFCLRR_MSIRDYF BIT(4) 874 #define RCC_C2CIFCLRR_PLL1RDYF BIT(5) 875 #define RCC_C2CIFCLRR_PLL2RDYF BIT(6) 876 #define RCC_C2CIFCLRR_PLL4RDYF BIT(8) 877 #define RCC_C2CIFCLRR_PLL5RDYF BIT(9) 878 #define RCC_C2CIFCLRR_PLL6RDYF BIT(10) 879 #define RCC_C2CIFCLRR_PLL7RDYF BIT(11) 880 #define RCC_C2CIFCLRR_PLL8RDYF BIT(12) 881 #define RCC_C2CIFCLRR_LSECSSF BIT(16) 882 #define RCC_C2CIFCLRR_WKUPF BIT(20) 883 884 /* RCC_IWDGC1FZSETR register fields */ 885 #define RCC_IWDGC1FZSETR_FZ_IWDG1 BIT(0) 886 #define RCC_IWDGC1FZSETR_FZ_IWDG2 BIT(1) 887 888 /* RCC_IWDGC1FZCLRR register fields */ 889 #define RCC_IWDGC1FZCLRR_FZ_IWDG1 BIT(0) 890 #define RCC_IWDGC1FZCLRR_FZ_IWDG2 BIT(1) 891 892 /* RCC_IWDGC1CFGSETR register fields */ 893 #define RCC_IWDGC1CFGSETR_IWDG1_SYSRSTEN BIT(0) 894 #define RCC_IWDGC1CFGSETR_IWDG2_SYSRSTEN BIT(2) 895 #define RCC_IWDGC1CFGSETR_IWDG2_KERRST BIT(18) 896 897 /* RCC_IWDGC1CFGCLRR register fields */ 898 #define RCC_IWDGC1CFGCLRR_IWDG1_SYSRSTEN BIT(0) 899 #define RCC_IWDGC1CFGCLRR_IWDG2_SYSRSTEN BIT(2) 900 #define RCC_IWDGC1CFGCLRR_IWDG2_KERRST BIT(18) 901 902 /* RCC_IWDGC2FZSETR register fields */ 903 #define RCC_IWDGC2FZSETR_FZ_IWDG3 BIT(0) 904 #define RCC_IWDGC2FZSETR_FZ_IWDG4 BIT(1) 905 906 /* RCC_IWDGC2FZCLRR register fields */ 907 #define RCC_IWDGC2FZCLRR_FZ_IWDG3 BIT(0) 908 #define RCC_IWDGC2FZCLRR_FZ_IWDG4 BIT(1) 909 910 /* RCC_IWDGC2CFGSETR register fields */ 911 #define RCC_IWDGC2CFGSETR_IWDG3_SYSRSTEN BIT(0) 912 #define RCC_IWDGC2CFGSETR_IWDG4_SYSRSTEN BIT(2) 913 #define RCC_IWDGC2CFGSETR_IWDG4_KERRST BIT(18) 914 915 /* RCC_IWDGC2CFGCLRR register fields */ 916 #define RCC_IWDGC2CFGCLRR_IWDG3_SYSRSTEN BIT(0) 917 #define RCC_IWDGC2CFGCLRR_IWDG4_SYSRSTEN BIT(2) 918 #define RCC_IWDGC2CFGCLRR_IWDG4_KERRST BIT(18) 919 920 /* RCC_MCO1CFGR register fields */ 921 #define RCC_MCO1CFGR_MCO1SEL BIT(0) 922 #define RCC_MCO1CFGR_MCO1ON BIT(8) 923 924 /* RCC_MCO2CFGR register fields */ 925 #define RCC_MCO2CFGR_MCO2SEL BIT(0) 926 #define RCC_MCO2CFGR_MCO2ON BIT(8) 927 928 /* RCC_OCENSETR register fields */ 929 #define RCC_OCENSETR_HSION BIT(0) 930 #define RCC_OCENSETR_HSIKERON BIT(1) 931 #define RCC_OCENSETR_MSION BIT(2) 932 #define RCC_OCENSETR_MSIKERON BIT(3) 933 #define RCC_OCENSETR_HSEDIV2ON BIT(5) 934 #define RCC_OCENSETR_HSEDIV2BYP BIT(6) 935 #define RCC_OCENSETR_HSEDIGBYP BIT(7) 936 #define RCC_OCENSETR_HSEON BIT(8) 937 #define RCC_OCENSETR_HSEKERON BIT(9) 938 #define RCC_OCENSETR_HSEBYP BIT(10) 939 #define RCC_OCENSETR_HSECSSON BIT(11) 940 941 #define RCC_OCENSETR_HSEDIGBYP_BIT 7 942 #define RCC_OCENSETR_HSEBYP_BIT 10 943 #define RCC_OCENSETR_HSECSSON_BIT 11 944 945 /* RCC_OCENCLRR register fields */ 946 #define RCC_OCENCLRR_HSION BIT(0) 947 #define RCC_OCENCLRR_HSIKERON BIT(1) 948 #define RCC_OCENCLRR_MSION BIT(2) 949 #define RCC_OCENCLRR_MSIKERON BIT(3) 950 #define RCC_OCENCLRR_HSEDIV2ON BIT(5) 951 #define RCC_OCENCLRR_HSEDIV2BYP BIT(6) 952 #define RCC_OCENCLRR_HSEDIGBYP BIT(7) 953 #define RCC_OCENCLRR_HSEON BIT(8) 954 #define RCC_OCENCLRR_HSEKERON BIT(9) 955 #define RCC_OCENCLRR_HSEBYP BIT(10) 956 957 /* RCC_OCRDYR register fields */ 958 #define RCC_OCRDYR_HSIRDY BIT(0) 959 #define RCC_OCRDYR_MSIRDY BIT(2) 960 #define RCC_OCRDYR_HSERDY BIT(8) 961 #define RCC_OCRDYR_CKREST BIT(25) 962 963 /* RCC_HSICFGR register fields */ 964 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) 965 #define RCC_HSICFGR_HSITRIM_SHIFT 8 966 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(24, 16) 967 #define RCC_HSICFGR_HSICAL_SHIFT 16 968 969 /* RCC_MSICFGR register fields */ 970 #define RCC_MSICFGR_MSITRIM_MASK GENMASK_32(12, 8) 971 #define RCC_MSICFGR_MSITRIM_SHIFT 8 972 #define RCC_MSICFGR_MSICAL_MASK GENMASK_32(23, 16) 973 #define RCC_MSICFGR_MSICAL_SHIFT 16 974 975 /* RCC_LSICR register fields */ 976 #define RCC_LSICR_LSION BIT(0) 977 #define RCC_LSICR_LSIRDY BIT(1) 978 979 /* RCC_RTCDIVR register fields */ 980 #define RCC_RTCDIVR_RTCDIV_MASK GENMASK_32(5, 0) 981 982 /* RCC_APB1DIVR register fields */ 983 #define RCC_APB1DIVR_APB1DIV_MASK GENMASK_32(2, 0) 984 #define RCC_APB1DIVR_APB1DIVRDY BIT(31) 985 986 /* RCC_APB2DIVR register fields */ 987 #define RCC_APB2DIVR_APB2DIV_MASK GENMASK_32(2, 0) 988 #define RCC_APB2DIVR_APB2DIVRDY BIT(31) 989 990 /* RCC_APB3DIVR register fields */ 991 #define RCC_APB3DIVR_APB3DIV_MASK GENMASK_32(2, 0) 992 #define RCC_APB3DIVR_APB3DIVRDY BIT(31) 993 994 /* RCC_APB4DIVR register fields */ 995 #define RCC_APB4DIVR_APB4DIV_MASK GENMASK_32(2, 0) 996 #define RCC_APB4DIVR_APB4DIVRDY BIT(31) 997 998 /* RCC_APB5DIVR register fields */ 999 #define RCC_APB5DIVR_APB5DIV_MASK GENMASK_32(2, 0) 1000 #define RCC_APB5DIVR_APB5DIVRDY BIT(31) 1001 1002 /* RCC_APBDBGDIVR register fields */ 1003 #define RCC_APBDBGDIVR_APBDBGDIV_MASK GENMASK_32(2, 0) 1004 #define RCC_APBDBGDIVR_APBDBGDIVRDY BIT(31) 1005 1006 /* RCC_TIMG1PRER register fields */ 1007 #define RCC_TIMG1PRER_TIMG1PRE BIT(0) 1008 #define RCC_TIMG1PRER_TIMG1PRERDY BIT(31) 1009 1010 /* RCC_TIMG2PRER register fields */ 1011 #define RCC_TIMG2PRER_TIMG2PRE BIT(0) 1012 #define RCC_TIMG2PRER_TIMG2PRERDY BIT(31) 1013 1014 /* RCC_LSMCUDIVR register fields */ 1015 #define RCC_LSMCUDIVR_LSMCUDIV BIT(0) 1016 #define RCC_LSMCUDIVR_LSMCUDIVRDY BIT(31) 1017 1018 /* RCC_DDRCPCFGR register fields */ 1019 #define RCC_DDRCPCFGR_DDRCPRST BIT(0) 1020 #define RCC_DDRCPCFGR_DDRCPEN BIT(1) 1021 #define RCC_DDRCPCFGR_DDRCPLPEN BIT(2) 1022 1023 /* RCC_DDRCAPBCFGR register fields */ 1024 #define RCC_DDRCAPBCFGR_DDRCAPBRST BIT(0) 1025 #define RCC_DDRCAPBCFGR_DDRCAPBEN BIT(1) 1026 #define RCC_DDRCAPBCFGR_DDRCAPBLPEN BIT(2) 1027 1028 /* RCC_DDRPHYCAPBCFGR register fields */ 1029 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBRST BIT(0) 1030 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBEN BIT(1) 1031 #define RCC_DDRPHYCAPBCFGR_DDRPHYCAPBLPEN BIT(2) 1032 1033 /* RCC_DDRPHYCCFGR register fields */ 1034 #define RCC_DDRPHYCCFGR_DDRPHYCEN BIT(1) 1035 1036 /* RCC_DDRCFGR register fields */ 1037 #define RCC_DDRCFGR_DDRCFGRST BIT(0) 1038 #define RCC_DDRCFGR_DDRCFGEN BIT(1) 1039 #define RCC_DDRCFGR_DDRCFGLPEN BIT(2) 1040 1041 /* RCC_DDRITFCFGR register fields */ 1042 #define RCC_DDRITFCFGR_DDRRST BIT(0) 1043 #define RCC_DDRITFCFGR_DDRCKMOD_MASK GENMASK_32(5, 4) 1044 #define RCC_DDRITFCFGR_DDRSHR BIT(8) 1045 #define RCC_DDRITFCFGR_DDRPHYDLP BIT(16) 1046 1047 /* RCC_SYSRAMCFGR register fields */ 1048 #define RCC_SYSRAMCFGR_SYSRAMEN BIT(1) 1049 #define RCC_SYSRAMCFGR_SYSRAMLPEN BIT(2) 1050 1051 /* RCC_SRAM1CFGR register fields */ 1052 #define RCC_SRAM1CFGR_SRAM1EN BIT(1) 1053 #define RCC_SRAM1CFGR_SRAM1LPEN BIT(2) 1054 1055 /* RCC_RETRAMCFGR register fields */ 1056 #define RCC_RETRAMCFGR_RETRAMEN BIT(1) 1057 #define RCC_RETRAMCFGR_RETRAMLPEN BIT(2) 1058 1059 /* RCC_BKPSRAMCFGR register fields */ 1060 #define RCC_BKPSRAMCFGR_BKPSRAMEN BIT(1) 1061 #define RCC_BKPSRAMCFGR_BKPSRAMLPEN BIT(2) 1062 1063 /* RCC_OSPI1CFGR register fields */ 1064 #define RCC_OSPI1CFGR_OSPI1RST BIT(0) 1065 #define RCC_OSPI1CFGR_OSPI1EN BIT(1) 1066 #define RCC_OSPI1CFGR_OSPI1LPEN BIT(2) 1067 #define RCC_OSPI1CFGR_OTFDEC1RST BIT(8) 1068 #define RCC_OSPI1CFGR_OSPI1DLLRST BIT(16) 1069 1070 /* RCC_FMCCFGR register fields */ 1071 #define RCC_FMCCFGR_FMCRST BIT(0) 1072 #define RCC_FMCCFGR_FMCEN BIT(1) 1073 #define RCC_FMCCFGR_FMCLPEN BIT(2) 1074 1075 /* RCC_DBGCFGR register fields */ 1076 #define RCC_DBGCFGR_DBGEN BIT(8) 1077 #define RCC_DBGCFGR_TRACEEN BIT(9) 1078 #define RCC_DBGCFGR_DBGMCUEN BIT(10) 1079 #define RCC_DBGCFGR_DBGRST BIT(12) 1080 1081 /* RCC_STMCFGR register fields */ 1082 #define RCC_STMCFGR_STMEN BIT(1) 1083 #define RCC_STMCFGR_STMLPEN BIT(2) 1084 1085 /* RCC_ETRCFGR register fields */ 1086 #define RCC_ETRCFGR_ETREN BIT(1) 1087 #define RCC_ETRCFGR_ETRLPEN BIT(2) 1088 1089 /* RCC_GPIOACFGR register fields */ 1090 #define RCC_GPIOACFGR_GPIOARST BIT(0) 1091 #define RCC_GPIOACFGR_GPIOAEN BIT(1) 1092 #define RCC_GPIOACFGR_GPIOALPEN BIT(2) 1093 1094 /* RCC_GPIOBCFGR register fields */ 1095 #define RCC_GPIOBCFGR_GPIOBRST BIT(0) 1096 #define RCC_GPIOBCFGR_GPIOBEN BIT(1) 1097 #define RCC_GPIOBCFGR_GPIOBLPEN BIT(2) 1098 1099 /* RCC_GPIOCCFGR register fields */ 1100 #define RCC_GPIOCCFGR_GPIOCRST BIT(0) 1101 #define RCC_GPIOCCFGR_GPIOCEN BIT(1) 1102 #define RCC_GPIOCCFGR_GPIOCLPEN BIT(2) 1103 1104 /* RCC_GPIODCFGR register fields */ 1105 #define RCC_GPIODCFGR_GPIODRST BIT(0) 1106 #define RCC_GPIODCFGR_GPIODEN BIT(1) 1107 #define RCC_GPIODCFGR_GPIODLPEN BIT(2) 1108 1109 /* RCC_GPIOECFGR register fields */ 1110 #define RCC_GPIOECFGR_GPIOERST BIT(0) 1111 #define RCC_GPIOECFGR_GPIOEEN BIT(1) 1112 #define RCC_GPIOECFGR_GPIOELPEN BIT(2) 1113 1114 /* RCC_GPIOFCFGR register fields */ 1115 #define RCC_GPIOFCFGR_GPIOFRST BIT(0) 1116 #define RCC_GPIOFCFGR_GPIOFEN BIT(1) 1117 #define RCC_GPIOFCFGR_GPIOFLPEN BIT(2) 1118 1119 /* RCC_GPIOGCFGR register fields */ 1120 #define RCC_GPIOGCFGR_GPIOGRST BIT(0) 1121 #define RCC_GPIOGCFGR_GPIOGEN BIT(1) 1122 #define RCC_GPIOGCFGR_GPIOGLPEN BIT(2) 1123 1124 /* RCC_GPIOHCFGR register fields */ 1125 #define RCC_GPIOHCFGR_GPIOHRST BIT(0) 1126 #define RCC_GPIOHCFGR_GPIOHEN BIT(1) 1127 #define RCC_GPIOHCFGR_GPIOHLPEN BIT(2) 1128 1129 /* RCC_GPIOICFGR register fields */ 1130 #define RCC_GPIOICFGR_GPIOIRST BIT(0) 1131 #define RCC_GPIOICFGR_GPIOIEN BIT(1) 1132 #define RCC_GPIOICFGR_GPIOILPEN BIT(2) 1133 1134 /* RCC_GPIOZCFGR register fields */ 1135 #define RCC_GPIOZCFGR_GPIOZRST BIT(0) 1136 #define RCC_GPIOZCFGR_GPIOZEN BIT(1) 1137 #define RCC_GPIOZCFGR_GPIOZLPEN BIT(2) 1138 1139 /* RCC_HPDMA1CFGR register fields */ 1140 #define RCC_HPDMA1CFGR_HPDMA1RST BIT(0) 1141 #define RCC_HPDMA1CFGR_HPDMA1EN BIT(1) 1142 #define RCC_HPDMA1CFGR_HPDMA1LPEN BIT(2) 1143 1144 /* RCC_HPDMA2CFGR register fields */ 1145 #define RCC_HPDMA2CFGR_HPDMA2RST BIT(0) 1146 #define RCC_HPDMA2CFGR_HPDMA2EN BIT(1) 1147 #define RCC_HPDMA2CFGR_HPDMA2LPEN BIT(2) 1148 1149 /* RCC_HPDMA3CFGR register fields */ 1150 #define RCC_HPDMA3CFGR_HPDMA3RST BIT(0) 1151 #define RCC_HPDMA3CFGR_HPDMA3EN BIT(1) 1152 #define RCC_HPDMA3CFGR_HPDMA3LPEN BIT(2) 1153 1154 /* RCC_IPCC1CFGR register fields */ 1155 #define RCC_IPCC1CFGR_IPCC1RST BIT(0) 1156 #define RCC_IPCC1CFGR_IPCC1EN BIT(1) 1157 #define RCC_IPCC1CFGR_IPCC1LPEN BIT(2) 1158 1159 /* RCC_RTCCFGR register fields */ 1160 #define RCC_RTCCFGR_RTCEN BIT(1) 1161 #define RCC_RTCCFGR_RTCLPEN BIT(2) 1162 1163 /* RCC_SYSCPU1CFGR register fields */ 1164 #define RCC_SYSCPU1CFGR_SYSCPU1EN BIT(1) 1165 #define RCC_SYSCPU1CFGR_SYSCPU1LPEN BIT(2) 1166 1167 /* RCC_BSECCFGR register fields */ 1168 #define RCC_BSECCFGR_BSECEN BIT(1) 1169 #define RCC_BSECCFGR_BSECLPEN BIT(2) 1170 1171 /* RCC_PLLxCFGR1 register fields */ 1172 #define RCC_PLLxCFGR1_SSMODRST BIT(0) 1173 #define RCC_PLLxCFGR1_PLLEN BIT(8) 1174 #define RCC_PLLxCFGR1_PLLRDY BIT(24) 1175 #define RCC_PLLxCFGR1_CKREFST BIT(28) 1176 1177 /* RCC_PLLxCFGR2 register fields */ 1178 #define RCC_PLLxCFGR2_FREFDIV_MASK GENMASK_32(5, 0) 1179 #define RCC_PLLxCFGR2_FBDIV_MASK GENMASK_32(27, 16) 1180 #define RCC_PLLxCFGR2_FREFDIV_SHIFT 0 1181 #define RCC_PLLxCFGR2_FBDIV_SHIFT 16 1182 1183 /* RCC_PLLxCFGR3 register fields */ 1184 #define RCC_PLLxCFGR3_FRACIN_MASK GENMASK_32(23, 0) 1185 #define RCC_PLLxCFGR3_DOWNSPREAD BIT(24) 1186 #define RCC_PLLxCFGR3_DACEN BIT(25) 1187 #define RCC_PLLxCFGR3_SSCGDIS BIT(26) 1188 #define RCC_PLLxCFGR3_FRACIN_SHIFT 0 1189 1190 /* RCC_PLLxCFGR4 register fields */ 1191 #define RCC_PLLxCFGR4_DSMEN BIT(8) 1192 #define RCC_PLLxCFGR4_FOUTPOSTDIVEN BIT(9) 1193 #define RCC_PLLxCFGR4_BYPASS BIT(10) 1194 1195 /* RCC_PLLxCFGR5 register fields */ 1196 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) 1197 #define RCC_PLLxCFGR5_SPREAD_MASK GENMASK_32(20, 16) 1198 #define RCC_PLLxCFGR5_DIVVAL_SHIFT 0 1199 #define RCC_PLLxCFGR5_SPREAD_SHIFT 16 1200 1201 /* RCC_PLLxCFGR6 register fields */ 1202 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) 1203 #define RCC_PLLxCFGR6_POSTDIV1_SHIFT 0 1204 1205 /* RCC_PLLxCFGR7 register fields */ 1206 #define RCC_PLLxCFGR7_POSTDIV2_MASK GENMASK_32(2, 0) 1207 #define RCC_PLLxCFGR7_POSTDIV2_SHIFT 0 1208 1209 /* RCC_HSIFMONCR register fields */ 1210 #define RCC_HSIFMONCR_HSIREF_MASK GENMASK_32(10, 0) 1211 #define RCC_HSIFMONCR_HSIMONEN BIT(15) 1212 #define RCC_HSIFMONCR_HSIDEV_MASK GENMASK_32(21, 16) 1213 #define RCC_HSIFMONCR_HSIMONIE BIT(30) 1214 #define RCC_HSIFMONCR_HSIMONF BIT(31) 1215 1216 /* RCC_HSIFVALR register fields */ 1217 #define RCC_HSIFVALR_HSIVAL_MASK GENMASK_32(10, 0) 1218 1219 /* RCC_MSIFMONCR register fields */ 1220 #define RCC_MSIFMONCR_MSIREF_MASK GENMASK_32(8, 0) 1221 #define RCC_MSIFMONCR_MSIMONEN BIT(15) 1222 #define RCC_MSIFMONCR_MSIDEV_MASK GENMASK_32(20, 16) 1223 #define RCC_MSIFMONCR_MSIMONIE BIT(30) 1224 #define RCC_MSIFMONCR_MSIMONF BIT(31) 1225 1226 /* RCC_MSIFVALR register fields */ 1227 #define RCC_MSIFVALR_MSIVAL_MASK GENMASK_32(8, 0) 1228 1229 /* RCC_TIM1CFGR register fields */ 1230 #define RCC_TIM1CFGR_TIM1RST BIT(0) 1231 #define RCC_TIM1CFGR_TIM1EN BIT(1) 1232 #define RCC_TIM1CFGR_TIM1LPEN BIT(2) 1233 1234 /* RCC_TIM2CFGR register fields */ 1235 #define RCC_TIM2CFGR_TIM2RST BIT(0) 1236 #define RCC_TIM2CFGR_TIM2EN BIT(1) 1237 #define RCC_TIM2CFGR_TIM2LPEN BIT(2) 1238 1239 /* RCC_TIM3CFGR register fields */ 1240 #define RCC_TIM3CFGR_TIM3RST BIT(0) 1241 #define RCC_TIM3CFGR_TIM3EN BIT(1) 1242 #define RCC_TIM3CFGR_TIM3LPEN BIT(2) 1243 1244 /* RCC_TIM4CFGR register fields */ 1245 #define RCC_TIM4CFGR_TIM4RST BIT(0) 1246 #define RCC_TIM4CFGR_TIM4EN BIT(1) 1247 #define RCC_TIM4CFGR_TIM4LPEN BIT(2) 1248 1249 /* RCC_TIM5CFGR register fields */ 1250 #define RCC_TIM5CFGR_TIM5RST BIT(0) 1251 #define RCC_TIM5CFGR_TIM5EN BIT(1) 1252 #define RCC_TIM5CFGR_TIM5LPEN BIT(2) 1253 1254 /* RCC_TIM6CFGR register fields */ 1255 #define RCC_TIM6CFGR_TIM6RST BIT(0) 1256 #define RCC_TIM6CFGR_TIM6EN BIT(1) 1257 #define RCC_TIM6CFGR_TIM6LPEN BIT(2) 1258 1259 /* RCC_TIM7CFGR register fields */ 1260 #define RCC_TIM7CFGR_TIM7RST BIT(0) 1261 #define RCC_TIM7CFGR_TIM7EN BIT(1) 1262 #define RCC_TIM7CFGR_TIM7LPEN BIT(2) 1263 1264 /* RCC_TIM8CFGR register fields */ 1265 #define RCC_TIM8CFGR_TIM8RST BIT(0) 1266 #define RCC_TIM8CFGR_TIM8EN BIT(1) 1267 #define RCC_TIM8CFGR_TIM8LPEN BIT(2) 1268 1269 /* RCC_TIM10CFGR register fields */ 1270 #define RCC_TIM10CFGR_TIM10RST BIT(0) 1271 #define RCC_TIM10CFGR_TIM10EN BIT(1) 1272 #define RCC_TIM10CFGR_TIM10LPEN BIT(2) 1273 1274 /* RCC_TIM11CFGR register fields */ 1275 #define RCC_TIM11CFGR_TIM11RST BIT(0) 1276 #define RCC_TIM11CFGR_TIM11EN BIT(1) 1277 #define RCC_TIM11CFGR_TIM11LPEN BIT(2) 1278 1279 /* RCC_TIM12CFGR register fields */ 1280 #define RCC_TIM12CFGR_TIM12RST BIT(0) 1281 #define RCC_TIM12CFGR_TIM12EN BIT(1) 1282 #define RCC_TIM12CFGR_TIM12LPEN BIT(2) 1283 1284 /* RCC_TIM13CFGR register fields */ 1285 #define RCC_TIM13CFGR_TIM13RST BIT(0) 1286 #define RCC_TIM13CFGR_TIM13EN BIT(1) 1287 #define RCC_TIM13CFGR_TIM13LPEN BIT(2) 1288 1289 /* RCC_TIM14CFGR register fields */ 1290 #define RCC_TIM14CFGR_TIM14RST BIT(0) 1291 #define RCC_TIM14CFGR_TIM14EN BIT(1) 1292 #define RCC_TIM14CFGR_TIM14LPEN BIT(2) 1293 1294 /* RCC_TIM15CFGR register fields */ 1295 #define RCC_TIM15CFGR_TIM15RST BIT(0) 1296 #define RCC_TIM15CFGR_TIM15EN BIT(1) 1297 #define RCC_TIM15CFGR_TIM15LPEN BIT(2) 1298 1299 /* RCC_TIM16CFGR register fields */ 1300 #define RCC_TIM16CFGR_TIM16RST BIT(0) 1301 #define RCC_TIM16CFGR_TIM16EN BIT(1) 1302 #define RCC_TIM16CFGR_TIM16LPEN BIT(2) 1303 1304 /* RCC_TIM17CFGR register fields */ 1305 #define RCC_TIM17CFGR_TIM17RST BIT(0) 1306 #define RCC_TIM17CFGR_TIM17EN BIT(1) 1307 #define RCC_TIM17CFGR_TIM17LPEN BIT(2) 1308 1309 /* RCC_LPTIM1CFGR register fields */ 1310 #define RCC_LPTIM1CFGR_LPTIM1RST BIT(0) 1311 #define RCC_LPTIM1CFGR_LPTIM1EN BIT(1) 1312 #define RCC_LPTIM1CFGR_LPTIM1LPEN BIT(2) 1313 1314 /* RCC_LPTIM2CFGR register fields */ 1315 #define RCC_LPTIM2CFGR_LPTIM2RST BIT(0) 1316 #define RCC_LPTIM2CFGR_LPTIM2EN BIT(1) 1317 #define RCC_LPTIM2CFGR_LPTIM2LPEN BIT(2) 1318 1319 /* RCC_LPTIM3CFGR register fields */ 1320 #define RCC_LPTIM3CFGR_LPTIM3RST BIT(0) 1321 #define RCC_LPTIM3CFGR_LPTIM3EN BIT(1) 1322 #define RCC_LPTIM3CFGR_LPTIM3LPEN BIT(2) 1323 1324 /* RCC_LPTIM4CFGR register fields */ 1325 #define RCC_LPTIM4CFGR_LPTIM4RST BIT(0) 1326 #define RCC_LPTIM4CFGR_LPTIM4EN BIT(1) 1327 #define RCC_LPTIM4CFGR_LPTIM4LPEN BIT(2) 1328 1329 /* RCC_LPTIM5CFGR register fields */ 1330 #define RCC_LPTIM5CFGR_LPTIM5RST BIT(0) 1331 #define RCC_LPTIM5CFGR_LPTIM5EN BIT(1) 1332 #define RCC_LPTIM5CFGR_LPTIM5LPEN BIT(2) 1333 1334 /* RCC_SPI1CFGR register fields */ 1335 #define RCC_SPI1CFGR_SPI1RST BIT(0) 1336 #define RCC_SPI1CFGR_SPI1EN BIT(1) 1337 #define RCC_SPI1CFGR_SPI1LPEN BIT(2) 1338 1339 /* RCC_SPI2CFGR register fields */ 1340 #define RCC_SPI2CFGR_SPI2RST BIT(0) 1341 #define RCC_SPI2CFGR_SPI2EN BIT(1) 1342 #define RCC_SPI2CFGR_SPI2LPEN BIT(2) 1343 1344 /* RCC_SPI3CFGR register fields */ 1345 #define RCC_SPI3CFGR_SPI3RST BIT(0) 1346 #define RCC_SPI3CFGR_SPI3EN BIT(1) 1347 #define RCC_SPI3CFGR_SPI3LPEN BIT(2) 1348 1349 /* RCC_SPI4CFGR register fields */ 1350 #define RCC_SPI4CFGR_SPI4RST BIT(0) 1351 #define RCC_SPI4CFGR_SPI4EN BIT(1) 1352 #define RCC_SPI4CFGR_SPI4LPEN BIT(2) 1353 1354 /* RCC_SPI5CFGR register fields */ 1355 #define RCC_SPI5CFGR_SPI5RST BIT(0) 1356 #define RCC_SPI5CFGR_SPI5EN BIT(1) 1357 #define RCC_SPI5CFGR_SPI5LPEN BIT(2) 1358 1359 /* RCC_SPI6CFGR register fields */ 1360 #define RCC_SPI6CFGR_SPI6RST BIT(0) 1361 #define RCC_SPI6CFGR_SPI6EN BIT(1) 1362 #define RCC_SPI6CFGR_SPI6LPEN BIT(2) 1363 1364 /* RCC_SPDIFRXCFGR register fields */ 1365 #define RCC_SPDIFRXCFGR_SPDIFRXRST BIT(0) 1366 #define RCC_SPDIFRXCFGR_SPDIFRXEN BIT(1) 1367 #define RCC_SPDIFRXCFGR_SPDIFRXLPEN BIT(2) 1368 1369 /* RCC_USART1CFGR register fields */ 1370 #define RCC_USART1CFGR_USART1RST BIT(0) 1371 #define RCC_USART1CFGR_USART1EN BIT(1) 1372 #define RCC_USART1CFGR_USART1LPEN BIT(2) 1373 1374 /* RCC_USART2CFGR register fields */ 1375 #define RCC_USART2CFGR_USART2RST BIT(0) 1376 #define RCC_USART2CFGR_USART2EN BIT(1) 1377 #define RCC_USART2CFGR_USART2LPEN BIT(2) 1378 1379 /* RCC_USART3CFGR register fields */ 1380 #define RCC_USART3CFGR_USART3RST BIT(0) 1381 #define RCC_USART3CFGR_USART3EN BIT(1) 1382 #define RCC_USART3CFGR_USART3LPEN BIT(2) 1383 1384 /* RCC_UART4CFGR register fields */ 1385 #define RCC_UART4CFGR_UART4RST BIT(0) 1386 #define RCC_UART4CFGR_UART4EN BIT(1) 1387 #define RCC_UART4CFGR_UART4LPEN BIT(2) 1388 1389 /* RCC_UART5CFGR register fields */ 1390 #define RCC_UART5CFGR_UART5RST BIT(0) 1391 #define RCC_UART5CFGR_UART5EN BIT(1) 1392 #define RCC_UART5CFGR_UART5LPEN BIT(2) 1393 1394 /* RCC_USART6CFGR register fields */ 1395 #define RCC_USART6CFGR_USART6RST BIT(0) 1396 #define RCC_USART6CFGR_USART6EN BIT(1) 1397 #define RCC_USART6CFGR_USART6LPEN BIT(2) 1398 1399 /* RCC_UART7CFGR register fields */ 1400 #define RCC_UART7CFGR_UART7RST BIT(0) 1401 #define RCC_UART7CFGR_UART7EN BIT(1) 1402 #define RCC_UART7CFGR_UART7LPEN BIT(2) 1403 1404 /* RCC_LPUART1CFGR register fields */ 1405 #define RCC_LPUART1CFGR_LPUART1RST BIT(0) 1406 #define RCC_LPUART1CFGR_LPUART1EN BIT(1) 1407 #define RCC_LPUART1CFGR_LPUART1LPEN BIT(2) 1408 1409 /* RCC_I2C1CFGR register fields */ 1410 #define RCC_I2C1CFGR_I2C1RST BIT(0) 1411 #define RCC_I2C1CFGR_I2C1EN BIT(1) 1412 #define RCC_I2C1CFGR_I2C1LPEN BIT(2) 1413 1414 /* RCC_I2C2CFGR register fields */ 1415 #define RCC_I2C2CFGR_I2C2RST BIT(0) 1416 #define RCC_I2C2CFGR_I2C2EN BIT(1) 1417 #define RCC_I2C2CFGR_I2C2LPEN BIT(2) 1418 1419 /* RCC_I2C3CFGR register fields */ 1420 #define RCC_I2C3CFGR_I2C3RST BIT(0) 1421 #define RCC_I2C3CFGR_I2C3EN BIT(1) 1422 #define RCC_I2C3CFGR_I2C3LPEN BIT(2) 1423 1424 /* RCC_SAI1CFGR register fields */ 1425 #define RCC_SAI1CFGR_SAI1RST BIT(0) 1426 #define RCC_SAI1CFGR_SAI1EN BIT(1) 1427 #define RCC_SAI1CFGR_SAI1LPEN BIT(2) 1428 1429 /* RCC_SAI2CFGR register fields */ 1430 #define RCC_SAI2CFGR_SAI2RST BIT(0) 1431 #define RCC_SAI2CFGR_SAI2EN BIT(1) 1432 #define RCC_SAI2CFGR_SAI2LPEN BIT(2) 1433 1434 /* RCC_SAI3CFGR register fields */ 1435 #define RCC_SAI3CFGR_SAI3RST BIT(0) 1436 #define RCC_SAI3CFGR_SAI3EN BIT(1) 1437 #define RCC_SAI3CFGR_SAI3LPEN BIT(2) 1438 1439 /* RCC_SAI4CFGR register fields */ 1440 #define RCC_SAI4CFGR_SAI4RST BIT(0) 1441 #define RCC_SAI4CFGR_SAI4EN BIT(1) 1442 #define RCC_SAI4CFGR_SAI4LPEN BIT(2) 1443 1444 /* RCC_MDF1CFGR register fields */ 1445 #define RCC_MDF1CFGR_MDF1RST BIT(0) 1446 #define RCC_MDF1CFGR_MDF1EN BIT(1) 1447 #define RCC_MDF1CFGR_MDF1LPEN BIT(2) 1448 1449 /* RCC_FDCANCFGR register fields */ 1450 #define RCC_FDCANCFGR_FDCANRST BIT(0) 1451 #define RCC_FDCANCFGR_FDCANEN BIT(1) 1452 #define RCC_FDCANCFGR_FDCANLPEN BIT(2) 1453 1454 /* RCC_HDPCFGR register fields */ 1455 #define RCC_HDPCFGR_HDPRST BIT(0) 1456 #define RCC_HDPCFGR_HDPEN BIT(1) 1457 1458 /* RCC_ADC1CFGR register fields */ 1459 #define RCC_ADC1CFGR_ADC1RST BIT(0) 1460 #define RCC_ADC1CFGR_ADC1EN BIT(1) 1461 #define RCC_ADC1CFGR_ADC1LPEN BIT(2) 1462 #define RCC_ADC1CFGR_ADC1KERSEL BIT(12) 1463 1464 /* RCC_ADC2CFGR register fields */ 1465 #define RCC_ADC2CFGR_ADC2RST BIT(0) 1466 #define RCC_ADC2CFGR_ADC2EN BIT(1) 1467 #define RCC_ADC2CFGR_ADC2LPEN BIT(2) 1468 #define RCC_ADC2CFGR_ADC2KERSEL_MASK GENMASK_32(13, 12) 1469 1470 /* RCC_ETH1CFGR register fields */ 1471 #define RCC_ETH1CFGR_ETH1RST BIT(0) 1472 #define RCC_ETH1CFGR_ETH1MACEN BIT(1) 1473 #define RCC_ETH1CFGR_ETH1MACLPEN BIT(2) 1474 #define RCC_ETH1CFGR_ETH1STPEN BIT(4) 1475 #define RCC_ETH1CFGR_ETH1EN BIT(5) 1476 #define RCC_ETH1CFGR_ETH1LPEN BIT(6) 1477 #define RCC_ETH1CFGR_ETH1TXEN BIT(8) 1478 #define RCC_ETH1CFGR_ETH1TXLPEN BIT(9) 1479 #define RCC_ETH1CFGR_ETH1RXEN BIT(10) 1480 #define RCC_ETH1CFGR_ETH1RXLPEN BIT(11) 1481 1482 /* RCC_ETH2CFGR register fields */ 1483 #define RCC_ETH2CFGR_ETH2RST BIT(0) 1484 #define RCC_ETH2CFGR_ETH2MACEN BIT(1) 1485 #define RCC_ETH2CFGR_ETH2MACLPEN BIT(2) 1486 #define RCC_ETH2CFGR_ETH2STPEN BIT(4) 1487 #define RCC_ETH2CFGR_ETH2EN BIT(5) 1488 #define RCC_ETH2CFGR_ETH2LPEN BIT(6) 1489 #define RCC_ETH2CFGR_ETH2TXEN BIT(8) 1490 #define RCC_ETH2CFGR_ETH2TXLPEN BIT(9) 1491 #define RCC_ETH2CFGR_ETH2RXEN BIT(10) 1492 #define RCC_ETH2CFGR_ETH2RXLPEN BIT(11) 1493 1494 /* RCC_USBHCFGR register fields */ 1495 #define RCC_USBHCFGR_USBHRST BIT(0) 1496 #define RCC_USBHCFGR_USBHEN BIT(1) 1497 #define RCC_USBHCFGR_USBHLPEN BIT(2) 1498 1499 /* RCC_USB2PHY1CFGR register fields */ 1500 #define RCC_USB2PHY1CFGR_USB2PHY1RST BIT(0) 1501 #define RCC_USB2PHY1CFGR_USB2PHY1EN BIT(1) 1502 #define RCC_USB2PHY1CFGR_USB2PHY1LPEN BIT(2) 1503 #define RCC_USB2PHY1CFGR_USB2PHY1CKREFSEL BIT(15) 1504 1505 /* RCC_OTGCFGR register fields */ 1506 #define RCC_OTGCFGR_OTGRST BIT(0) 1507 #define RCC_OTGCFGR_OTGEN BIT(1) 1508 #define RCC_OTGCFGR_OTGLPEN BIT(2) 1509 1510 /* RCC_USB2PHY2CFGR register fields */ 1511 #define RCC_USB2PHY2CFGR_USB2PHY2RST BIT(0) 1512 #define RCC_USB2PHY2CFGR_USB2PHY2EN BIT(1) 1513 #define RCC_USB2PHY2CFGR_USB2PHY2LPEN BIT(2) 1514 #define RCC_USB2PHY2CFGR_USB2PHY2CKREFSEL BIT(15) 1515 1516 /* RCC_STGENCFGR register fields */ 1517 #define RCC_STGENCFGR_STGENEN BIT(1) 1518 #define RCC_STGENCFGR_STGENLPEN BIT(2) 1519 #define RCC_STGENCFGR_STGENSTPEN BIT(4) 1520 1521 /* RCC_SDMMC1CFGR register fields */ 1522 #define RCC_SDMMC1CFGR_SDMMC1RST BIT(0) 1523 #define RCC_SDMMC1CFGR_SDMMC1EN BIT(1) 1524 #define RCC_SDMMC1CFGR_SDMMC1LPEN BIT(2) 1525 #define RCC_SDMMC1CFGR_SDMMC1DLLRST BIT(16) 1526 1527 /* RCC_SDMMC2CFGR register fields */ 1528 #define RCC_SDMMC2CFGR_SDMMC2RST BIT(0) 1529 #define RCC_SDMMC2CFGR_SDMMC2EN BIT(1) 1530 #define RCC_SDMMC2CFGR_SDMMC2LPEN BIT(2) 1531 #define RCC_SDMMC2CFGR_SDMMC2DLLRST BIT(16) 1532 1533 /* RCC_SDMMC3CFGR register fields */ 1534 #define RCC_SDMMC3CFGR_SDMMC3RST BIT(0) 1535 #define RCC_SDMMC3CFGR_SDMMC3EN BIT(1) 1536 #define RCC_SDMMC3CFGR_SDMMC3LPEN BIT(2) 1537 #define RCC_SDMMC3CFGR_SDMMC3DLLRST BIT(16) 1538 1539 /* RCC_LTDCCFGR register fields */ 1540 #define RCC_LTDCCFGR_LTDCRST BIT(0) 1541 #define RCC_LTDCCFGR_LTDCEN BIT(1) 1542 #define RCC_LTDCCFGR_LTDCLPEN BIT(2) 1543 1544 /* RCC_CSICFGR register fields */ 1545 #define RCC_CSICFGR_CSIRST BIT(0) 1546 #define RCC_CSICFGR_CSIEN BIT(1) 1547 #define RCC_CSICFGR_CSILPEN BIT(2) 1548 1549 /* RCC_DCMIPPCFGR register fields */ 1550 #define RCC_DCMIPPCFGR_DCMIPPRST BIT(0) 1551 #define RCC_DCMIPPCFGR_DCMIPPEN BIT(1) 1552 #define RCC_DCMIPPCFGR_DCMIPPLPEN BIT(2) 1553 1554 /* RCC_DCMIPSSICFGR register fields */ 1555 #define RCC_DCMIPSSICFGR_DCMIPSSIRST BIT(0) 1556 #define RCC_DCMIPSSICFGR_DCMIPSSIEN BIT(1) 1557 #define RCC_DCMIPSSICFGR_DCMIPSSILPEN BIT(2) 1558 1559 /* RCC_RNG1CFGR register fields */ 1560 #define RCC_RNG1CFGR_RNG1RST BIT(0) 1561 #define RCC_RNG1CFGR_RNG1EN BIT(1) 1562 #define RCC_RNG1CFGR_RNG1LPEN BIT(2) 1563 1564 /* RCC_RNG2CFGR register fields */ 1565 #define RCC_RNG2CFGR_RNG2RST BIT(0) 1566 #define RCC_RNG2CFGR_RNG2EN BIT(1) 1567 #define RCC_RNG2CFGR_RNG2LPEN BIT(2) 1568 1569 /* RCC_PKACFGR register fields */ 1570 #define RCC_PKACFGR_PKARST BIT(0) 1571 #define RCC_PKACFGR_PKAEN BIT(1) 1572 #define RCC_PKACFGR_PKALPEN BIT(2) 1573 1574 /* RCC_SAESCFGR register fields */ 1575 #define RCC_SAESCFGR_SAESRST BIT(0) 1576 #define RCC_SAESCFGR_SAESEN BIT(1) 1577 #define RCC_SAESCFGR_SAESLPEN BIT(2) 1578 1579 /* RCC_HASH1CFGR register fields */ 1580 #define RCC_HASH1CFGR_HASH1RST BIT(0) 1581 #define RCC_HASH1CFGR_HASH1EN BIT(1) 1582 #define RCC_HASH1CFGR_HASH1LPEN BIT(2) 1583 1584 /* RCC_HASH2CFGR register fields */ 1585 #define RCC_HASH2CFGR_HASH2RST BIT(0) 1586 #define RCC_HASH2CFGR_HASH2EN BIT(1) 1587 #define RCC_HASH2CFGR_HASH2LPEN BIT(2) 1588 1589 /* RCC_CRYP1CFGR register fields */ 1590 #define RCC_CRYP1CFGR_CRYP1RST BIT(0) 1591 #define RCC_CRYP1CFGR_CRYP1EN BIT(1) 1592 #define RCC_CRYP1CFGR_CRYP1LPEN BIT(2) 1593 1594 /* RCC_CRYP2CFGR register fields */ 1595 #define RCC_CRYP2CFGR_CRYP2RST BIT(0) 1596 #define RCC_CRYP2CFGR_CRYP2EN BIT(1) 1597 #define RCC_CRYP2CFGR_CRYP2LPEN BIT(2) 1598 1599 /* RCC_IWDG1CFGR register fields */ 1600 #define RCC_IWDG1CFGR_IWDG1EN BIT(1) 1601 #define RCC_IWDG1CFGR_IWDG1LPEN BIT(2) 1602 1603 /* RCC_IWDG2CFGR register fields */ 1604 #define RCC_IWDG2CFGR_IWDG2EN BIT(1) 1605 #define RCC_IWDG2CFGR_IWDG2LPEN BIT(2) 1606 1607 /* RCC_IWDG3CFGR register fields */ 1608 #define RCC_IWDG3CFGR_IWDG3EN BIT(1) 1609 #define RCC_IWDG3CFGR_IWDG3LPEN BIT(2) 1610 1611 /* RCC_IWDG4CFGR register fields */ 1612 #define RCC_IWDG4CFGR_IWDG4EN BIT(1) 1613 #define RCC_IWDG4CFGR_IWDG4LPEN BIT(2) 1614 1615 /* RCC_WWDG1CFGR register fields */ 1616 #define RCC_WWDG1CFGR_WWDG1RST BIT(0) 1617 #define RCC_WWDG1CFGR_WWDG1EN BIT(1) 1618 #define RCC_WWDG1CFGR_WWDG1LPEN BIT(2) 1619 1620 /* RCC_VREFCFGR register fields */ 1621 #define RCC_VREFCFGR_VREFRST BIT(0) 1622 #define RCC_VREFCFGR_VREFEN BIT(1) 1623 #define RCC_VREFCFGR_VREFLPEN BIT(2) 1624 1625 /* RCC_DTSCFGR register fields */ 1626 #define RCC_DTSCFGR_DTSRST BIT(0) 1627 #define RCC_DTSCFGR_DTSEN BIT(1) 1628 #define RCC_DTSCFGR_DTSLPEN BIT(2) 1629 #define RCC_DTSCFGR_DTSKERSEL_MASK GENMASK_32(13, 12) 1630 1631 /* RCC_CRCCFGR register fields */ 1632 #define RCC_CRCCFGR_CRCRST BIT(0) 1633 #define RCC_CRCCFGR_CRCEN BIT(1) 1634 #define RCC_CRCCFGR_CRCLPEN BIT(2) 1635 1636 /* RCC_SERCCFGR register fields */ 1637 #define RCC_SERCCFGR_SERCRST BIT(0) 1638 #define RCC_SERCCFGR_SERCEN BIT(1) 1639 #define RCC_SERCCFGR_SERCLPEN BIT(2) 1640 1641 /* RCC_DDRPERFMCFGR register fields */ 1642 #define RCC_DDRPERFMCFGR_DDRPERFMRST BIT(0) 1643 #define RCC_DDRPERFMCFGR_DDRPERFMEN BIT(1) 1644 #define RCC_DDRPERFMCFGR_DDRPERFMLPEN BIT(2) 1645 1646 /* RCC_I3C1CFGR register fields */ 1647 #define RCC_I3C1CFGR_I3C1RST BIT(0) 1648 #define RCC_I3C1CFGR_I3C1EN BIT(1) 1649 #define RCC_I3C1CFGR_I3C1LPEN BIT(2) 1650 1651 /* RCC_I3C2CFGR register fields */ 1652 #define RCC_I3C2CFGR_I3C2RST BIT(0) 1653 #define RCC_I3C2CFGR_I3C2EN BIT(1) 1654 #define RCC_I3C2CFGR_I3C2LPEN BIT(2) 1655 1656 /* RCC_I3C3CFGR register fields */ 1657 #define RCC_I3C3CFGR_I3C3RST BIT(0) 1658 #define RCC_I3C3CFGR_I3C3EN BIT(1) 1659 #define RCC_I3C3CFGR_I3C3LPEN BIT(2) 1660 1661 /* RCC_MUXSELCFGR register fields */ 1662 #define RCC_MUXSELCFGR_MUXSEL0_MASK GENMASK_32(2, 0) 1663 #define RCC_MUXSELCFGR_MUXSEL1_MASK GENMASK_32(6, 4) 1664 #define RCC_MUXSELCFGR_MUXSEL2_MASK GENMASK_32(10, 8) 1665 #define RCC_MUXSELCFGR_MUXSEL3_MASK GENMASK_32(14, 12) 1666 #define RCC_MUXSELCFGR_MUXSEL4_MASK GENMASK_32(18, 16) 1667 #define RCC_MUXSELCFGR_MUXSEL5_MASK GENMASK_32(21, 20) 1668 #define RCC_MUXSELCFGR_MUXSEL6_MASK GENMASK_32(25, 24) 1669 1670 /* RCC_XBAR0CFGR register fields */ 1671 #define RCC_XBAR0CFGR_XBAR0SEL_MASK GENMASK_32(3, 0) 1672 #define RCC_XBAR0CFGR_XBAR0SEL_SHIFT 0 1673 #define RCC_XBAR0CFGR_XBAR0EN BIT(6) 1674 #define RCC_XBAR0CFGR_XBAR0STS BIT(7) 1675 1676 /* RCC_PREDIVxCFGR register fields */ 1677 #define RCC_PREDIV0CFGR_PREDIV0_MASK GENMASK_32(9, 0) 1678 #define RCC_PREDIV0CFGR_PREDIV0_SHIFT 0 1679 1680 /* RCC_FINDIVxCFGR register fields */ 1681 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) 1682 #define RCC_FINDIV0CFGR_FINDIV0_SHIFT 0 1683 #define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) 1684 1685 /* RCC_FINDIV0CFGR register fields */ 1686 #define RCC_FINDIV0CFGR_FINDIV0_MASK GENMASK_32(5, 0) 1687 #define RCC_FINDIV0CFGR_FINDIV0EN BIT(6) 1688 1689 /* RCC_PREDIVSR1 register fields */ 1690 #define RCC_PREDIVSR1_PREDIVSTS_MASK GENMASK_32(31, 0) 1691 1692 /* RCC_PREDIVSR2 register fields */ 1693 #define RCC_PREDIVSR2_PREDIVSTS_MASK GENMASK_32(31, 0) 1694 1695 /* RCC_FINDIVSR1 register fields */ 1696 #define RCC_FINDIVSR1_FINDIVSTS_MASK GENMASK_32(31, 0) 1697 1698 /* RCC_FINDIVSR2 register fields */ 1699 #define RCC_FINDIVSR2_FINDIVSTS_MASK GENMASK_32(31, 0) 1700 1701 /* RCC_FCALCOBS0CFGR register fields */ 1702 #define RCC_FCALCOBS0CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 1703 #define RCC_FCALCOBS0CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 1704 #define RCC_FCALCOBS0CFGR_FCALCCKEXTSEL BIT(15) 1705 #define RCC_FCALCOBS0CFGR_CKOBSEXTSEL BIT(16) 1706 #define RCC_FCALCOBS0CFGR_FCALCCKINV BIT(17) 1707 #define RCC_FCALCOBS0CFGR_CKOBSINV BIT(18) 1708 #define RCC_FCALCOBS0CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 1709 #define RCC_FCALCOBS0CFGR_FCALCCKEN BIT(25) 1710 #define RCC_FCALCOBS0CFGR_CKOBSEN BIT(26) 1711 #define RCC_FCALCOBS0CFGR_CKINTSEL_SHIFT 0 1712 #define RCC_FCALCOBS0CFGR_CKEXTSEL_SHIFT 8 1713 #define RCC_FCALCOBS0CFGR_CKOBSDIV_SHIFT 22 1714 1715 /* RCC_FCALCOBS1CFGR register fields */ 1716 #define RCC_FCALCOBS1CFGR_CKINTSEL_MASK GENMASK_32(7, 0) 1717 #define RCC_FCALCOBS1CFGR_CKEXTSEL_MASK GENMASK_32(10, 8) 1718 #define RCC_FCALCOBS1CFGR_CKOBSEXTSEL BIT(16) 1719 #define RCC_FCALCOBS1CFGR_CKOBSINV BIT(18) 1720 #define RCC_FCALCOBS1CFGR_CKOBSDIV_MASK GENMASK_32(24, 22) 1721 #define RCC_FCALCOBS1CFGR_CKOBSEN BIT(26) 1722 #define RCC_FCALCOBS1CFGR_FCALCRSTN BIT(27) 1723 #define RCC_FCALCOBS1CFGR_CKINTSEL_SHIFT 0 1724 #define RCC_FCALCOBS1CFGR_CKEXTSEL_SHIFT 8 1725 #define RCC_FCALCOBS1CFGR_CKOBSDIV_SHIFT 22 1726 1727 /* RCC_FCALCREFCFGR register fields */ 1728 #define RCC_FCALCREFCFGR_FCALCREFCKSEL_MASK GENMASK_32(2, 0) 1729 1730 /* RCC_FCALCCR1 register fields */ 1731 #define RCC_FCALCCR1_FCALCRUN BIT(0) 1732 1733 /* RCC_FCALCCR2 register fields */ 1734 #define RCC_FCALCCR2_FCALCMD_MASK GENMASK_32(4, 3) 1735 #define RCC_FCALCCR2_FCALCTWC_MASK GENMASK_32(14, 11) 1736 #define RCC_FCALCCR2_FCALCTYP_MASK GENMASK_32(21, 17) 1737 #define RCC_FCALCCR2_FCALCMD_SHIFT 3 1738 #define RCC_FCALCCR2_FCALCTWC_SHIFT 11 1739 #define RCC_FCALCCR2_FCALCTYP_SHIFT 17 1740 1741 /* RCC_FCALCSR register fields */ 1742 #define RCC_FCALCSR_FVAL_MASK GENMASK_32(15, 0) 1743 #define RCC_FCALCSR_FCALCSTS BIT(19) 1744 #define RCC_FCALCSR_FVAL_OVERFLOW BIT(16) 1745 1746 /* RCC_VERR register fields */ 1747 #define RCC_VERR_MINREV_MASK GENMASK_32(3, 0) 1748 #define RCC_VERR_MAJREV_MASK GENMASK_32(7, 4) 1749 1750 /* RCC_IDR register fields */ 1751 #define RCC_IDR_ID_MASK GENMASK_32(31, 0) 1752 1753 /* RCC_SIDR register fields */ 1754 #define RCC_SIDR_SID_MASK GENMASK_32(31, 0) 1755 1756 #endif /* __DRIVERS_STM32MP21_RCC_H */ 1757