1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* 3 * Copyright (c) 2017-2018, STMicroelectronics 4 */ 5 6 #ifndef __DRIVERS_STM32MP1_RCC_H__ 7 #define __DRIVERS_STM32MP1_RCC_H__ 8 9 #include <io.h> 10 #include <stdbool.h> 11 #include <util.h> 12 13 #define RCC_TZCR 0x00 14 #define RCC_OCENSETR 0x0C 15 #define RCC_OCENCLRR 0x10 16 #define RCC_HSICFGR 0x18 17 #define RCC_CSICFGR 0x1C 18 #define RCC_MPCKSELR 0x20 19 #define RCC_ASSCKSELR 0x24 20 #define RCC_RCK12SELR 0x28 21 #define RCC_MPCKDIVR 0x2C 22 #define RCC_AXIDIVR 0x30 23 #define RCC_APB4DIVR 0x3C 24 #define RCC_APB5DIVR 0x40 25 #define RCC_RTCDIVR 0x44 26 #define RCC_MSSCKSELR 0x48 27 #define RCC_PLL1CR 0x80 28 #define RCC_PLL1CFGR1 0x84 29 #define RCC_PLL1CFGR2 0x88 30 #define RCC_PLL1FRACR 0x8C 31 #define RCC_PLL1CSGR 0x90 32 #define RCC_PLL2CR 0x94 33 #define RCC_PLL2CFGR1 0x98 34 #define RCC_PLL2CFGR2 0x9C 35 #define RCC_PLL2FRACR 0xA0 36 #define RCC_PLL2CSGR 0xA4 37 #define RCC_I2C46CKSELR 0xC0 38 #define RCC_SPI6CKSELR 0xC4 39 #define RCC_UART1CKSELR 0xC8 40 #define RCC_RNG1CKSELR 0xCC 41 #define RCC_CPERCKSELR 0xD0 42 #define RCC_STGENCKSELR 0xD4 43 #define RCC_DDRITFCR 0xD8 44 #define RCC_MP_BOOTCR 0x100 45 #define RCC_MP_SREQSETR 0x104 46 #define RCC_MP_SREQCLRR 0x108 47 #define RCC_MP_GCR 0x10C 48 #define RCC_MP_APRSTCR 0x110 49 #define RCC_MP_APRSTSR 0x114 50 #define RCC_BDCR 0x140 51 #define RCC_RDLSICR 0x144 52 #define RCC_APB4RSTSETR 0x180 53 #define RCC_APB4RSTCLRR 0x184 54 #define RCC_APB5RSTSETR 0x188 55 #define RCC_APB5RSTCLRR 0x18C 56 #define RCC_AHB5RSTSETR 0x190 57 #define RCC_AHB5RSTCLRR 0x194 58 #define RCC_AHB6RSTSETR 0x198 59 #define RCC_AHB6RSTCLRR 0x19C 60 #define RCC_TZAHB6RSTSETR 0x1A0 61 #define RCC_TZAHB6RSTCLRR 0x1A4 62 #define RCC_MP_APB4ENSETR 0x200 63 #define RCC_MP_APB4ENCLRR 0x204 64 #define RCC_MP_APB5ENSETR 0x208 65 #define RCC_MP_APB5ENCLRR 0x20C 66 #define RCC_MP_AHB5ENSETR 0x210 67 #define RCC_MP_AHB5ENCLRR 0x214 68 #define RCC_MP_AHB6ENSETR 0x218 69 #define RCC_MP_AHB6ENCLRR 0x21C 70 #define RCC_MP_TZAHB6ENSETR 0x220 71 #define RCC_MP_TZAHB6ENCLRR 0x224 72 #define RCC_MC_APB4ENSETR 0x280 73 #define RCC_MC_APB4ENCLRR 0x284 74 #define RCC_MC_APB5ENSETR 0x288 75 #define RCC_MC_APB5ENCLRR 0x28C 76 #define RCC_MC_AHB5ENSETR 0x290 77 #define RCC_MC_AHB5ENCLRR 0x294 78 #define RCC_MC_AHB6ENSETR 0x298 79 #define RCC_MC_AHB6ENCLRR 0x29C 80 #define RCC_MP_APB4LPENSETR 0x300 81 #define RCC_MP_APB4LPENCLRR 0x304 82 #define RCC_MP_APB5LPENSETR 0x308 83 #define RCC_MP_APB5LPENCLRR 0x30C 84 #define RCC_MP_AHB5LPENSETR 0x310 85 #define RCC_MP_AHB5LPENCLRR 0x314 86 #define RCC_MP_AHB6LPENSETR 0x318 87 #define RCC_MP_AHB6LPENCLRR 0x31C 88 #define RCC_MP_TZAHB6LPENSETR 0x320 89 #define RCC_MP_TZAHB6LPENCLRR 0x324 90 #define RCC_MC_APB4LPENSETR 0x380 91 #define RCC_MC_APB4LPENCLRR 0x384 92 #define RCC_MC_APB5LPENSETR 0x388 93 #define RCC_MC_APB5LPENCLRR 0x38C 94 #define RCC_MC_AHB5LPENSETR 0x390 95 #define RCC_MC_AHB5LPENCLRR 0x394 96 #define RCC_MC_AHB6LPENSETR 0x398 97 #define RCC_MC_AHB6LPENCLRR 0x39C 98 #define RCC_BR_RSTSCLRR 0x400 99 #define RCC_MP_GRSTCSETR 0x404 100 #define RCC_MP_RSTSCLRR 0x408 101 #define RCC_MP_IWDGFZSETR 0x40C 102 #define RCC_MP_IWDGFZCLRR 0x410 103 #define RCC_MP_CIER 0x414 104 #define RCC_MP_CIFR 0x418 105 #define RCC_PWRLPDLYCR 0x41C 106 #define RCC_MP_RSTSSETR 0x420 107 #define RCC_MCO1CFGR 0x800 108 #define RCC_MCO2CFGR 0x804 109 #define RCC_OCRDYR 0x808 110 #define RCC_DBGCFGR 0x80C 111 #define RCC_RCK3SELR 0x820 112 #define RCC_RCK4SELR 0x824 113 #define RCC_TIMG1PRER 0x828 114 #define RCC_TIMG2PRER 0x82C 115 #define RCC_MCUDIVR 0x830 116 #define RCC_APB1DIVR 0x834 117 #define RCC_APB2DIVR 0x838 118 #define RCC_APB3DIVR 0x83C 119 #define RCC_PLL3CR 0x880 120 #define RCC_PLL3CFGR1 0x884 121 #define RCC_PLL3CFGR2 0x888 122 #define RCC_PLL3FRACR 0x88C 123 #define RCC_PLL3CSGR 0x890 124 #define RCC_PLL4CR 0x894 125 #define RCC_PLL4CFGR1 0x898 126 #define RCC_PLL4CFGR2 0x89C 127 #define RCC_PLL4FRACR 0x8A0 128 #define RCC_PLL4CSGR 0x8A4 129 #define RCC_I2C12CKSELR 0x8C0 130 #define RCC_I2C35CKSELR 0x8C4 131 #define RCC_SAI1CKSELR 0x8C8 132 #define RCC_SAI2CKSELR 0x8CC 133 #define RCC_SAI3CKSELR 0x8D0 134 #define RCC_SAI4CKSELR 0x8D4 135 #define RCC_SPI2S1CKSELR 0x8D8 136 #define RCC_SPI2S23CKSELR 0x8DC 137 #define RCC_SPI45CKSELR 0x8E0 138 #define RCC_UART6CKSELR 0x8E4 139 #define RCC_UART24CKSELR 0x8E8 140 #define RCC_UART35CKSELR 0x8EC 141 #define RCC_UART78CKSELR 0x8F0 142 #define RCC_SDMMC12CKSELR 0x8F4 143 #define RCC_SDMMC3CKSELR 0x8F8 144 #define RCC_ETHCKSELR 0x8FC 145 #define RCC_QSPICKSELR 0x900 146 #define RCC_FMCCKSELR 0x904 147 #define RCC_FDCANCKSELR 0x90C 148 #define RCC_SPDIFCKSELR 0x914 149 #define RCC_CECCKSELR 0x918 150 #define RCC_USBCKSELR 0x91C 151 #define RCC_RNG2CKSELR 0x920 152 #define RCC_DSICKSELR 0x924 153 #define RCC_ADCCKSELR 0x928 154 #define RCC_LPTIM45CKSELR 0x92C 155 #define RCC_LPTIM23CKSELR 0x930 156 #define RCC_LPTIM1CKSELR 0x934 157 #define RCC_APB1RSTSETR 0x980 158 #define RCC_APB1RSTCLRR 0x984 159 #define RCC_APB2RSTSETR 0x988 160 #define RCC_APB2RSTCLRR 0x98C 161 #define RCC_APB3RSTSETR 0x990 162 #define RCC_APB3RSTCLRR 0x994 163 #define RCC_AHB2RSTSETR 0x998 164 #define RCC_AHB2RSTCLRR 0x99C 165 #define RCC_AHB3RSTSETR 0x9A0 166 #define RCC_AHB3RSTCLRR 0x9A4 167 #define RCC_AHB4RSTSETR 0x9A8 168 #define RCC_AHB4RSTCLRR 0x9AC 169 #define RCC_MP_APB1ENSETR 0xA00 170 #define RCC_MP_APB1ENCLRR 0xA04 171 #define RCC_MP_APB2ENSETR 0xA08 172 #define RCC_MP_APB2ENCLRR 0xA0C 173 #define RCC_MP_APB3ENSETR 0xA10 174 #define RCC_MP_APB3ENCLRR 0xA14 175 #define RCC_MP_AHB2ENSETR 0xA18 176 #define RCC_MP_AHB2ENCLRR 0xA1C 177 #define RCC_MP_AHB3ENSETR 0xA20 178 #define RCC_MP_AHB3ENCLRR 0xA24 179 #define RCC_MP_AHB4ENSETR 0xA28 180 #define RCC_MP_AHB4ENCLRR 0xA2C 181 #define RCC_MP_MLAHBENSETR 0xA38 182 #define RCC_MP_MLAHBENCLRR 0xA3C 183 #define RCC_MC_APB1ENSETR 0xA80 184 #define RCC_MC_APB1ENCLRR 0xA84 185 #define RCC_MC_APB2ENSETR 0xA88 186 #define RCC_MC_APB2ENCLRR 0xA8C 187 #define RCC_MC_APB3ENSETR 0xA90 188 #define RCC_MC_APB3ENCLRR 0xA94 189 #define RCC_MC_AHB2ENSETR 0xA98 190 #define RCC_MC_AHB2ENCLRR 0xA9C 191 #define RCC_MC_AHB3ENSETR 0xAA0 192 #define RCC_MC_AHB3ENCLRR 0xAA4 193 #define RCC_MC_AHB4ENSETR 0xAA8 194 #define RCC_MC_AHB4ENCLRR 0xAAC 195 #define RCC_MC_AXIMENSETR 0xAB0 196 #define RCC_MC_AXIMENCLRR 0xAB4 197 #define RCC_MC_MLAHBENSETR 0xAB8 198 #define RCC_MC_MLAHBENCLRR 0xABC 199 #define RCC_MP_APB1LPENSETR 0xB00 200 #define RCC_MP_APB1LPENCLRR 0xB04 201 #define RCC_MP_APB2LPENSETR 0xB08 202 #define RCC_MP_APB2LPENCLRR 0xB0C 203 #define RCC_MP_APB3LPENSETR 0xB10 204 #define RCC_MP_APB3LPENCLRR 0xB14 205 #define RCC_MP_AHB2LPENSETR 0xB18 206 #define RCC_MP_AHB2LPENCLRR 0xB1C 207 #define RCC_MP_AHB3LPENSETR 0xB20 208 #define RCC_MP_AHB3LPENCLRR 0xB24 209 #define RCC_MP_AHB4LPENSETR 0xB28 210 #define RCC_MP_AHB4LPENCLRR 0xB2C 211 #define RCC_MP_AXIMLPENSETR 0xB30 212 #define RCC_MP_AXIMLPENCLRR 0xB34 213 #define RCC_MP_MLAHBLPENSETR 0xB38 214 #define RCC_MP_MLAHBLPENCLRR 0xB3C 215 #define RCC_MC_APB1LPENSETR 0xB80 216 #define RCC_MC_APB1LPENCLRR 0xB84 217 #define RCC_MC_APB2LPENSETR 0xB88 218 #define RCC_MC_APB2LPENCLRR 0xB8C 219 #define RCC_MC_APB3LPENSETR 0xB90 220 #define RCC_MC_APB3LPENCLRR 0xB94 221 #define RCC_MC_AHB2LPENSETR 0xB98 222 #define RCC_MC_AHB2LPENCLRR 0xB9C 223 #define RCC_MC_AHB3LPENSETR 0xBA0 224 #define RCC_MC_AHB3LPENCLRR 0xBA4 225 #define RCC_MC_AHB4LPENSETR 0xBA8 226 #define RCC_MC_AHB4LPENCLRR 0xBAC 227 #define RCC_MC_AXIMLPENSETR 0xBB0 228 #define RCC_MC_AXIMLPENCLRR 0xBB4 229 #define RCC_MC_MLAHBLPENSETR 0xBB8 230 #define RCC_MC_MLAHBLPENCLRR 0xBBC 231 #define RCC_MC_RSTSCLRR 0xC00 232 #define RCC_MC_CIER 0xC14 233 #define RCC_MC_CIFR 0xC18 234 #define RCC_VERR 0xFF4 235 #define RCC_IDR 0xFF8 236 #define RCC_SIDR 0xFFC 237 238 #define RCC_OFFSET_MASK GENMASK_32(11, 0) 239 240 /* Values for RCC_TZCR register */ 241 #define RCC_TZCR_TZEN BIT(0) 242 #define RCC_TZCR_MCKPROT BIT(1) 243 244 /* Used for most of RCC_<x>SELR registers */ 245 #define RCC_SELR_SRC_MASK GENMASK_32(2, 0) 246 #define RCC_SELR_REFCLK_SRC_MASK GENMASK_32(1, 0) 247 #define RCC_SELR_SRCRDY BIT(31) 248 249 /* Values of RCC_MPCKSELR register */ 250 #define RCC_MPCKSELR_HSI 0x00000000 251 #define RCC_MPCKSELR_HSE 0x00000001 252 #define RCC_MPCKSELR_PLL 0x00000002 253 #define RCC_MPCKSELR_PLL_MPUDIV 0x00000003 254 255 /* Values of RCC_ASSCKSELR register */ 256 #define RCC_ASSCKSELR_HSI 0x00000000 257 #define RCC_ASSCKSELR_HSE 0x00000001 258 #define RCC_ASSCKSELR_PLL 0x00000002 259 260 /* Values of RCC_MSSCKSELR register */ 261 #define RCC_MSSCKSELR_HSI 0x00000000 262 #define RCC_MSSCKSELR_HSE 0x00000001 263 #define RCC_MSSCKSELR_CSI 0x00000002 264 #define RCC_MSSCKSELR_PLL 0x00000003 265 266 /* Values of RCC_CPERCKSELR register */ 267 #define RCC_CPERCKSELR_HSI 0x00000000 268 #define RCC_CPERCKSELR_CSI 0x00000001 269 #define RCC_CPERCKSELR_HSE 0x00000002 270 271 /* used for most of RCC_<x>DIVR registers: max div for RTC */ 272 #define RCC_DIVR_DIV_MASK GENMASK_32(5, 0) 273 #define RCC_DIVR_DIVRDY BIT(31) 274 275 /* Masks for specific DIVR registers */ 276 #define RCC_APBXDIV_MASK GENMASK_32(2, 0) 277 #define RCC_MPUDIV_MASK GENMASK_32(2, 0) 278 #define RCC_AXIDIV_MASK GENMASK_32(2, 0) 279 #define RCC_MCUDIV_MASK GENMASK_32(3, 0) 280 281 /* Used for TIMER Prescaler */ 282 #define RCC_TIMGXPRER_TIMGXPRE BIT(0) 283 284 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */ 285 #define RCC_MP_ENCLRR_OFFSET 4u 286 287 /* Offset between RCC_MP_xxxRSTSETR and RCC_MP_xxxRSTCLRR registers */ 288 #define RCC_MP_RSTCLRR_OFFSET 4u 289 290 /* Fields of RCC_BDCR register */ 291 #define RCC_BDCR_LSEON BIT(0) 292 #define RCC_BDCR_LSEBYP BIT(1) 293 #define RCC_BDCR_LSERDY BIT(2) 294 #define RCC_BDCR_DIGBYP BIT(3) 295 #define RCC_BDCR_LSEDRV_MASK GENMASK_32(5, 4) 296 #define RCC_BDCR_LSEDRV_SHIFT 4 297 #define RCC_BDCR_LSECSSON BIT(8) 298 #define RCC_BDCR_RTCCKEN_POS 20 299 #define RCC_BDCR_RTCCKEN BIT(RCC_BDCR_RTCCKEN_POS) 300 #define RCC_BDCR_RTCSRC_MASK GENMASK_32(17, 16) 301 #define RCC_BDCR_RTCSRC_SHIFT 16 302 #define RCC_BDCR_VSWRST BIT(31) 303 304 /* Fields of RCC_RDLSICR register */ 305 #define RCC_RDLSICR_LSION BIT(0) 306 #define RCC_RDLSICR_LSIRDY BIT(1) 307 308 /* Used for all RCC_PLL<n>CR registers */ 309 #define RCC_PLLNCR_PLLON BIT(0) 310 #define RCC_PLLNCR_PLLRDY BIT(1) 311 #define RCC_PLLNCR_SSCG_CTRL BIT(2) 312 #define RCC_PLLNCR_DIVPEN BIT(4) 313 #define RCC_PLLNCR_DIVQEN BIT(5) 314 #define RCC_PLLNCR_DIVREN BIT(6) 315 #define RCC_PLLNCR_DIVEN_SHIFT 4 316 317 /* Used for all RCC_PLL<n>CFGR1 registers */ 318 #define RCC_PLLNCFGR1_DIVM_SHIFT 16 319 #define RCC_PLLNCFGR1_DIVM_MASK GENMASK_32(21, 16) 320 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 321 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK_32(8, 0) 322 /* Only for PLL3 and PLL4 */ 323 #define RCC_PLLNCFGR1_IFRGE_SHIFT 24 324 #define RCC_PLLNCFGR1_IFRGE_MASK GENMASK_32(25, 24) 325 326 /* Used for all RCC_PLL<n>CFGR2 registers */ 327 #define RCC_PLLNCFGR2_DIVX_MASK GENMASK_32(6, 0) 328 #define RCC_PLLNCFGR2_DIVP_SHIFT 0 329 #define RCC_PLLNCFGR2_DIVP_MASK GENMASK_32(6, 0) 330 #define RCC_PLLNCFGR2_DIVQ_SHIFT 8 331 #define RCC_PLLNCFGR2_DIVQ_MASK GENMASK_32(14, 8) 332 #define RCC_PLLNCFGR2_DIVR_SHIFT 16 333 #define RCC_PLLNCFGR2_DIVR_MASK GENMASK_32(22, 16) 334 335 /* Used for all RCC_PLL<n>FRACR registers */ 336 #define RCC_PLLNFRACR_FRACV_SHIFT 3 337 #define RCC_PLLNFRACR_FRACV_MASK GENMASK_32(15, 3) 338 #define RCC_PLLNFRACR_FRACLE BIT(16) 339 340 /* Used for all RCC_PLL<n>CSGR registers */ 341 #define RCC_PLLNCSGR_INC_STEP_SHIFT 16 342 #define RCC_PLLNCSGR_INC_STEP_MASK GENMASK_32(30, 16) 343 #define RCC_PLLNCSGR_MOD_PER_SHIFT 0 344 #define RCC_PLLNCSGR_MOD_PER_MASK GENMASK_32(12, 0) 345 #define RCC_PLLNCSGR_SSCG_MODE_SHIFT 15 346 #define RCC_PLLNCSGR_SSCG_MODE_MASK BIT(15) 347 348 /* Used for RCC_OCENSETR and RCC_OCENCLRR registers */ 349 #define RCC_OCENR_HSION BIT(0) 350 #define RCC_OCENR_HSIKERON BIT(1) 351 #define RCC_OCENR_CSION BIT(4) 352 #define RCC_OCENR_CSIKERON BIT(5) 353 #define RCC_OCENR_DIGBYP BIT(7) 354 #define RCC_OCENR_HSEON BIT(8) 355 #define RCC_OCENR_HSEKERON BIT(9) 356 #define RCC_OCENR_HSEBYP BIT(10) 357 #define RCC_OCENR_HSECSSON BIT(11) 358 359 /* Fields of RCC_OCRDYR register */ 360 #define RCC_OCRDYR_HSIRDY BIT(0) 361 #define RCC_OCRDYR_HSIDIVRDY BIT(2) 362 #define RCC_OCRDYR_CSIRDY BIT(4) 363 #define RCC_OCRDYR_HSERDY BIT(8) 364 365 /* Fields of RCC_DDRITFCR register */ 366 #define RCC_DDRITFCR_DDRC1EN BIT(0) 367 #define RCC_DDRITFCR_DDRC1LPEN BIT(1) 368 #define RCC_DDRITFCR_DDRC2EN BIT(2) 369 #define RCC_DDRITFCR_DDRC2LPEN BIT(3) 370 #define RCC_DDRITFCR_DDRPHYCEN BIT(4) 371 #define RCC_DDRITFCR_DDRPHYCLPEN BIT(5) 372 #define RCC_DDRITFCR_DDRCAPBEN BIT(6) 373 #define RCC_DDRITFCR_DDRCAPBLPEN BIT(7) 374 #define RCC_DDRITFCR_AXIDCGEN BIT(8) 375 #define RCC_DDRITFCR_DDRPHYCAPBEN BIT(9) 376 #define RCC_DDRITFCR_DDRPHYCAPBLPEN BIT(10) 377 #define RCC_DDRITFCR_DDRCAPBRST BIT(14) 378 #define RCC_DDRITFCR_DDRCAXIRST BIT(15) 379 #define RCC_DDRITFCR_DDRCORERST BIT(16) 380 #define RCC_DDRITFCR_DPHYAPBRST BIT(17) 381 #define RCC_DDRITFCR_DPHYRST BIT(18) 382 #define RCC_DDRITFCR_DPHYCTLRST BIT(19) 383 #define RCC_DDRITFCR_DDRCKMOD_MASK GENMASK_32(22, 20) 384 #define RCC_DDRITFCR_DDRCKMOD_SHIFT 20 385 #define RCC_DDRITFCR_DDRCKMOD_SSR 0 386 #define RCC_DDRITFCR_DDRCKMOD_ASR1 BIT(20) 387 #define RCC_DDRITFCR_DDRCKMOD_HSR1 BIT(21) 388 #define RCC_DDRITFCR_GSKPCTRL BIT(24) 389 390 /* Fields of RCC_HSICFGR register */ 391 #define RCC_HSICFGR_HSIDIV_MASK GENMASK_32(1, 0) 392 #define RCC_HSICFGR_HSITRIM_SHIFT 8 393 #define RCC_HSICFGR_HSITRIM_MASK GENMASK_32(14, 8) 394 #define RCC_HSICFGR_HSICAL_SHIFT 16 395 #define RCC_HSICFGR_HSICAL_MASK GENMASK_32(27, 16) 396 397 /* Fields of RCC_CSICFGR register */ 398 #define RCC_CSICFGR_CSITRIM_SHIFT 8 399 #define RCC_CSICFGR_CSITRIM_MASK GENMASK_32(12, 8) 400 #define RCC_CSICFGR_CSICAL_SHIFT 16 401 #define RCC_CSICFGR_CSICAL_MASK GENMASK_32(23, 16) 402 403 /* Used for RCC_MCO related operations */ 404 #define RCC_MCOCFG_MCOON BIT(12) 405 #define RCC_MCOCFG_MCODIV_MASK GENMASK_32(7, 4) 406 #define RCC_MCOCFG_MCODIV_SHIFT 4 407 #define RCC_MCOCFG_MCOSRC_MASK GENMASK_32(2, 0) 408 409 /* Fields of RCC_DBGCFGR register */ 410 #define RCC_DBGCFGR_DBGCKEN BIT(8) 411 412 /* RCC register fields for reset reasons */ 413 #define RCC_MP_RSTSCLRR_PORRSTF BIT(0) 414 #define RCC_MP_RSTSCLRR_BORRSTF BIT(1) 415 #define RCC_MP_RSTSCLRR_PADRSTF BIT(2) 416 #define RCC_MP_RSTSCLRR_HCSSRSTF BIT(3) 417 #define RCC_MP_RSTSCLRR_VCORERSTF BIT(4) 418 #define RCC_MP_RSTSCLRR_MPSYSRSTF BIT(6) 419 #define RCC_MP_RSTSCLRR_MCSYSRSTF BIT(7) 420 #define RCC_MP_RSTSCLRR_IWDG1RSTF BIT(8) 421 #define RCC_MP_RSTSCLRR_IWDG2RSTF BIT(9) 422 #define RCC_MP_RSTSCLRR_STDBYRSTF BIT(11) 423 #define RCC_MP_RSTSCLRR_CSTDBYRSTF BIT(12) 424 425 /* Global Reset Register */ 426 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0) 427 #define RCC_MP_GRSTCSETR_MCURST BIT(1) 428 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4) 429 #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5) 430 431 /* Clock Source Interrupt Flag Register */ 432 #define RCC_MP_CIFR_LSIRDYF BIT(0) 433 #define RCC_MP_CIFR_LSERDYF BIT(1) 434 #define RCC_MP_CIFR_HSIRDYF BIT(2) 435 #define RCC_MP_CIFR_HSERDYF BIT(3) 436 #define RCC_MP_CIFR_CSIRDYF BIT(4) 437 #define RCC_MP_CIFR_PLL1DYF BIT(8) 438 #define RCC_MP_CIFR_PLL2DYF BIT(9) 439 #define RCC_MP_CIFR_PLL3DYF BIT(10) 440 #define RCC_MP_CIFR_PLL4DYF BIT(11) 441 #define RCC_MP_CIFR_LSECSSF BIT(16) 442 #define RCC_MP_CIFR_WKUPF BIT(20) 443 #define RCC_MP_CIFR_MASK (RCC_MP_CIFR_LSIRDYF | RCC_MP_CIFR_LSERDYF | \ 444 RCC_MP_CIFR_HSIRDYF | RCC_MP_CIFR_HSERDYF | \ 445 RCC_MP_CIFR_CSIRDYF | RCC_MP_CIFR_PLL1DYF | \ 446 RCC_MP_CIFR_PLL2DYF | RCC_MP_CIFR_PLL3DYF | \ 447 RCC_MP_CIFR_PLL4DYF | RCC_MP_CIFR_LSECSSF | \ 448 RCC_MP_CIFR_WKUPF) 449 450 /* Stop Request Set Register */ 451 #define RCC_MP_SREQSETR_STPREQ_P0 BIT(0) 452 #define RCC_MP_SREQSETR_STPREQ_P1 BIT(1) 453 454 /* Stop Request Clear Register */ 455 #define RCC_MP_SREQCLRR_STPREQ_P0 BIT(0) 456 #define RCC_MP_SREQCLRR_STPREQ_P1 BIT(1) 457 458 /* Global Control Register */ 459 #define RCC_MP_GCR_BOOT_MCU BIT(0) 460 461 /* RCC_MP_APB5RST(SET|CLR)R bit fields */ 462 #define RCC_APB5RSTSETR_SPI6RST BIT(0) 463 #define RCC_APB5RSTSETR_I2C4RST BIT(2) 464 #define RCC_APB5RSTSETR_I2C6RST BIT(3) 465 #define RCC_APB5RSTSETR_USART1RST BIT(4) 466 #define RCC_APB5RSTSETR_STGENRST BIT(20) 467 468 /* RCC_MP_APB5EN(SET|CLR)R bit fields */ 469 #define RCC_MP_APB5ENSETR_SPI6EN_POS 0 470 #define RCC_MP_APB5ENSETR_I2C4EN_POS 2 471 #define RCC_MP_APB5ENSETR_I2C6EN_POS 3 472 #define RCC_MP_APB5ENSETR_USART1EN_POS 4 473 #define RCC_MP_APB5ENSETR_RTCAPBEN_POS 8 474 #define RCC_MP_APB5ENSETR_TZC1EN_POS 11 475 #define RCC_MP_APB5ENSETR_TZC2EN_POS 12 476 #define RCC_MP_APB5ENSETR_TZPCEN_POS 13 477 #define RCC_MP_APB5ENSETR_IWDG1APBEN_POS 15 478 #define RCC_MP_APB5ENSETR_BSECEN_POS 16 479 #define RCC_MP_APB5ENSETR_STGENEN_POS 20 480 481 #define RCC_MP_APB5ENSETR_SPI6EN BIT(RCC_MP_APB5ENSETR_SPI6EN_POS) 482 #define RCC_MP_APB5ENSETR_I2C4EN BIT(RCC_MP_APB5ENSETR_I2C4EN_POS) 483 #define RCC_MP_APB5ENSETR_I2C6EN BIT(RCC_MP_APB5ENSETR_I2C6EN_POS) 484 #define RCC_MP_APB5ENSETR_USART1EN BIT(RCC_MP_APB5ENSETR_USART1EN_POS) 485 #define RCC_MP_APB5ENSETR_RTCAPBEN BIT(RCC_MP_APB5ENSETR_RTCAPBEN_POS) 486 #define RCC_MP_APB5ENSETR_TZC1EN BIT(RCC_MP_APB5ENSETR_TZC1EN_POS) 487 #define RCC_MP_APB5ENSETR_TZC2EN BIT(RCC_MP_APB5ENSETR_TZC2EN_POS) 488 #define RCC_MP_APB5ENSETR_TZPCEN BIT(RCC_MP_APB5ENSETR_TZPCEN_POS) 489 #define RCC_MP_APB5ENSETR_IWDG1APBEN BIT(RCC_MP_APB5ENSETR_IWDG1APBEN_POS) 490 #define RCC_MP_APB5ENSETR_BSECEN BIT(RCC_MP_APB5ENSETR_BSECEN_POS) 491 #define RCC_MP_APB5ENSETR_STGENEN BIT(RCC_MP_APB5ENSETR_STGENEN_POS) 492 493 /* RCC_MP_APB5LPEN(SET|CLR)R bit fields */ 494 #define RCC_MP_APB5LPENSETR_SPI6LPEN BIT(0) 495 #define RCC_MP_APB5LPENSETR_I2C4LPEN BIT(2) 496 #define RCC_MP_APB5LPENSETR_I2C6LPEN BIT(3) 497 #define RCC_MP_APB5LPENSETR_USART1LPEN BIT(4) 498 #define RCC_MP_APB5LPENSETR_RTCAPBLPEN BIT(8) 499 #define RCC_MP_APB5LPENSETR_TZC1LPEN BIT(11) 500 #define RCC_MP_APB5LPENSETR_TZC2LPEN BIT(12) 501 #define RCC_MP_APB5LPENSETR_TZPCLPEN BIT(13) 502 #define RCC_MP_APB5LPENSETR_IWDG1APBLPEN BIT(15) 503 #define RCC_MP_APB5LPENSETR_BSECLPEN BIT(16) 504 #define RCC_MP_APB5LPENSETR_STGENLPEN BIT(20) 505 #define RCC_MP_APB5LPENSETR_STGENSTPEN BIT(21) 506 507 /* RCC_MP_AHB5RST(SET|CLR)R bit fields */ 508 #define RCC_AHB5RSTSETR_GPIOZRST BIT(0) 509 #define RCC_AHB5RSTSETR_CRYP1RST BIT(4) 510 #define RCC_AHB5RSTSETR_HASH1RST BIT(5) 511 #define RCC_AHB5RSTSETR_RNG1RST BIT(6) 512 #define RCC_AHB5RSTSETR_AXIMCRST BIT(16) 513 514 /* RCC_MP_AHB5EN(SET|CLR)R bit fields */ 515 #define RCC_MP_AHB5ENSETR_GPIOZEN_POS 0 516 #define RCC_MP_AHB5ENSETR_CRYP1EN_POS 4 517 #define RCC_MP_AHB5ENSETR_HASH1EN_POS 5 518 #define RCC_MP_AHB5ENSETR_RNG1EN_POS 6 519 #define RCC_MP_AHB5ENSETR_BKPSRAMEN_POS 8 520 #define RCC_MP_AHB5ENSETR_AXIMCEN_POS 16 521 522 #define RCC_MP_AHB5ENSETR_GPIOZEN BIT(RCC_MP_AHB5ENSETR_GPIOZEN_POS) 523 #define RCC_MP_AHB5ENSETR_CRYP1EN BIT(RCC_MP_AHB5ENSETR_CRYP1EN_POS) 524 #define RCC_MP_AHB5ENSETR_HASH1EN BIT(RCC_MP_AHB5ENSETR_HASH1EN_POS) 525 #define RCC_MP_AHB5ENSETR_RNG1EN BIT(RCC_MP_AHB5ENSETR_RNG1EN_POS) 526 #define RCC_MP_AHB5ENSETR_BKPSRAMEN BIT(RCC_MP_AHB5ENSETR_BKPSRAMEN_POS) 527 #define RCC_MP_AHB5ENSETR_AXIMCEN BIT(RCC_MP_AHB5ENSETR_AXIMCEN_POS) 528 529 /* RCC_MP_AHB5LPEN(SET|CLR)R bit fields */ 530 #define RCC_MP_AHB5LPENSETR_GPIOZLPEN BIT(0) 531 #define RCC_MP_AHB5LPENSETR_CRYP1LPEN BIT(4) 532 #define RCC_MP_AHB5LPENSETR_HASH1LPEN BIT(5) 533 #define RCC_MP_AHB5LPENSETR_RNG1LPEN BIT(6) 534 #define RCC_MP_AHB5LPENSETR_BKPSRAMLPEN BIT(8) 535 536 /* RCC_MP_TZAHB6EN(SET|CLR)R bit fields */ 537 #define RCC_MP_TZAHB6ENSETR_MDMA_POS 0 538 #define RCC_MP_TZAHB6ENSETR_MDMA BIT(RCC_MP_TZAHB6ENSETR_MDMA_POS) 539 540 /* RCC_MP_IWDGFZ(SET|CLR)R bit fields */ 541 #define RCC_MP_IWDGFZSETR_IWDG1 BIT(0) 542 #define RCC_MP_IWDGFZSETR_IWDG2 BIT(1) 543 544 #define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc" 545 #define DT_RCC_SECURE_CLK_COMPAT "st,stm32mp1-rcc-secure" 546 547 #ifndef __ASSEMBLER__ 548 vaddr_t stm32_rcc_base(void); 549 550 static inline bool stm32_rcc_is_secure(void) 551 { 552 return io_read32(stm32_rcc_base() + RCC_TZCR) & RCC_TZCR_TZEN; 553 } 554 555 static inline bool stm32_rcc_is_mckprot(void) 556 { 557 return io_read32(stm32_rcc_base() + RCC_TZCR) & RCC_TZCR_MCKPROT; 558 } 559 #endif /*__ASSEMBLER__*/ 560 561 #endif /*__DRIVERS_STM32MP1_RCC_H__*/ 562