1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/stm32_gpio.h> 10 #include <kernel/dt.h> 11 #include <mm/core_memprot.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <util.h> 15 #include <types_ext.h> 16 17 /* 18 * I2C specification values as per version 6.0, 4th of April 2014 [1], 19 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 20 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 21 * 22 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 23 */ 24 #define I2C_STANDARD_RATE U(100000) 25 #define I2C_FAST_RATE U(400000) 26 #define I2C_FAST_PLUS_RATE U(1000000) 27 28 /* 29 * Initialization configuration structure for the STM32 I2C bus. 30 * Refer to the SoC Reference Manual for more details on configuration items. 31 * 32 * @dt_status: non-secure/secure status read from DT 33 * @pbase: I2C interface base address 34 * @reg_size: I2C interface register map size 35 * @clock: I2C bus/interface clock 36 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 37 * @own_address1: 7-bit or 10-bit first device own address. 38 * @dual_address_mode: True if enabling Dual-Addressing mode 39 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 40 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 41 * @general_call_mode: True if enbling General-Call mode 42 * @no_stretch_mode: If enabling the No-Stretch mode 43 * @rise_time: SCL clock pin rising time in nanoseconds 44 * @fall_time: SCL clock pin falling time in nanoseconds 45 * @bus_rate: Specifies the I2C clock frequency in Hertz 46 * @analog_filter: True if enabling analog filter 47 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 48 */ 49 struct stm32_i2c_init_s { 50 unsigned int dt_status; 51 paddr_t pbase; 52 size_t reg_size; 53 unsigned int clock; 54 bool addr_mode_10b_not_7b; 55 uint32_t own_address1; 56 bool dual_address_mode; 57 uint32_t own_address2; 58 uint32_t own_address2_masks; 59 bool general_call_mode; 60 bool no_stretch_mode; 61 uint32_t rise_time; 62 uint32_t fall_time; 63 uint32_t bus_rate; 64 bool analog_filter; 65 uint8_t digital_filter_coef; 66 }; 67 68 enum i2c_state_e { 69 I2C_STATE_RESET, /* Not yet initialized */ 70 I2C_STATE_READY, /* Ready for use */ 71 I2C_STATE_BUSY, /* Internal process ongoing */ 72 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 73 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 74 I2C_STATE_SUSPENDED, /* Bus is supended */ 75 }; 76 77 enum i2c_mode_e { 78 I2C_MODE_NONE, /* No active communication */ 79 I2C_MODE_MASTER, /* Communication in Master Mode */ 80 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 81 I2C_MODE_MEM, /* Communication in Memory Mode */ 82 }; 83 84 #define I2C_ERROR_NONE U(0x0) 85 #define I2C_ERROR_BERR BIT(0) 86 #define I2C_ERROR_ARLO BIT(1) 87 #define I2C_ERROR_ACKF BIT(2) 88 #define I2C_ERROR_OVR BIT(3) 89 #define I2C_ERROR_DMA BIT(4) 90 #define I2C_ERROR_TIMEOUT BIT(5) 91 #define I2C_ERROR_SIZE BIT(6) 92 93 /* I2C interface registers state */ 94 struct i2c_cfg { 95 uint32_t timingr; 96 uint32_t oar1; 97 uint32_t oar2; 98 uint32_t cr1; 99 uint32_t cr2; 100 }; 101 102 /* 103 * I2C bus device 104 * @base: I2C SoC registers base address 105 * @reg_size: I2C SoC registers address map size 106 * @dt_status: non-secure/secure status read from DT 107 * @clock: clock ID 108 * @i2c_state: Driver state ID I2C_STATE_* 109 * @i2c_err: Last error code I2C_ERROR_* 110 * @saved_timing: Saved timing value if already computed 111 * @saved_frequency: Saved frequency value if already computed 112 * @sec_cfg: I2C registers configuration storage 113 * @pinctrl: PINCTRLs configuration for the I2C PINs 114 * @pinctrl_count: Number of PINCTRLs elements 115 */ 116 struct i2c_handle_s { 117 struct io_pa_va base; 118 size_t reg_size; 119 unsigned int dt_status; 120 unsigned long clock; 121 enum i2c_state_e i2c_state; 122 uint32_t i2c_err; 123 uint32_t saved_timing; 124 unsigned long saved_frequency; 125 struct i2c_cfg sec_cfg; 126 struct stm32_pinctrl *pinctrl; 127 size_t pinctrl_count; 128 }; 129 130 /* STM32 specific defines */ 131 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 132 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 133 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 134 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 135 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 136 137 /* 138 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 139 * 140 * @fdt: Reference to DT 141 * @node: Target I2C node in the DT 142 * @init: Output stm32_i2c_init_s structure 143 * @pinctrl: Reference to output pinctrl array 144 * @pinctrl_count: Input @pinctrl array size, output expected size 145 * Return 0 on success else a negative value 146 */ 147 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 148 struct stm32_i2c_init_s *init, 149 struct stm32_pinctrl **pinctrl, 150 size_t *pinctrl_count); 151 152 /* 153 * Initialize I2C bus handle from input configuration directives 154 * 155 * @hi2c: Reference to I2C bus handle structure 156 * @init_data: Input stm32_i2c_init_s structure 157 * Return 0 on success else a negative value 158 */ 159 int stm32_i2c_init(struct i2c_handle_s *hi2c, 160 struct stm32_i2c_init_s *init_data); 161 162 /* 163 * Send a memory write request in the I2C bus 164 * 165 * @hi2c: Reference to I2C bus handle structure 166 * @dev_addr: Target device I2C address 167 * @mem_addr: Target device memory address 168 * @mem_addr_size: Byte size of internal memory address 169 * @p_data: Data to be written 170 * @size: Byte size of the data to be written 171 * @timeout_ms: Timeout value in milliseconds 172 * Return 0 on success else a negative value 173 */ 174 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 175 uint32_t mem_addr, uint32_t mem_addr_size, 176 uint8_t *p_data, size_t size, unsigned int timeout_ms); 177 178 /* 179 * Send a memory read request in the I2C bus 180 * 181 * @hi2c: Reference to I2C bus handle structure 182 * @dev_addr: Target device I2C address 183 * @mem_addr: Target device memory address 184 * @mem_addr_size: Byte size of internal memory address 185 * @p_data: Data to be read 186 * @size: Byte size of the data to be read 187 * @timeout_ms: Timeout value in milliseconds 188 * Return 0 on success else a negative value 189 */ 190 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 191 uint32_t mem_addr, uint32_t mem_addr_size, 192 uint8_t *p_data, size_t size, unsigned int timeout_ms); 193 194 /* 195 * Send a data buffer in master mode on the I2C bus 196 * 197 * @hi2c: Reference to I2C bus handle structure 198 * @dev_addr: Target device I2C address 199 * @p_data: Data to be sent 200 * @size: Byte size of the data to be sent 201 * @timeout_ms: Timeout value in milliseconds 202 * Return 0 on success else a negative value 203 */ 204 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 205 uint8_t *p_data, size_t size, 206 unsigned int timeout_ms); 207 208 /* 209 * Receive a data buffer in master mode on the I2C bus 210 * 211 * @hi2c: Reference to I2C bus handle structure 212 * @dev_addr: Target device I2C address 213 * @p_data: Buffer for the received data 214 * @size: Byte size of the data to be received 215 * @timeout_ms: Timeout value in milliseconds 216 * Return 0 on success else a negative value 217 */ 218 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 219 uint8_t *p_data, size_t size, 220 unsigned int timeout_ms); 221 222 /* 223 * Optimized 1 byte read/write function for unpaged sequences. 224 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 225 * Return 0 on success else a negative value 226 */ 227 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 228 unsigned int mem_addr, uint8_t *p_data, 229 bool write); 230 231 /* 232 * Check link with the I2C device 233 * 234 * @hi2c: Reference to I2C bus handle structure 235 * @dev_addr: Target device I2C address 236 * @trials: Number of attempts of I2C request 237 * @timeout_ms: Timeout value in milliseconds for each I2C request 238 * Return 0 on success else a negative value 239 */ 240 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 241 unsigned int trials, unsigned int timeout_ms); 242 243 /* 244 * Suspend I2C bus. 245 * Bus owner is reponsible for calling stm32_i2c_suspend(). 246 * 247 * @hi2c: Reference to I2C bus handle structure 248 */ 249 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 250 251 /* 252 * Resume I2C bus. 253 * Bus owner is reponsible for calling stm32_i2c_resume(). 254 * 255 * @hi2c: Reference to I2C bus handle structure 256 */ 257 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 258 259 /* 260 * Return true if I2C bus is enabled for secure world only, false otherwise 261 */ 262 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 263 { 264 return hi2c->dt_status == DT_STATUS_OK_SEC; 265 } 266 267 #endif /* __STM32_I2C_H */ 268