1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/stm32_gpio.h> 10 #include <kernel/dt.h> 11 #include <mm/core_memprot.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <util.h> 15 #include <types_ext.h> 16 17 /* 18 * I2C specification values as per version 6.0, 4th of April 2014 [1], 19 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 20 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 21 * 22 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 23 */ 24 enum i2c_speed_e { 25 I2C_SPEED_STANDARD, /* 100 kHz */ 26 I2C_SPEED_FAST, /* 400 kHz */ 27 I2C_SPEED_FAST_PLUS, /* 1 MHz */ 28 }; 29 30 #define I2C_STANDARD_RATE 100000 31 #define I2C_FAST_RATE 400000 32 #define I2C_FAST_PLUS_RATE 1000000 33 34 /* 35 * Initialization configuration structure for the STM32 I2C bus. 36 * Refer to the SoC Reference Manual for more details on configuration items. 37 * 38 * @dt_status: non-secure/secure status read from DT 39 * @pbase: I2C interface base address 40 * @clock: I2C bus/interface clock 41 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 42 * @own_address1: 7-bit or 10-bit first device own address. 43 * @dual_address_mode: True if enabling Dual-Addressing mode 44 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 45 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 46 * @general_call_mode: True if enbling General-Call mode 47 * @no_stretch_mode: If enabling the No-Stretch mode 48 * @rise_time: SCL clock pin rising time in nanoseconds 49 * @fall_time: SCL clock pin falling time in nanoseconds 50 * @speed_mode: I2C clock source frequency mode 51 * @analog_filter: True if enabling analog filter 52 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 53 */ 54 struct stm32_i2c_init_s { 55 unsigned int dt_status; 56 paddr_t pbase; 57 unsigned int clock; 58 bool addr_mode_10b_not_7b; 59 uint32_t own_address1; 60 bool dual_address_mode; 61 uint32_t own_address2; 62 uint32_t own_address2_masks; 63 bool general_call_mode; 64 bool no_stretch_mode; 65 uint32_t rise_time; 66 uint32_t fall_time; 67 enum i2c_speed_e speed_mode; 68 bool analog_filter; 69 uint8_t digital_filter_coef; 70 }; 71 72 enum i2c_state_e { 73 I2C_STATE_RESET, /* Not yet initialized */ 74 I2C_STATE_READY, /* Ready for use */ 75 I2C_STATE_BUSY, /* Internal process ongoing */ 76 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 77 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 78 I2C_STATE_SUSPENDED, /* Bus is supended */ 79 }; 80 81 enum i2c_mode_e { 82 I2C_MODE_NONE, /* No active communication */ 83 I2C_MODE_MASTER, /* Communication in Master Mode */ 84 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 85 I2C_MODE_MEM, /* Communication in Memory Mode */ 86 }; 87 88 #define I2C_ERROR_NONE 0x0 89 #define I2C_ERROR_BERR BIT(0) 90 #define I2C_ERROR_ARLO BIT(1) 91 #define I2C_ERROR_ACKF BIT(2) 92 #define I2C_ERROR_OVR BIT(3) 93 #define I2C_ERROR_DMA BIT(4) 94 #define I2C_ERROR_TIMEOUT BIT(5) 95 #define I2C_ERROR_SIZE BIT(6) 96 97 /* I2C interface registers state */ 98 struct i2c_cfg { 99 uint32_t timingr; 100 uint32_t oar1; 101 uint32_t oar2; 102 uint32_t cr1; 103 uint32_t cr2; 104 }; 105 106 /* 107 * I2C bus device 108 * @base: I2C SoC registers base address 109 * @dt_status: non-secure/secure status read from DT 110 * @clock: clock ID 111 * @i2c_state: Driver state ID I2C_STATE_* 112 * @i2c_err: Last error code I2C_ERROR_* 113 * @sec_cfg: I2C regsiters configuration storage 114 * @pinctrl: PINCTRLs configuration for the I2C PINs 115 * @pinctrl_count: Number of PINCTRLs elements 116 */ 117 struct i2c_handle_s { 118 struct io_pa_va base; 119 unsigned int dt_status; 120 unsigned long clock; 121 enum i2c_state_e i2c_state; 122 uint32_t i2c_err; 123 struct i2c_cfg sec_cfg; 124 struct stm32_pinctrl *pinctrl; 125 size_t pinctrl_count; 126 }; 127 128 /* STM32 specific defines */ 129 #define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD 130 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 131 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 132 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 133 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 134 #define STM32_I2C_DIGITAL_FILTER_MAX 16 135 136 /* 137 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 138 * 139 * @fdt: Reference to DT 140 * @node: Target I2C node in the DT 141 * @init: Output stm32_i2c_init_s structure 142 * @pinctrl: Reference to output pinctrl array 143 * @pinctrl_count: Input @pinctrl array size, output expected size 144 * Return 0 on success else a negative value 145 */ 146 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 147 struct stm32_i2c_init_s *init, 148 struct stm32_pinctrl **pinctrl, 149 size_t *pinctrl_count); 150 151 /* 152 * Initialize I2C bus handle from input configuration directives 153 * 154 * @hi2c: Reference to I2C bus handle structure 155 * @init_data: Input stm32_i2c_init_s structure 156 * Return 0 on success else a negative value 157 */ 158 int stm32_i2c_init(struct i2c_handle_s *hi2c, 159 struct stm32_i2c_init_s *init_data); 160 161 /* 162 * Send a memory write request in the I2C bus 163 * 164 * @hi2c: Reference to I2C bus handle structure 165 * @dev_addr: Target device I2C address 166 * @mem_addr: Target device memory address 167 * @mem_addr_size: Byte size of internal memory address 168 * @p_data: Data to be written 169 * @size: Byte size of the data to be written 170 * @timeout_ms: Timeout value in milliseconds 171 * Return 0 on success else a negative value 172 */ 173 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 174 uint32_t mem_addr, uint32_t mem_addr_size, 175 uint8_t *p_data, size_t size, unsigned int timeout_ms); 176 177 /* 178 * Send a memory read request in the I2C bus 179 * 180 * @hi2c: Reference to I2C bus handle structure 181 * @dev_addr: Target device I2C address 182 * @mem_addr: Target device memory address 183 * @mem_addr_size: Byte size of internal memory address 184 * @p_data: Data to be read 185 * @size: Byte size of the data to be read 186 * @timeout_ms: Timeout value in milliseconds 187 * Return 0 on success else a negative value 188 */ 189 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 190 uint32_t mem_addr, uint32_t mem_addr_size, 191 uint8_t *p_data, size_t size, unsigned int timeout_ms); 192 193 /* 194 * Send a data buffer in master mode on the I2C bus 195 * 196 * @hi2c: Reference to I2C bus handle structure 197 * @dev_addr: Target device I2C address 198 * @p_data: Data to be sent 199 * @size: Byte size of the data to be sent 200 * @timeout_ms: Timeout value in milliseconds 201 * Return 0 on success else a negative value 202 */ 203 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 204 uint8_t *p_data, size_t size, 205 unsigned int timeout_ms); 206 207 /* 208 * Receive a data buffer in master mode on the I2C bus 209 * 210 * @hi2c: Reference to I2C bus handle structure 211 * @dev_addr: Target device I2C address 212 * @p_data: Buffer for the received data 213 * @size: Byte size of the data to be received 214 * @timeout_ms: Timeout value in milliseconds 215 * Return 0 on success else a negative value 216 */ 217 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 218 uint8_t *p_data, size_t size, 219 unsigned int timeout_ms); 220 221 /* 222 * Optimized 1 byte read/write function for unpaged sequences. 223 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 224 * Return 0 on success else a negative value 225 */ 226 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 227 unsigned int mem_addr, uint8_t *p_data, 228 bool write); 229 230 /* 231 * Check link with the I2C device 232 * 233 * @hi2c: Reference to I2C bus handle structure 234 * @dev_addr: Target device I2C address 235 * @trials: Number of attempts of I2C request 236 * @timeout_ms: Timeout value in milliseconds for each I2C request 237 * Return 0 on success else a negative value 238 */ 239 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 240 unsigned int trials, unsigned int timeout_ms); 241 242 /* 243 * Suspend I2C bus. 244 * Bus owner is reponsible for calling stm32_i2c_suspend(). 245 * 246 * @hi2c: Reference to I2C bus handle structure 247 */ 248 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 249 250 /* 251 * Resume I2C bus. 252 * Bus owner is reponsible for calling stm32_i2c_resume(). 253 * 254 * @hi2c: Reference to I2C bus handle structure 255 */ 256 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 257 258 /* 259 * Return true if I2C bus is enabled for secure world only, false otherwise 260 */ 261 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 262 { 263 return hi2c->dt_status == DT_STATUS_OK_SEC; 264 } 265 266 #endif /* __STM32_I2C_H */ 267