1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/clk.h> 10 #include <drivers/stm32_gpio.h> 11 #include <kernel/dt.h> 12 #include <mm/core_memprot.h> 13 #include <stdbool.h> 14 #include <stdint.h> 15 #include <util.h> 16 #include <types_ext.h> 17 18 /* 19 * I2C specification values as per version 6.0, 4th of April 2014 [1], 20 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 21 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 22 * 23 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 24 */ 25 #define I2C_STANDARD_RATE U(100000) 26 #define I2C_FAST_RATE U(400000) 27 #define I2C_FAST_PLUS_RATE U(1000000) 28 29 /* 30 * Initialization configuration structure for the STM32 I2C bus. 31 * Refer to the SoC Reference Manual for more details on configuration items. 32 * 33 * @dt_status: non-secure/secure status read from DT 34 * @pbase: I2C interface base address 35 * @reg_size: I2C interface register map size 36 * @clock: I2C bus/interface clock 37 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 38 * @own_address1: 7-bit or 10-bit first device own address. 39 * @dual_address_mode: True if enabling Dual-Addressing mode 40 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 41 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 42 * @general_call_mode: True if enbling General-Call mode 43 * @no_stretch_mode: If enabling the No-Stretch mode 44 * @rise_time: SCL clock pin rising time in nanoseconds 45 * @fall_time: SCL clock pin falling time in nanoseconds 46 * @bus_rate: Specifies the I2C clock frequency in Hertz 47 * @analog_filter: True if enabling analog filter 48 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 49 */ 50 struct stm32_i2c_init_s { 51 unsigned int dt_status; 52 paddr_t pbase; 53 size_t reg_size; 54 struct clk *clock; 55 bool addr_mode_10b_not_7b; 56 uint32_t own_address1; 57 bool dual_address_mode; 58 uint32_t own_address2; 59 uint32_t own_address2_masks; 60 bool general_call_mode; 61 bool no_stretch_mode; 62 uint32_t rise_time; 63 uint32_t fall_time; 64 uint32_t bus_rate; 65 bool analog_filter; 66 uint8_t digital_filter_coef; 67 }; 68 69 enum i2c_state_e { 70 I2C_STATE_RESET, /* Not yet initialized */ 71 I2C_STATE_READY, /* Ready for use */ 72 I2C_STATE_BUSY, /* Internal process ongoing */ 73 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 74 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 75 I2C_STATE_SUSPENDED, /* Bus is supended */ 76 }; 77 78 enum i2c_mode_e { 79 I2C_MODE_NONE, /* No active communication */ 80 I2C_MODE_MASTER, /* Communication in Master Mode */ 81 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 82 I2C_MODE_MEM, /* Communication in Memory Mode */ 83 }; 84 85 #define I2C_ERROR_NONE U(0x0) 86 #define I2C_ERROR_BERR BIT(0) 87 #define I2C_ERROR_ARLO BIT(1) 88 #define I2C_ERROR_ACKF BIT(2) 89 #define I2C_ERROR_OVR BIT(3) 90 #define I2C_ERROR_DMA BIT(4) 91 #define I2C_ERROR_TIMEOUT BIT(5) 92 #define I2C_ERROR_SIZE BIT(6) 93 94 /* I2C interface registers state */ 95 struct i2c_cfg { 96 uint32_t timingr; 97 uint32_t oar1; 98 uint32_t oar2; 99 uint32_t cr1; 100 uint32_t cr2; 101 }; 102 103 /* 104 * I2C bus device 105 * @base: I2C SoC registers base address 106 * @reg_size: I2C SoC registers address map size 107 * @dt_status: non-secure/secure status read from DT 108 * @clock: clock ID 109 * @i2c_state: Driver state ID I2C_STATE_* 110 * @i2c_err: Last error code I2C_ERROR_* 111 * @saved_timing: Saved timing value if already computed 112 * @saved_frequency: Saved frequency value if already computed 113 * @sec_cfg: I2C registers configuration storage 114 * @pinctrl: PINCTRLs configuration for the I2C PINs 115 * @pinctrl_count: Number of PINCTRLs elements 116 */ 117 struct i2c_handle_s { 118 struct io_pa_va base; 119 size_t reg_size; 120 unsigned int dt_status; 121 struct clk *clock; 122 enum i2c_state_e i2c_state; 123 uint32_t i2c_err; 124 uint32_t saved_timing; 125 unsigned long saved_frequency; 126 struct i2c_cfg sec_cfg; 127 struct stm32_pinctrl *pinctrl; 128 size_t pinctrl_count; 129 }; 130 131 /* STM32 specific defines */ 132 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 133 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 134 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 135 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 136 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 137 138 /* 139 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 140 * 141 * @fdt: Reference to DT 142 * @node: Target I2C node in the DT 143 * @init: Output stm32_i2c_init_s structure 144 * @pinctrl: Reference to output pinctrl array 145 * @pinctrl_count: Input @pinctrl array size, output expected size upon success 146 * Return a TEE_Result compliant value 147 */ 148 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 149 struct stm32_i2c_init_s *init, 150 struct stm32_pinctrl **pinctrl, 151 size_t *pinctrl_count); 152 153 /* 154 * Initialize I2C bus handle from input configuration directives 155 * 156 * @hi2c: Reference to I2C bus handle structure 157 * @init_data: Input stm32_i2c_init_s structure 158 * Return 0 on success else a negative value 159 */ 160 int stm32_i2c_init(struct i2c_handle_s *hi2c, 161 struct stm32_i2c_init_s *init_data); 162 163 /* 164 * Send a memory write request in the I2C bus 165 * 166 * @hi2c: Reference to I2C bus handle structure 167 * @dev_addr: Target device I2C address 168 * @mem_addr: Target device memory address 169 * @mem_addr_size: Byte size of internal memory address 170 * @p_data: Data to be written 171 * @size: Byte size of the data to be written 172 * @timeout_ms: Timeout value in milliseconds 173 * Return 0 on success else a negative value 174 */ 175 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 176 uint32_t mem_addr, uint32_t mem_addr_size, 177 uint8_t *p_data, size_t size, unsigned int timeout_ms); 178 179 /* 180 * Send a memory read request in the I2C bus 181 * 182 * @hi2c: Reference to I2C bus handle structure 183 * @dev_addr: Target device I2C address 184 * @mem_addr: Target device memory address 185 * @mem_addr_size: Byte size of internal memory address 186 * @p_data: Data to be read 187 * @size: Byte size of the data to be read 188 * @timeout_ms: Timeout value in milliseconds 189 * Return 0 on success else a negative value 190 */ 191 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 192 uint32_t mem_addr, uint32_t mem_addr_size, 193 uint8_t *p_data, size_t size, unsigned int timeout_ms); 194 195 /* 196 * Send a data buffer in master mode on the I2C bus 197 * 198 * @hi2c: Reference to I2C bus handle structure 199 * @dev_addr: Target device I2C address 200 * @p_data: Data to be sent 201 * @size: Byte size of the data to be sent 202 * @timeout_ms: Timeout value in milliseconds 203 * Return 0 on success else a negative value 204 */ 205 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 206 uint8_t *p_data, size_t size, 207 unsigned int timeout_ms); 208 209 /* 210 * Receive a data buffer in master mode on the I2C bus 211 * 212 * @hi2c: Reference to I2C bus handle structure 213 * @dev_addr: Target device I2C address 214 * @p_data: Buffer for the received data 215 * @size: Byte size of the data to be received 216 * @timeout_ms: Timeout value in milliseconds 217 * Return 0 on success else a negative value 218 */ 219 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 220 uint8_t *p_data, size_t size, 221 unsigned int timeout_ms); 222 223 /* 224 * Optimized 1 byte read/write function for unpaged sequences. 225 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 226 * Return 0 on success else a negative value 227 */ 228 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 229 unsigned int mem_addr, uint8_t *p_data, 230 bool write); 231 232 /* 233 * Check link with the I2C device 234 * 235 * @hi2c: Reference to I2C bus handle structure 236 * @dev_addr: Target device I2C address 237 * @trials: Number of attempts of I2C request 238 * @timeout_ms: Timeout value in milliseconds for each I2C request 239 * Return 0 on success else a negative value 240 */ 241 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 242 unsigned int trials, unsigned int timeout_ms); 243 244 /* 245 * Suspend I2C bus. 246 * Bus owner is reponsible for calling stm32_i2c_suspend(). 247 * 248 * @hi2c: Reference to I2C bus handle structure 249 */ 250 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 251 252 /* 253 * Resume I2C bus. 254 * Bus owner is reponsible for calling stm32_i2c_resume(). 255 * 256 * @hi2c: Reference to I2C bus handle structure 257 */ 258 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 259 260 /* 261 * Return true if I2C bus is enabled for secure world only, false otherwise 262 */ 263 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 264 { 265 return hi2c->dt_status == DT_STATUS_OK_SEC; 266 } 267 268 #endif /* __STM32_I2C_H */ 269