1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/stm32_gpio.h> 10 #include <mm/core_memprot.h> 11 #include <stdbool.h> 12 #include <stdint.h> 13 #include <util.h> 14 #include <types_ext.h> 15 16 /* 17 * I2C specification values as per version 6.0, 4th of April 2014 [1], 18 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 19 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 20 * 21 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 22 */ 23 enum i2c_speed_e { 24 I2C_SPEED_STANDARD, /* 100 kHz */ 25 I2C_SPEED_FAST, /* 400 kHz */ 26 I2C_SPEED_FAST_PLUS, /* 1 MHz */ 27 }; 28 29 #define I2C_STANDARD_RATE 100000 30 #define I2C_FAST_RATE 400000 31 #define I2C_FAST_PLUS_RATE 1000000 32 33 /* 34 * Initialization configuration structure for the STM32 I2C bus. 35 * Refer to the SoC Reference Manual for more details on configuration items. 36 * 37 * @pbase: I2C interface base address 38 * @clock: I2C bus/interface clock 39 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 40 * @own_address1: 7-bit or 10-bit first device own address. 41 * @dual_address_mode: True if enabling Dual-Addressing mode 42 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 43 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 44 * @general_call_mode: True if enbling General-Call mode 45 * @no_stretch_mode: If enabling the No-Stretch mode 46 * @rise_time: SCL clock pin rising time in nanoseconds 47 * @fall_time: SCL clock pin falling time in nanoseconds 48 * @speed_mode: I2C clock source frequency mode 49 * @analog_filter: True if enabling analog filter 50 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 51 */ 52 struct stm32_i2c_init_s { 53 paddr_t pbase; 54 unsigned int clock; 55 bool addr_mode_10b_not_7b; 56 uint32_t own_address1; 57 bool dual_address_mode; 58 uint32_t own_address2; 59 uint32_t own_address2_masks; 60 bool general_call_mode; 61 bool no_stretch_mode; 62 uint32_t rise_time; 63 uint32_t fall_time; 64 enum i2c_speed_e speed_mode; 65 bool analog_filter; 66 uint8_t digital_filter_coef; 67 }; 68 69 enum i2c_state_e { 70 I2C_STATE_RESET, /* Not yet initialized */ 71 I2C_STATE_READY, /* Ready for use */ 72 I2C_STATE_BUSY, /* Internal process ongoing */ 73 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 74 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 75 I2C_STATE_SUSPENDED, /* Bus is supended */ 76 }; 77 78 enum i2c_mode_e { 79 I2C_MODE_NONE, /* No active communication */ 80 I2C_MODE_MASTER, /* Communication in Master Mode */ 81 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 82 I2C_MODE_MEM, /* Communication in Memory Mode */ 83 }; 84 85 #define I2C_ERROR_NONE 0x0 86 #define I2C_ERROR_BERR BIT(0) 87 #define I2C_ERROR_ARLO BIT(1) 88 #define I2C_ERROR_ACKF BIT(2) 89 #define I2C_ERROR_OVR BIT(3) 90 #define I2C_ERROR_DMA BIT(4) 91 #define I2C_ERROR_TIMEOUT BIT(5) 92 #define I2C_ERROR_SIZE BIT(6) 93 94 /* I2C interface registers state */ 95 struct i2c_cfg { 96 uint32_t timingr; 97 uint32_t oar1; 98 uint32_t oar2; 99 uint32_t cr1; 100 uint32_t cr2; 101 }; 102 103 /* 104 * I2C bus device 105 * @base: I2C SoC registers base address 106 * @clock: clock ID 107 * @i2c_state: Driver state ID I2C_STATE_* 108 * @i2c_err: Last error code I2C_ERROR_* 109 * @sec_cfg: I2C regsiters configuration storage 110 * @pinctrl: PINCTRLs configuration for the I2C PINs 111 * @pinctrl_count: Number of PINCTRLs elements 112 */ 113 struct i2c_handle_s { 114 struct io_pa_va base; 115 unsigned long clock; 116 enum i2c_state_e i2c_state; 117 uint32_t i2c_err; 118 struct i2c_cfg sec_cfg; 119 struct stm32_pinctrl *pinctrl; 120 size_t pinctrl_count; 121 }; 122 123 /* STM32 specific defines */ 124 #define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD 125 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 126 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 127 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 128 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 129 #define STM32_I2C_DIGITAL_FILTER_MAX 16 130 131 /* 132 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 133 * 134 * @fdt: Reference to DT 135 * @node: Target I2C node in the DT 136 * @init: Output stm32_i2c_init_s structure 137 * @pinctrl: Reference to output pinctrl array 138 * @pinctrl_count: Input @pinctrl array size, output expected size 139 * Return 0 on success else a negative value 140 */ 141 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 142 struct stm32_i2c_init_s *init, 143 struct stm32_pinctrl **pinctrl, 144 size_t *pinctrl_count); 145 146 /* 147 * Initialize I2C bus handle from input configuration directives 148 * 149 * @hi2c: Reference to I2C bus handle structure 150 * @init_data: Input stm32_i2c_init_s structure 151 * Return 0 on success else a negative value 152 */ 153 int stm32_i2c_init(struct i2c_handle_s *hi2c, 154 struct stm32_i2c_init_s *init_data); 155 156 /* 157 * Send a memory write request in the I2C bus 158 * 159 * @hi2c: Reference to I2C bus handle structure 160 * @dev_addr: Target device I2C address 161 * @mem_addr: Target device memory address 162 * @mem_addr_size: Byte size of internal memory address 163 * @p_data: Data to be written 164 * @size: Byte size of the data to be written 165 * @timeout_ms: Timeout value in milliseconds 166 * Return 0 on success else a negative value 167 */ 168 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 169 uint32_t mem_addr, uint32_t mem_addr_size, 170 uint8_t *p_data, size_t size, unsigned int timeout_ms); 171 172 /* 173 * Send a memory read request in the I2C bus 174 * 175 * @hi2c: Reference to I2C bus handle structure 176 * @dev_addr: Target device I2C address 177 * @mem_addr: Target device memory address 178 * @mem_addr_size: Byte size of internal memory address 179 * @p_data: Data to be read 180 * @size: Byte size of the data to be read 181 * @timeout_ms: Timeout value in milliseconds 182 * Return 0 on success else a negative value 183 */ 184 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 185 uint32_t mem_addr, uint32_t mem_addr_size, 186 uint8_t *p_data, size_t size, unsigned int timeout_ms); 187 188 /* 189 * Send a data buffer in master mode on the I2C bus 190 * 191 * @hi2c: Reference to I2C bus handle structure 192 * @dev_addr: Target device I2C address 193 * @p_data: Data to be sent 194 * @size: Byte size of the data to be sent 195 * @timeout_ms: Timeout value in milliseconds 196 * Return 0 on success else a negative value 197 */ 198 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 199 uint8_t *p_data, size_t size, 200 unsigned int timeout_ms); 201 202 /* 203 * Receive a data buffer in master mode on the I2C bus 204 * 205 * @hi2c: Reference to I2C bus handle structure 206 * @dev_addr: Target device I2C address 207 * @p_data: Buffer for the received data 208 * @size: Byte size of the data to be received 209 * @timeout_ms: Timeout value in milliseconds 210 * Return 0 on success else a negative value 211 */ 212 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 213 uint8_t *p_data, size_t size, 214 unsigned int timeout_ms); 215 216 /* 217 * Optimized 1 byte read/write function for unpaged sequences. 218 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 219 * Return 0 on success else a negative value 220 */ 221 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 222 unsigned int mem_addr, uint8_t *p_data, 223 bool write); 224 225 /* 226 * Check link with the I2C device 227 * 228 * @hi2c: Reference to I2C bus handle structure 229 * @dev_addr: Target device I2C address 230 * @trials: Number of attempts of I2C request 231 * @timeout_ms: Timeout value in milliseconds for each I2C request 232 * Return 0 on success else a negative value 233 */ 234 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 235 unsigned int trials, unsigned int timeout_ms); 236 237 /* 238 * Suspend I2C bus. 239 * Bus owner is reponsible for calling stm32_i2c_suspend(). 240 * 241 * @hi2c: Reference to I2C bus handle structure 242 */ 243 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 244 245 /* 246 * Resume I2C bus. 247 * Bus owner is reponsible for calling stm32_i2c_resume(). 248 * 249 * @hi2c: Reference to I2C bus handle structure 250 */ 251 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 252 253 #endif /* __STM32_I2C_H */ 254