1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <drivers/stm32_gpio.h> 10 #include <kernel/dt.h> 11 #include <mm/core_memprot.h> 12 #include <stdbool.h> 13 #include <stdint.h> 14 #include <util.h> 15 #include <types_ext.h> 16 17 /* 18 * I2C specification values as per version 6.0, 4th of April 2014 [1], 19 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 20 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 21 * 22 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 23 */ 24 #define I2C_STANDARD_RATE U(100000) 25 #define I2C_FAST_RATE U(400000) 26 #define I2C_FAST_PLUS_RATE U(1000000) 27 28 /* 29 * Initialization configuration structure for the STM32 I2C bus. 30 * Refer to the SoC Reference Manual for more details on configuration items. 31 * 32 * @dt_status: non-secure/secure status read from DT 33 * @pbase: I2C interface base address 34 * @clock: I2C bus/interface clock 35 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 36 * @own_address1: 7-bit or 10-bit first device own address. 37 * @dual_address_mode: True if enabling Dual-Addressing mode 38 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 39 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 40 * @general_call_mode: True if enbling General-Call mode 41 * @no_stretch_mode: If enabling the No-Stretch mode 42 * @rise_time: SCL clock pin rising time in nanoseconds 43 * @fall_time: SCL clock pin falling time in nanoseconds 44 * @bus_rate: Specifies the I2C clock frequency in Hertz 45 * @analog_filter: True if enabling analog filter 46 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 47 */ 48 struct stm32_i2c_init_s { 49 unsigned int dt_status; 50 paddr_t pbase; 51 unsigned int clock; 52 bool addr_mode_10b_not_7b; 53 uint32_t own_address1; 54 bool dual_address_mode; 55 uint32_t own_address2; 56 uint32_t own_address2_masks; 57 bool general_call_mode; 58 bool no_stretch_mode; 59 uint32_t rise_time; 60 uint32_t fall_time; 61 uint32_t bus_rate; 62 bool analog_filter; 63 uint8_t digital_filter_coef; 64 }; 65 66 enum i2c_state_e { 67 I2C_STATE_RESET, /* Not yet initialized */ 68 I2C_STATE_READY, /* Ready for use */ 69 I2C_STATE_BUSY, /* Internal process ongoing */ 70 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 71 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 72 I2C_STATE_SUSPENDED, /* Bus is supended */ 73 }; 74 75 enum i2c_mode_e { 76 I2C_MODE_NONE, /* No active communication */ 77 I2C_MODE_MASTER, /* Communication in Master Mode */ 78 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 79 I2C_MODE_MEM, /* Communication in Memory Mode */ 80 }; 81 82 #define I2C_ERROR_NONE U(0x0) 83 #define I2C_ERROR_BERR BIT(0) 84 #define I2C_ERROR_ARLO BIT(1) 85 #define I2C_ERROR_ACKF BIT(2) 86 #define I2C_ERROR_OVR BIT(3) 87 #define I2C_ERROR_DMA BIT(4) 88 #define I2C_ERROR_TIMEOUT BIT(5) 89 #define I2C_ERROR_SIZE BIT(6) 90 91 /* I2C interface registers state */ 92 struct i2c_cfg { 93 uint32_t timingr; 94 uint32_t oar1; 95 uint32_t oar2; 96 uint32_t cr1; 97 uint32_t cr2; 98 }; 99 100 /* 101 * I2C bus device 102 * @base: I2C SoC registers base address 103 * @dt_status: non-secure/secure status read from DT 104 * @clock: clock ID 105 * @i2c_state: Driver state ID I2C_STATE_* 106 * @i2c_err: Last error code I2C_ERROR_* 107 * @saved_timing: Saved timing value if already computed 108 * @saved_frequency: Saved frequency value if already computed 109 * @sec_cfg: I2C registers configuration storage 110 * @pinctrl: PINCTRLs configuration for the I2C PINs 111 * @pinctrl_count: Number of PINCTRLs elements 112 */ 113 struct i2c_handle_s { 114 struct io_pa_va base; 115 unsigned int dt_status; 116 unsigned long clock; 117 enum i2c_state_e i2c_state; 118 uint32_t i2c_err; 119 uint32_t saved_timing; 120 unsigned long saved_frequency; 121 struct i2c_cfg sec_cfg; 122 struct stm32_pinctrl *pinctrl; 123 size_t pinctrl_count; 124 }; 125 126 /* STM32 specific defines */ 127 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 128 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 129 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 130 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 131 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 132 133 /* 134 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 135 * 136 * @fdt: Reference to DT 137 * @node: Target I2C node in the DT 138 * @init: Output stm32_i2c_init_s structure 139 * @pinctrl: Reference to output pinctrl array 140 * @pinctrl_count: Input @pinctrl array size, output expected size 141 * Return 0 on success else a negative value 142 */ 143 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 144 struct stm32_i2c_init_s *init, 145 struct stm32_pinctrl **pinctrl, 146 size_t *pinctrl_count); 147 148 /* 149 * Initialize I2C bus handle from input configuration directives 150 * 151 * @hi2c: Reference to I2C bus handle structure 152 * @init_data: Input stm32_i2c_init_s structure 153 * Return 0 on success else a negative value 154 */ 155 int stm32_i2c_init(struct i2c_handle_s *hi2c, 156 struct stm32_i2c_init_s *init_data); 157 158 /* 159 * Send a memory write request in the I2C bus 160 * 161 * @hi2c: Reference to I2C bus handle structure 162 * @dev_addr: Target device I2C address 163 * @mem_addr: Target device memory address 164 * @mem_addr_size: Byte size of internal memory address 165 * @p_data: Data to be written 166 * @size: Byte size of the data to be written 167 * @timeout_ms: Timeout value in milliseconds 168 * Return 0 on success else a negative value 169 */ 170 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 171 uint32_t mem_addr, uint32_t mem_addr_size, 172 uint8_t *p_data, size_t size, unsigned int timeout_ms); 173 174 /* 175 * Send a memory read request in the I2C bus 176 * 177 * @hi2c: Reference to I2C bus handle structure 178 * @dev_addr: Target device I2C address 179 * @mem_addr: Target device memory address 180 * @mem_addr_size: Byte size of internal memory address 181 * @p_data: Data to be read 182 * @size: Byte size of the data to be read 183 * @timeout_ms: Timeout value in milliseconds 184 * Return 0 on success else a negative value 185 */ 186 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 187 uint32_t mem_addr, uint32_t mem_addr_size, 188 uint8_t *p_data, size_t size, unsigned int timeout_ms); 189 190 /* 191 * Send a data buffer in master mode on the I2C bus 192 * 193 * @hi2c: Reference to I2C bus handle structure 194 * @dev_addr: Target device I2C address 195 * @p_data: Data to be sent 196 * @size: Byte size of the data to be sent 197 * @timeout_ms: Timeout value in milliseconds 198 * Return 0 on success else a negative value 199 */ 200 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 201 uint8_t *p_data, size_t size, 202 unsigned int timeout_ms); 203 204 /* 205 * Receive a data buffer in master mode on the I2C bus 206 * 207 * @hi2c: Reference to I2C bus handle structure 208 * @dev_addr: Target device I2C address 209 * @p_data: Buffer for the received data 210 * @size: Byte size of the data to be received 211 * @timeout_ms: Timeout value in milliseconds 212 * Return 0 on success else a negative value 213 */ 214 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 215 uint8_t *p_data, size_t size, 216 unsigned int timeout_ms); 217 218 /* 219 * Optimized 1 byte read/write function for unpaged sequences. 220 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 221 * Return 0 on success else a negative value 222 */ 223 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 224 unsigned int mem_addr, uint8_t *p_data, 225 bool write); 226 227 /* 228 * Check link with the I2C device 229 * 230 * @hi2c: Reference to I2C bus handle structure 231 * @dev_addr: Target device I2C address 232 * @trials: Number of attempts of I2C request 233 * @timeout_ms: Timeout value in milliseconds for each I2C request 234 * Return 0 on success else a negative value 235 */ 236 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 237 unsigned int trials, unsigned int timeout_ms); 238 239 /* 240 * Suspend I2C bus. 241 * Bus owner is reponsible for calling stm32_i2c_suspend(). 242 * 243 * @hi2c: Reference to I2C bus handle structure 244 */ 245 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 246 247 /* 248 * Resume I2C bus. 249 * Bus owner is reponsible for calling stm32_i2c_resume(). 250 * 251 * @hi2c: Reference to I2C bus handle structure 252 */ 253 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 254 255 /* 256 * Return true if I2C bus is enabled for secure world only, false otherwise 257 */ 258 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 259 { 260 return hi2c->dt_status == DT_STATUS_OK_SEC; 261 } 262 263 #endif /* __STM32_I2C_H */ 264