1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 */ 5 6 #ifndef DRIVERS_STM32_I2C_H 7 #define DRIVERS_STM32_I2C_H 8 9 #include <drivers/clk.h> 10 #include <drivers/i2c.h> 11 #include <drivers/pinctrl.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <mm/core_memprot.h> 15 #include <stdbool.h> 16 #include <stdint.h> 17 #include <util.h> 18 #include <types_ext.h> 19 20 /* 21 * I2C specification values as per version 6.0, 4th of April 2014 [1], 22 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 23 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 24 * 25 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 26 */ 27 #define I2C_STANDARD_RATE U(100000) 28 #define I2C_FAST_RATE U(400000) 29 #define I2C_FAST_PLUS_RATE U(1000000) 30 31 /* 32 * struct stm32_i2c_init_s - STM32 I2C configuration data 33 * 34 * @dt_status: non-secure/secure status read from DT 35 * @pbase: I2C interface base address 36 * @reg_size: I2C interface register map size 37 * @clock: I2C bus/interface clock 38 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 39 * @own_address1: 7-bit or 10-bit first device own address. 40 * @dual_address_mode: True if enabling Dual-Addressing mode 41 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 42 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 43 * @general_call_mode: True if enbling General-Call mode 44 * @no_stretch_mode: If enabling the No-Stretch mode 45 * @rise_time: SCL clock pin rising time in nanoseconds 46 * @fall_time: SCL clock pin falling time in nanoseconds 47 * @bus_rate: Specifies the I2C clock frequency in Hertz 48 * @analog_filter: True if enabling analog filter 49 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 50 */ 51 struct stm32_i2c_init_s { 52 unsigned int dt_status; 53 paddr_t pbase; 54 size_t reg_size; 55 struct clk *clock; 56 bool addr_mode_10b_not_7b; 57 uint32_t own_address1; 58 bool dual_address_mode; 59 uint32_t own_address2; 60 uint32_t own_address2_masks; 61 bool general_call_mode; 62 bool no_stretch_mode; 63 uint32_t rise_time; 64 uint32_t fall_time; 65 uint32_t bus_rate; 66 bool analog_filter; 67 uint8_t digital_filter_coef; 68 }; 69 70 enum i2c_state_e { 71 I2C_STATE_RESET, /* Not yet initialized */ 72 I2C_STATE_READY, /* Ready for use */ 73 I2C_STATE_BUSY, /* Internal process ongoing */ 74 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 75 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 76 I2C_STATE_SUSPENDED, /* Bus is supended */ 77 }; 78 79 enum i2c_mode_e { 80 I2C_MODE_NONE, /* No active communication */ 81 I2C_MODE_MASTER, /* Communication in Master Mode */ 82 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 83 I2C_MODE_MEM, /* Communication in Memory Mode */ 84 }; 85 86 #define I2C_ERROR_NONE U(0x0) 87 #define I2C_ERROR_BERR BIT(0) 88 #define I2C_ERROR_ARLO BIT(1) 89 #define I2C_ERROR_ACKF BIT(2) 90 #define I2C_ERROR_OVR BIT(3) 91 #define I2C_ERROR_DMA BIT(4) 92 #define I2C_ERROR_TIMEOUT BIT(5) 93 #define I2C_ERROR_SIZE BIT(6) 94 95 /* I2C interface registers state */ 96 struct i2c_cfg { 97 uint32_t timingr; 98 uint32_t oar1; 99 uint32_t oar2; 100 uint32_t cr1; 101 uint32_t cr2; 102 }; 103 104 /* 105 * I2C bus device 106 * @base: I2C SoC registers base address 107 * @reg_size: I2C SoC registers address map size 108 * @dt_status: non-secure/secure status read from DT 109 * @clock: clock ID 110 * @i2c_state: Driver state ID I2C_STATE_* 111 * @i2c_err: Last error code I2C_ERROR_* 112 * @saved_timing: Saved timing value if already computed 113 * @saved_frequency: Saved frequency value if already computed 114 * @sec_cfg: I2C registers configuration storage 115 * @pinctrl: Pin control configuration for the I2C bus in active state 116 * @pinctrl_sleep: Pin control configuration for the I2C bus in standby state 117 */ 118 struct i2c_handle_s { 119 struct io_pa_va base; 120 size_t reg_size; 121 unsigned int dt_status; 122 struct clk *clock; 123 enum i2c_state_e i2c_state; 124 uint32_t i2c_err; 125 uint32_t saved_timing; 126 unsigned long saved_frequency; 127 struct i2c_cfg sec_cfg; 128 struct pinctrl_state *pinctrl; 129 struct pinctrl_state *pinctrl_sleep; 130 }; 131 132 /* 133 * struct stm32_i2c_dev - Bus consumer device over an STM32 I2C bus 134 * @i2c_dev: I2C consumer instance 135 * @i2c_ctrl: I2C bus control operation 136 * @handle: Handle on a single STM32 I2C bus interface 137 */ 138 struct stm32_i2c_dev { 139 struct i2c_dev i2c_dev; 140 struct i2c_ctrl i2c_ctrl; 141 struct i2c_handle_s *handle; 142 }; 143 144 /* STM32 specific defines */ 145 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 146 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 147 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 148 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 149 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 150 151 /* 152 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 153 * 154 * @fdt: Reference to DT 155 * @node: Target I2C node in the DT 156 * @init: Output stm32_i2c_init_s structure 157 * @pinctrl_active: Output active I2C pinctrl state 158 * @pinctrl_sleep: Output suspended I2C pinctrl state 159 * Return a TEE_Result compliant value 160 */ 161 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 162 struct stm32_i2c_init_s *init, 163 struct pinctrl_state **pinctrl_active, 164 struct pinctrl_state **pinctrl_sleep); 165 166 /* 167 * Initialize I2C bus handle from input configuration directives 168 * 169 * @hi2c: Reference to I2C bus handle structure 170 * @init_data: Input stm32_i2c_init_s structure 171 * Return 0 on success else a negative value 172 */ 173 int stm32_i2c_init(struct i2c_handle_s *hi2c, 174 struct stm32_i2c_init_s *init_data); 175 176 /* 177 * Send a memory write request in the I2C bus 178 * 179 * @hi2c: Reference to I2C bus handle structure 180 * @dev_addr: Target device I2C address 181 * @mem_addr: Target device memory address 182 * @mem_addr_size: Byte size of internal memory address 183 * @p_data: Data to be written 184 * @size: Byte size of the data to be written 185 * @timeout_ms: Timeout value in milliseconds 186 * Return 0 on success else a negative value 187 */ 188 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 189 uint32_t mem_addr, uint32_t mem_addr_size, 190 uint8_t *p_data, size_t size, unsigned int timeout_ms); 191 192 /* 193 * Send a memory read request in the I2C bus 194 * 195 * @hi2c: Reference to I2C bus handle structure 196 * @dev_addr: Target device I2C address 197 * @mem_addr: Target device memory address 198 * @mem_addr_size: Byte size of internal memory address 199 * @p_data: Data to be read 200 * @size: Byte size of the data to be read 201 * @timeout_ms: Timeout value in milliseconds 202 * Return 0 on success else a negative value 203 */ 204 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 205 uint32_t mem_addr, uint32_t mem_addr_size, 206 uint8_t *p_data, size_t size, unsigned int timeout_ms); 207 208 /* 209 * Send a data buffer in master mode on the I2C bus 210 * 211 * @hi2c: Reference to I2C bus handle structure 212 * @dev_addr: Target device I2C address 213 * @p_data: Data to be sent 214 * @size: Byte size of the data to be sent 215 * @timeout_ms: Timeout value in milliseconds 216 * Return 0 on success else a negative value 217 */ 218 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 219 uint8_t *p_data, size_t size, 220 unsigned int timeout_ms); 221 222 /* 223 * Receive a data buffer in master mode on the I2C bus 224 * 225 * @hi2c: Reference to I2C bus handle structure 226 * @dev_addr: Target device I2C address 227 * @p_data: Buffer for the received data 228 * @size: Byte size of the data to be received 229 * @timeout_ms: Timeout value in milliseconds 230 * Return 0 on success else a negative value 231 */ 232 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 233 uint8_t *p_data, size_t size, 234 unsigned int timeout_ms); 235 236 /* 237 * Optimized 1 byte read/write function for unpaged sequences. 238 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 239 * Return 0 on success else a negative value 240 */ 241 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 242 unsigned int mem_addr, uint8_t *p_data, 243 bool write); 244 245 /* 246 * Check link with the I2C device 247 * 248 * @hi2c: Reference to I2C bus handle structure 249 * @dev_addr: Target device I2C address 250 * @trials: Number of attempts of I2C request 251 * @timeout_ms: Timeout value in milliseconds for each I2C request 252 * Return 0 on success else a negative value 253 */ 254 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 255 unsigned int trials, unsigned int timeout_ms); 256 257 /* 258 * Suspend I2C bus. 259 * Bus owner is reponsible for calling stm32_i2c_suspend(). 260 * 261 * @hi2c: Reference to I2C bus handle structure 262 */ 263 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 264 265 /* 266 * Resume I2C bus. 267 * Bus owner is reponsible for calling stm32_i2c_resume(). 268 * 269 * @hi2c: Reference to I2C bus handle structure 270 */ 271 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 272 273 /* 274 * Return true if I2C bus is enabled for secure world only, false otherwise 275 */ 276 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 277 { 278 return hi2c->dt_status == DT_STATUS_OK_SEC; 279 } 280 281 #endif /* DRIVERS_STM32_I2C_H*/ 282