1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 */ 5 6 #ifndef __STM32_I2C_H 7 #define __STM32_I2C_H 8 9 #include <mm/core_memprot.h> 10 #include <stdbool.h> 11 #include <stdint.h> 12 #include <util.h> 13 #include <types_ext.h> 14 15 /* 16 * Initialization configuration structure for the STM32 I2C bus. 17 * Refer to the SoC Reference Manual for more details on configuration items. 18 * 19 * @pbase: I2C interface base address 20 * @clock: I2C bus/interface clock 21 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 22 * @own_address1: 7-bit or 10-bit first device own address. 23 * @dual_address_mode: True if enabling Dual-Addressing mode 24 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 25 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 26 * @general_call_mode: True if enbling General-Call mode 27 * @no_stretch_mode: If enabling the No-Stretch mode 28 * @rise_time: SCL clock pin rising time in nanoseconds 29 * @fall_time: SCL clock pin falling time in nanoseconds 30 * @speed_mode: I2C clock source frequency mode 31 * @analog_filter: True if enabling analog filter 32 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 33 */ 34 struct stm32_i2c_init_s { 35 paddr_t pbase; 36 unsigned int clock; 37 bool addr_mode_10b_not_7b; 38 uint32_t own_address1; 39 bool dual_address_mode; 40 uint32_t own_address2; 41 uint32_t own_address2_masks; 42 bool general_call_mode; 43 bool no_stretch_mode; 44 uint32_t rise_time; 45 uint32_t fall_time; 46 enum i2c_speed_e speed_mode; 47 bool analog_filter; 48 uint8_t digital_filter_coef; 49 }; 50 51 enum i2c_state_e { 52 I2C_STATE_RESET, /* Not yet initialized */ 53 I2C_STATE_READY, /* Ready for use */ 54 I2C_STATE_BUSY, /* Internal process ongoing */ 55 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 56 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 57 I2C_STATE_SUSPENDED, /* Bus is supended */ 58 }; 59 60 enum i2c_mode_e { 61 I2C_MODE_NONE, /* No active communication */ 62 I2C_MODE_MASTER, /* Communication in Master Mode */ 63 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 64 I2C_MODE_MEM, /* Communication in Memory Mode */ 65 }; 66 67 #define I2C_ERROR_NONE 0x0 68 #define I2C_ERROR_BERR BIT(0) 69 #define I2C_ERROR_ARLO BIT(1) 70 #define I2C_ERROR_ACKF BIT(2) 71 #define I2C_ERROR_OVR BIT(3) 72 #define I2C_ERROR_DMA BIT(4) 73 #define I2C_ERROR_TIMEOUT BIT(5) 74 #define I2C_ERROR_SIZE BIT(6) 75 76 /* I2C interface registers state */ 77 struct i2c_cfg { 78 uint32_t timingr; 79 uint32_t oar1; 80 uint32_t oar2; 81 uint32_t cr1; 82 uint32_t cr2; 83 }; 84 85 /* 86 * I2C bus device 87 * @base: I2C SoC registers base address 88 * @clock: clock ID 89 * @i2c_state: Driver state ID I2C_STATE_* 90 * @i2c_err: Last error code I2C_ERROR_* 91 * @sec_cfg: I2C regsiters configuration storage 92 */ 93 struct i2c_handle_s { 94 struct io_pa_va base; 95 unsigned long clock; 96 enum i2c_state_e i2c_state; 97 uint32_t i2c_err; 98 struct i2c_cfg sec_cfg; 99 }; 100 101 /* STM32 specific defines */ 102 #define STM32_I2C_SPEED_DEFAULT I2C_SPEED_STANDARD 103 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 104 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 105 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 106 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 107 #define STM32_I2C_DIGITAL_FILTER_MAX 16 108 109 /* 110 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 111 * 112 * @fdt: Reference to DT 113 * @node: Target I2C node in the DT 114 * @init: Output stm32_i2c_init_s structure 115 * Return 0 on success else a negative value 116 */ 117 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 118 struct stm32_i2c_init_s *init); 119 120 /* 121 * Initialize I2C bus handle from input configuration directives 122 * 123 * @hi2c: Reference to I2C bus handle structure 124 * @init_data: Input stm32_i2c_init_s structure 125 * Return 0 on success else a negative value 126 */ 127 int stm32_i2c_init(struct i2c_handle_s *hi2c, 128 struct stm32_i2c_init_s *init_data); 129 130 /* 131 * Send a memory write request in the I2C bus 132 * 133 * @hi2c: Reference to I2C bus handle structure 134 * @dev_addr: Target device I2C address 135 * @mem_addr: Target device memory address 136 * @mem_addr_size: Byte size of internal memory address 137 * @p_data: Data to be written 138 * @size: Byte size of the data to be written 139 * @timeout_ms: Timeout value in milliseconds 140 * Return 0 on success else a negative value 141 */ 142 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 143 uint32_t mem_addr, uint32_t mem_addr_size, 144 uint8_t *p_data, size_t size, unsigned int timeout_ms); 145 146 /* 147 * Send a memory read request in the I2C bus 148 * 149 * @hi2c: Reference to I2C bus handle structure 150 * @dev_addr: Target device I2C address 151 * @mem_addr: Target device memory address 152 * @mem_addr_size: Byte size of internal memory address 153 * @p_data: Data to be read 154 * @size: Byte size of the data to be read 155 * @timeout_ms: Timeout value in milliseconds 156 * Return 0 on success else a negative value 157 */ 158 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 159 uint32_t mem_addr, uint32_t mem_addr_size, 160 uint8_t *p_data, size_t size, unsigned int timeout_ms); 161 162 /* 163 * Send a data buffer in master mode on the I2C bus 164 * 165 * @hi2c: Reference to I2C bus handle structure 166 * @dev_addr: Target device I2C address 167 * @p_data: Data to be sent 168 * @size: Byte size of the data to be sent 169 * @timeout_ms: Timeout value in milliseconds 170 * Return 0 on success else a negative value 171 */ 172 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 173 uint8_t *p_data, size_t size, 174 unsigned int timeout_ms); 175 176 /* 177 * Receive a data buffer in master mode on the I2C bus 178 * 179 * @hi2c: Reference to I2C bus handle structure 180 * @dev_addr: Target device I2C address 181 * @p_data: Buffer for the received data 182 * @size: Byte size of the data to be received 183 * @timeout_ms: Timeout value in milliseconds 184 * Return 0 on success else a negative value 185 */ 186 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 187 uint8_t *p_data, size_t size, 188 unsigned int timeout_ms); 189 190 /* 191 * Check link with the I2C device 192 * 193 * @hi2c: Reference to I2C bus handle structure 194 * @dev_addr: Target device I2C address 195 * @trials: Number of attempts of I2C request 196 * @timeout_ms: Timeout value in milliseconds for each I2C request 197 * Return 0 on success else a negative value 198 */ 199 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 200 unsigned int trials, unsigned int timeout_ms); 201 202 /* 203 * Suspend I2C bus. 204 * Bus owner is reponsible for calling stm32_i2c_suspend(). 205 * 206 * @hi2c: Reference to I2C bus handle structure 207 */ 208 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 209 210 /* 211 * Resume I2C bus. 212 * Bus owner is reponsible for calling stm32_i2c_resume(). 213 * 214 * @hi2c: Reference to I2C bus handle structure 215 */ 216 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 217 218 #endif /* __STM32_I2C_H */ 219