1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2 /* 3 * Copyright (c) 2017-2023, STMicroelectronics 4 */ 5 6 #ifndef __DRIVERS_STM32_I2C_H 7 #define __DRIVERS_STM32_I2C_H 8 9 #include <drivers/clk.h> 10 #include <drivers/i2c.h> 11 #include <drivers/pinctrl.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/mutex_pm_aware.h> 15 #include <mm/core_memprot.h> 16 #include <stdbool.h> 17 #include <stdint.h> 18 #include <util.h> 19 #include <types_ext.h> 20 21 /* 22 * I2C specification values as per version 6.0, 4th of April 2014 [1], 23 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 24 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 25 * 26 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 27 */ 28 #define I2C_STANDARD_RATE U(100000) 29 #define I2C_FAST_RATE U(400000) 30 #define I2C_FAST_PLUS_RATE U(1000000) 31 32 /* 33 * struct stm32_i2c_init_s - STM32 I2C configuration data 34 * 35 * @dt_status: non-secure/secure status read from DT 36 * @pbase: I2C interface base address 37 * @reg_size: I2C interface register map size 38 * @clock: I2C bus/interface clock 39 * @addr_mode_10b_not_7b: True if 10bit addressing mode, otherwise 7bit mode 40 * @own_address1: 7-bit or 10-bit first device own address. 41 * @dual_address_mode: True if enabling Dual-Addressing mode 42 * @own_address2: 7-bit second device own address (Dual-Addressing mode) 43 * @own_address2_masks: Acknowledge mask address (Dual-Addressing mode) 44 * @general_call_mode: True if enbling General-Call mode 45 * @no_stretch_mode: If enabling the No-Stretch mode 46 * @rise_time: SCL clock pin rising time in nanoseconds 47 * @fall_time: SCL clock pin falling time in nanoseconds 48 * @bus_rate: Specifies the I2C clock frequency in Hertz 49 * @analog_filter: True if enabling analog filter 50 * @digital_filter_coef: filter coef (below STM32_I2C_DIGITAL_FILTER_MAX) 51 */ 52 struct stm32_i2c_init_s { 53 unsigned int dt_status; 54 paddr_t pbase; 55 size_t reg_size; 56 struct clk *clock; 57 bool addr_mode_10b_not_7b; 58 uint32_t own_address1; 59 bool dual_address_mode; 60 uint32_t own_address2; 61 uint32_t own_address2_masks; 62 bool general_call_mode; 63 bool no_stretch_mode; 64 uint32_t rise_time; 65 uint32_t fall_time; 66 uint32_t bus_rate; 67 bool analog_filter; 68 uint8_t digital_filter_coef; 69 }; 70 71 enum i2c_state_e { 72 I2C_STATE_RESET, /* Not yet initialized */ 73 I2C_STATE_READY, /* Ready for use */ 74 I2C_STATE_BUSY, /* Internal process ongoing */ 75 I2C_STATE_BUSY_TX, /* Data Transmission ongoing */ 76 I2C_STATE_BUSY_RX, /* Data Reception ongoing */ 77 I2C_STATE_SUSPENDED, /* Bus is supended */ 78 }; 79 80 enum i2c_mode_e { 81 I2C_MODE_NONE, /* No active communication */ 82 I2C_MODE_MASTER, /* Communication in Master Mode */ 83 I2C_MODE_SLAVE, /* Communication in Slave Mode */ 84 I2C_MODE_MEM, /* Communication in Memory Mode */ 85 }; 86 87 #define I2C_ERROR_NONE U(0x0) 88 #define I2C_ERROR_BERR BIT(0) 89 #define I2C_ERROR_ARLO BIT(1) 90 #define I2C_ERROR_ACKF BIT(2) 91 #define I2C_ERROR_OVR BIT(3) 92 #define I2C_ERROR_DMA BIT(4) 93 #define I2C_ERROR_TIMEOUT BIT(5) 94 #define I2C_ERROR_SIZE BIT(6) 95 96 /* I2C interface registers state */ 97 struct i2c_cfg { 98 uint32_t timingr; 99 uint32_t oar1; 100 uint32_t oar2; 101 uint32_t cr1; 102 uint32_t cr2; 103 }; 104 105 /* 106 * I2C bus device 107 * @base: I2C SoC registers base address 108 * @reg_size: I2C SoC registers address map size 109 * @dt_status: non-secure/secure status read from DT 110 * @clock: clock ID 111 * @i2c_state: Driver state ID I2C_STATE_* 112 * @i2c_err: Last error code I2C_ERROR_* 113 * @saved_timing: Saved timing value if already computed 114 * @saved_frequency: Saved frequency value if already computed 115 * @sec_cfg: I2C registers configuration storage 116 * @pinctrl: Pin control configuration for the I2C bus in active state 117 * @pinctrl_sleep: Pin control configuration for the I2C bus in standby state 118 * @mu: Protection on concurrent access to the I2C bus considering PM context 119 */ 120 struct i2c_handle_s { 121 struct io_pa_va base; 122 size_t reg_size; 123 unsigned int dt_status; 124 struct clk *clock; 125 enum i2c_state_e i2c_state; 126 uint32_t i2c_err; 127 uint32_t saved_timing; 128 unsigned long saved_frequency; 129 struct i2c_cfg sec_cfg; 130 struct pinctrl_state *pinctrl; 131 struct pinctrl_state *pinctrl_sleep; 132 struct mutex_pm_aware mu; 133 }; 134 135 /* 136 * struct stm32_i2c_dev - Bus consumer device over an STM32 I2C bus 137 * @i2c_dev: I2C consumer instance 138 * @i2c_ctrl: I2C bus control operation 139 * @handle: Handle on a single STM32 I2C bus interface 140 */ 141 struct stm32_i2c_dev { 142 struct i2c_dev i2c_dev; 143 struct i2c_ctrl i2c_ctrl; 144 struct i2c_handle_s *handle; 145 }; 146 147 /* STM32 specific defines */ 148 #define STM32_I2C_RISE_TIME_DEFAULT U(25) /* ns */ 149 #define STM32_I2C_FALL_TIME_DEFAULT U(10) /* ns */ 150 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN U(50) /* ns */ 151 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX U(260) /* ns */ 152 #define STM32_I2C_DIGITAL_FILTER_MAX U(16) 153 154 /* 155 * Fill struct stm32_i2c_init_s from DT content for a given I2C node 156 * 157 * @fdt: Reference to DT 158 * @node: Target I2C node in the DT 159 * @init: Output stm32_i2c_init_s structure 160 * @pinctrl_active: Output active I2C pinctrl state 161 * @pinctrl_sleep: Output suspended I2C pinctrl state 162 * Return a TEE_Result compliant value 163 */ 164 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 165 struct stm32_i2c_init_s *init, 166 struct pinctrl_state **pinctrl_active, 167 struct pinctrl_state **pinctrl_sleep); 168 169 /* 170 * Initialize I2C bus handle from input configuration directives 171 * 172 * @hi2c: Reference to I2C bus handle structure 173 * @init_data: Input stm32_i2c_init_s structure 174 * Return 0 on success else a negative value 175 */ 176 int stm32_i2c_init(struct i2c_handle_s *hi2c, 177 struct stm32_i2c_init_s *init_data); 178 179 /* 180 * Send a memory write request in the I2C bus 181 * 182 * @hi2c: Reference to I2C bus handle structure 183 * @dev_addr: Target device I2C address 184 * @mem_addr: Target device memory address 185 * @mem_addr_size: Byte size of internal memory address 186 * @p_data: Data to be written 187 * @size: Byte size of the data to be written 188 * @timeout_ms: Timeout value in milliseconds 189 * Return 0 on success else a negative value 190 */ 191 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 192 uint32_t mem_addr, uint32_t mem_addr_size, 193 uint8_t *p_data, size_t size, unsigned int timeout_ms); 194 195 /* 196 * Send a memory read request in the I2C bus 197 * 198 * @hi2c: Reference to I2C bus handle structure 199 * @dev_addr: Target device I2C address 200 * @mem_addr: Target device memory address 201 * @mem_addr_size: Byte size of internal memory address 202 * @p_data: Data to be read 203 * @size: Byte size of the data to be read 204 * @timeout_ms: Timeout value in milliseconds 205 * Return 0 on success else a negative value 206 */ 207 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 208 uint32_t mem_addr, uint32_t mem_addr_size, 209 uint8_t *p_data, size_t size, unsigned int timeout_ms); 210 211 /* 212 * Send a data buffer in master mode on the I2C bus 213 * 214 * @hi2c: Reference to I2C bus handle structure 215 * @dev_addr: Target device I2C address 216 * @p_data: Data to be sent 217 * @size: Byte size of the data to be sent 218 * @timeout_ms: Timeout value in milliseconds 219 * Return 0 on success else a negative value 220 */ 221 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 222 uint8_t *p_data, size_t size, 223 unsigned int timeout_ms); 224 225 /* 226 * Receive a data buffer in master mode on the I2C bus 227 * 228 * @hi2c: Reference to I2C bus handle structure 229 * @dev_addr: Target device I2C address 230 * @p_data: Buffer for the received data 231 * @size: Byte size of the data to be received 232 * @timeout_ms: Timeout value in milliseconds 233 * Return 0 on success else a negative value 234 */ 235 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 236 uint8_t *p_data, size_t size, 237 unsigned int timeout_ms); 238 239 /* 240 * Optimized 1 byte read/write function for unpaged sequences. 241 * 8-bit addressing mode / single byte transferred / use default I2C timeout. 242 * Return 0 on success else a negative value 243 */ 244 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 245 unsigned int mem_addr, uint8_t *p_data, 246 bool write); 247 248 /* 249 * Check link with the I2C device 250 * 251 * @hi2c: Reference to I2C bus handle structure 252 * @dev_addr: Target device I2C address 253 * @trials: Number of attempts of I2C request 254 * @timeout_ms: Timeout value in milliseconds for each I2C request 255 * Return 0 on success else a negative value 256 */ 257 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 258 unsigned int trials, unsigned int timeout_ms); 259 260 /* 261 * Suspend I2C bus. 262 * Bus owner is reponsible for calling stm32_i2c_suspend(). 263 * 264 * @hi2c: Reference to I2C bus handle structure 265 */ 266 void stm32_i2c_suspend(struct i2c_handle_s *hi2c); 267 268 /* 269 * Resume I2C bus. 270 * Bus owner is reponsible for calling stm32_i2c_resume(). 271 * 272 * @hi2c: Reference to I2C bus handle structure 273 */ 274 void stm32_i2c_resume(struct i2c_handle_s *hi2c); 275 276 /* 277 * Return true if I2C bus is enabled for secure world only, false otherwise 278 */ 279 static inline bool i2c_is_secure(struct i2c_handle_s *hi2c) 280 { 281 return hi2c->dt_status == DT_STATUS_OK_SEC; 282 } 283 284 #endif /* __DRIVERS_STM32_I2C_H*/ 285