xref: /optee_os/core/include/drivers/stm32_gpio.h (revision 61bf256a049603ecd2588f1318ef476cd43fc13a)
14b5e93edSEtienne Carriere /* SPDX-License-Identifier: BSD-3-Clause */
24b5e93edSEtienne Carriere /*
3b38386fbSEtienne Carriere  * Copyright (c) 2017-2023, STMicroelectronics
44b5e93edSEtienne Carriere  */
54b5e93edSEtienne Carriere 
6d50fee03SEtienne Carriere #ifndef __DRIVERS_STM32_GPIO_H
7d50fee03SEtienne Carriere #define __DRIVERS_STM32_GPIO_H
84b5e93edSEtienne Carriere 
9aae59a1eSEtienne Carriere #include <assert.h>
10*61bf256aSGatien Chevallier #include <drivers/gpio.h>
11b38386fbSEtienne Carriere #include <drivers/pinctrl.h>
124b5e93edSEtienne Carriere #include <stdbool.h>
134b5e93edSEtienne Carriere #include <stdint.h>
144b5e93edSEtienne Carriere #include <stddef.h>
154b5e93edSEtienne Carriere 
1670ac0db5SEtienne Carriere struct pinctrl_state;
1769715ce9SEtienne Carriere struct stm32_pinctrl;
184b5e93edSEtienne Carriere 
19aae59a1eSEtienne Carriere #ifdef CFG_STM32_GPIO
204b5e93edSEtienne Carriere /*
2170ac0db5SEtienne Carriere  * Get the bank and pin indices related to a pin control state
2270ac0db5SEtienne Carriere  * @pinctrl: Pinctrl state
2370ac0db5SEtienne Carriere  * @bank: Output bank indices array or NULL
2470ac0db5SEtienne Carriere  * @pin: Output pin indices array or NULL
2570ac0db5SEtienne Carriere  * @count: [in] Number of cells of @bank and @pin, [out] pin count in @pinctrl
2670ac0db5SEtienne Carriere  */
2770ac0db5SEtienne Carriere void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *pinctrl,
2870ac0db5SEtienne Carriere 				 unsigned int *bank, unsigned int *pin,
2970ac0db5SEtienne Carriere 				 unsigned int *count);
30*61bf256aSGatien Chevallier 
31*61bf256aSGatien Chevallier /*
32*61bf256aSGatien Chevallier  * stm32_gpio_chip_bank_id() - Get the GPIO bank ID associated to a chip
33*61bf256aSGatien Chevallier  * @chip: GPIO chip associated to the bank
34*61bf256aSGatien Chevallier  */
35*61bf256aSGatien Chevallier unsigned int stm32_gpio_chip_bank_id(struct gpio_chip *chip);
3670ac0db5SEtienne Carriere #else
stm32_gpio_pinctrl_bank_pin(struct pinctrl_state * p __unused,unsigned int * bank __unused,unsigned int * pin __unused,unsigned int * count __unused)3770ac0db5SEtienne Carriere static inline void stm32_gpio_pinctrl_bank_pin(struct pinctrl_state *p __unused,
3870ac0db5SEtienne Carriere 					       unsigned int *bank __unused,
3970ac0db5SEtienne Carriere 					       unsigned int *pin __unused,
4070ac0db5SEtienne Carriere 					       unsigned int *count __unused)
4170ac0db5SEtienne Carriere {
4270ac0db5SEtienne Carriere }
43*61bf256aSGatien Chevallier 
44*61bf256aSGatien Chevallier static inline unsigned int __noreturn
stm32_gpio_chip_bank_id(struct gpio_chip * chip __unused)45*61bf256aSGatien Chevallier stm32_gpio_chip_bank_id(struct gpio_chip *chip __unused)
46*61bf256aSGatien Chevallier {
47*61bf256aSGatien Chevallier 	panic();
48*61bf256aSGatien Chevallier }
492c2f848fSEtienne Carriere #endif /*CFG_STM32_GPIO*/
50d50fee03SEtienne Carriere #endif /*__DRIVERS_STM32_GPIO_H*/
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