1cbb41c91SAbhishek Shah /* SPDX-License-Identifier: BSD-2-Clause */ 2cbb41c91SAbhishek Shah /* 3cbb41c91SAbhishek Shah * Copyright 2019 Broadcom. 4cbb41c91SAbhishek Shah */ 5cbb41c91SAbhishek Shah 6*fbe66cf8SEtienne Carriere #ifndef __DRIVERS_SP805_WDT_H 7*fbe66cf8SEtienne Carriere #define __DRIVERS_SP805_WDT_H 8cbb41c91SAbhishek Shah 9cbb41c91SAbhishek Shah #include <drivers/wdt.h> 10cbb41c91SAbhishek Shah #include <kernel/interrupt.h> 11cbb41c91SAbhishek Shah #include <mm/core_memprot.h> 12cbb41c91SAbhishek Shah #include <types_ext.h> 13cbb41c91SAbhishek Shah 14cbb41c91SAbhishek Shah /* SP805 register offset */ 15cbb41c91SAbhishek Shah #define WDT_LOAD_OFFSET 0x000 16cbb41c91SAbhishek Shah #define WDT_CONTROL_OFFSET 0x008 17cbb41c91SAbhishek Shah #define WDT_INTCLR_OFFSET 0x00c 18cbb41c91SAbhishek Shah #define WDT_LOCK_OFFSET 0xc00 19c2e4eb43SAnton Rybakov #define WDT_SIZE 0xc04 20cbb41c91SAbhishek Shah 21cbb41c91SAbhishek Shah /* Magic word to unlock the wd registers */ 22cbb41c91SAbhishek Shah #define WDT_UNLOCK_KEY 0x1ACCE551 23cbb41c91SAbhishek Shah #define WDT_LOCK_KEY 0x1 24cbb41c91SAbhishek Shah 25cbb41c91SAbhishek Shah /* Register field definitions */ 26cbb41c91SAbhishek Shah #define WDT_INT_EN BIT(0) 27cbb41c91SAbhishek Shah #define WDT_RESET_EN BIT(1) 28cbb41c91SAbhishek Shah #define WDT_INT_CLR BIT(0) 29cbb41c91SAbhishek Shah 30cbb41c91SAbhishek Shah #define WDT_LOAD_MIN 0x1 31cbb41c91SAbhishek Shah 32cbb41c91SAbhishek Shah typedef void (*sp805_itr_handler_func_t)(struct wdt_chip *chip); 33cbb41c91SAbhishek Shah 34cbb41c91SAbhishek Shah struct sp805_wdt_data { 35cbb41c91SAbhishek Shah struct io_pa_va base; 36cbb41c91SAbhishek Shah struct wdt_chip chip; 37cbb41c91SAbhishek Shah uint32_t clk_rate; 38cbb41c91SAbhishek Shah uint32_t load_val; 39cbb41c91SAbhishek Shah uint32_t itr_num; 40cbb41c91SAbhishek Shah sp805_itr_handler_func_t itr_handler; 41cbb41c91SAbhishek Shah }; 42cbb41c91SAbhishek Shah 43cbb41c91SAbhishek Shah /* 44cbb41c91SAbhishek Shah * Initialize sp805 watchdog timer 45cbb41c91SAbhishek Shah * 46cbb41c91SAbhishek Shah * @pd: allocated sp805 watchdog timer platform data 47cbb41c91SAbhishek Shah * @base: physical base address of sp805 watchdog timer 48cbb41c91SAbhishek Shah * @clk_rate: rate of the clock driving the watchdog timer hardware 49cbb41c91SAbhishek Shah * @timeout: watchdog timer timeout in seconds 50cbb41c91SAbhishek Shah * Return a TEE_Result compliant status 51cbb41c91SAbhishek Shah */ 52cbb41c91SAbhishek Shah TEE_Result sp805_wdt_init(struct sp805_wdt_data *pd, paddr_t base, 53cbb41c91SAbhishek Shah uint32_t clk_rate, uint32_t timeout); 54cbb41c91SAbhishek Shah 55cbb41c91SAbhishek Shah /* 56cbb41c91SAbhishek Shah * Optionally register sp805 watchdog timer interrupt handler 57cbb41c91SAbhishek Shah * 58cbb41c91SAbhishek Shah * @pd: platform data of sp805 watchdog timer for which interrupt handler 59cbb41c91SAbhishek Shah * is to be registered 60cbb41c91SAbhishek Shah * @itr_num: sp805 watchdog timer interrupt id 61cbb41c91SAbhishek Shah * @itr_flag: interrupt attributes 62cbb41c91SAbhishek Shah * @itr_handler: Optional interrupt handler callback 63cbb41c91SAbhishek Shah * Return a TEE_Result compliant status 64cbb41c91SAbhishek Shah */ 65cbb41c91SAbhishek Shah TEE_Result sp805_register_itr_handler(struct sp805_wdt_data *pd, 66cbb41c91SAbhishek Shah uint32_t itr_num, uint32_t itr_flag, 67cbb41c91SAbhishek Shah sp805_itr_handler_func_t itr_handler); 68cbb41c91SAbhishek Shah 69*fbe66cf8SEtienne Carriere #endif /* __DRIVERS_SP805_WDT_H */ 70