1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Microchip SAMA7 UDDR Controller and DDR3 PHY Controller registers offsets 4 * and bit definitions. 5 * 6 * Copyright (C) [2024] Microchip Technology Inc. and its subsidiaries 7 * 8 * Author: Tony Han <tony.han@microchip.com> 9 */ 10 11 #ifndef __SAMA7_DDR_H__ 12 #define __SAMA7_DDR_H__ 13 14 /* DDR3PHY */ 15 /* DDR3PHY PHY Initialization Register */ 16 #define DDR3PHY_PIR 0x04 17 #define DDR3PHY_PIR_DLLBYP BIT(17) /* DLL Bypass */ 18 #define DDR3PHY_PIR_ITMSRST BIT(4) /* Interface Timing Module Soft Reset */ 19 #define DDR3PHY_PIR_DLLLOCK BIT(2) /* DLL Lock */ 20 #define DDR3PHY_PIR_DLLSRST BIT(1) /* DLL Soft Rest */ 21 #define DDR3PHY_PIR_INIT BIT(0) /* Initialization Trigger */ 22 23 /* DDR3PHY PHY General Configuration Register */ 24 #define DDR3PHY_PGCR 0x08 25 #define DDR3PHY_PGCR_CKDV1 BIT(13) /* CK# Disable Value */ 26 #define DDR3PHY_PGCR_CKDV0 BIT(12) /* CK Disable Value */ 27 28 /* DDR3PHY PHY General Status Register */ 29 #define DDR3PHY_PGSR 0x0C 30 #define DDR3PHY_PGSR_IDONE BIT(0) /* Initialization Done */ 31 32 /* DDR3PHY AC DLL Control Register */ 33 #define DDR3PHY_ACDLLCR 0x14 34 #define DDR3PHY_ACDLLCR_DLLSRST BIT(30) /* DLL Soft Reset */ 35 36 /* DDR3PHY AC I/O Configuration Register */ 37 #define DDR3PHY_ACIOCR 0x24 38 #define DDR3PHY_ACIOCR_CSPDD_CS0 BIT(18) /* CS#[0] Power Down Driver */ 39 #define DDR3PHY_ACIOCR_CKPDD_CK0 BIT(8) /* CK[0] Power Down Driver */ 40 #define DDR3PHY_ACIORC_ACPDD BIT(3) /* AC Power Down Driver */ 41 42 /* DDR3PHY DATX8 Common Configuration Register */ 43 #define DDR3PHY_DXCCR 0x28 44 #define DDR3PHY_DXCCR_DXPDR BIT(3) /* Data Power Down Receiver */ 45 46 /* DDR3PHY DDR System General Configuration Register */ 47 #define DDR3PHY_DSGCR 0x2C 48 #define DDR3PHY_DSGCR_ODTPDD_ODT0 BIT(20) /* ODT[0] Power Down Driver */ 49 50 /* ZQ status register 0 */ 51 #define DDR3PHY_ZQ0SR0 0x188 52 /* impedance select offset */ 53 #define DDR3PHY_ZQ0SR0_PDO_OFF 0 /* Pull-down output */ 54 #define DDR3PHY_ZQ0SR0_PUO_OFF 5 /* Pull-up output */ 55 #define DDR3PHY_ZQ0SR0_PDODT_OFF 10 /* Pull-down on-die termination*/ 56 #define DDR3PHY_ZQ0SRO_PUODT_OFF 15 /* Pull-up on-die termination */ 57 58 /* DDR3PHY DATX8 DLL Control Register */ 59 #define DDR3PHY_DX0DLLCR 0x1CC 60 #define DDR3PHY_DX1DLLCR 0x20C /* DATX8 DLL Control Register */ 61 #define DDR3PHY_DXDLLCR_DLLDIS BIT(31) /* DLL Disable */ 62 63 /* UDDRC */ 64 /* UDDRC Operating Mode Status Register */ 65 #define UDDRC_STAT 0x04 66 /* SDRAM is not in Self-refresh */ 67 #define UDDRC_STAT_SELFREF_TYPE_DIS SHIFT_U32(0, 4) 68 /* SDRAM is in Self-refresh, which was caused by PHY Master Request */ 69 #define UDDRC_STAT_SELFREF_TYPE_PHY SHIFT_U32(1, 4) 70 /* SDRAM is in Self-refresh, which was not caused solely under 71 * Automatic Self-refresh control 72 */ 73 #define UDDRC_STAT_SELFREF_TYPE_SW SHIFT_U32(2, 4) 74 /* SDRAM is in Self-refresh, which was caused by Automatic Self-refresh only */ 75 #define UDDRC_STAT_SELFREF_TYPE_AUTO SHIFT_U32(3, 4) 76 #define UDDRC_STAT_SELFREF_TYPE_MSK GENMASK_32(5, 4) 77 #define UDDRC_STAT_OPMODE_INIT 0 78 #define UDDRC_STAT_OPMODE_NORMAL 1 79 #define UDDRC_STAT_OPMODE_PWRDOWN 2 80 #define UDDRC_STAT_OPMODE_SELF_REFRESH 3 81 #define UDDRC_STAT_OPMODE_MSK GENMASK_32(2, 0) 82 83 /* UDDRC Low Power Control Register */ 84 #define UDDRC_PWRCTL 0x30 85 #define UDDRC_PWRCTL_SELFREF_EN BIT(0) /* Automatic self-refresh */ 86 #define UDDRC_PWRCTL_SELFREF_SW BIT(5) /* Software self-refresh */ 87 88 /* UDDRC DFI Miscellaneous Control Register */ 89 #define UDDRC_DFIMISC 0x1B0 90 /* PHY initialization complete enable signal */ 91 #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN BIT(0) 92 93 /* UDDRC Software Register Programming Control Enable */ 94 #define UDDRC_SWCTRL 0x320 95 /* Enable quasi-dynamic register programming outside reset */ 96 #define UDDRC_SWCTRL_SW_DONE BIT(0) 97 98 /* UDDRC Software Register Programming Control Status */ 99 #define UDDRC_SWSTAT 0x324 100 #define UDDRC_SWSTAT_SW_DONE_ACK BIT(0) /* Register programming done */ 101 102 /* UDDRC Port Status Register */ 103 #define UDDRC_PSTAT 0x3FC 104 /* Read + writes outstanding transactions on all ports */ 105 #define UDDRC_PSTAT_ALL_PORTS 0x1F001F 106 107 #define UDDRC_PCTRL_0 0x490 /* Port 0 Control Register */ 108 #define UDDRC_PCTRL_1 0x540 /* Port 1 Control Register */ 109 #define UDDRC_PCTRL_2 0x5F0 /* Port 2 Control Register */ 110 #define UDDRC_PCTRL_3 0x6A0 /* Port 3 Control Register */ 111 #define UDDRC_PCTRL_4 0x750 /* Port 4 Control Register */ 112 113 #endif /* __SAMA7_DDR_H__ */ 114