188544a9fSRemi Koman /* SPDX-License-Identifier: BSD-2-Clause */ 288544a9fSRemi Koman /* 39756bcc4SClement Faure * Copyright 2020-2022 NXP 488544a9fSRemi Koman */ 588544a9fSRemi Koman #ifndef __DRIVERS_IMX_MU_H 688544a9fSRemi Koman #define __DRIVERS_IMX_MU_H 788544a9fSRemi Koman 888544a9fSRemi Koman #include <tee_api_types.h> 988544a9fSRemi Koman #include <types_ext.h> 1088544a9fSRemi Koman #include <util.h> 1188544a9fSRemi Koman 129756bcc4SClement Faure #define IMX_MU_DATA_U32(mesg, idx) ((mesg)->data.u32[(idx)]) 139756bcc4SClement Faure #define IMX_MU_DATA_U16(mesg, idx) ((mesg)->data.u16[(idx)]) 149756bcc4SClement Faure #define IMX_MU_DATA_U8(mesg, idx) ((mesg)->data.u8[(idx)]) 159756bcc4SClement Faure 16753e6fe4SClement Faure #define IMX_MU_MSG_SIZE 17 179756bcc4SClement Faure #define IMX_MU_NB_CHANNEL 4 189756bcc4SClement Faure 1916e0d122SSahil Malhotra #if defined(CFG_MX8ULP) || defined(CFG_MX93) || defined(CFG_MX91) || \ 20*2157edb3SSahil Malhotra defined(CFG_MX95) || defined(CFG_MX943) 219756bcc4SClement Faure struct imx_mu_msg_header { 229756bcc4SClement Faure uint8_t version; 239756bcc4SClement Faure uint8_t size; 249756bcc4SClement Faure uint8_t command; 259756bcc4SClement Faure uint8_t tag; 269756bcc4SClement Faure }; 279756bcc4SClement Faure #elif defined(CFG_MX8QM) || defined(CFG_MX8QX) || defined(CFG_MX8DXL) 289756bcc4SClement Faure struct imx_mu_msg_header { 299756bcc4SClement Faure uint8_t version; 309756bcc4SClement Faure uint8_t size; 319756bcc4SClement Faure uint8_t tag; 329756bcc4SClement Faure uint8_t command; 339756bcc4SClement Faure }; 349756bcc4SClement Faure #else 359756bcc4SClement Faure #error "Platform not supported" 369756bcc4SClement Faure #endif 3788544a9fSRemi Koman 3888544a9fSRemi Koman /* 399756bcc4SClement Faure * i.MX MU message format 409756bcc4SClement Faure * Note: the header format differs depending of the platform. 4188544a9fSRemi Koman */ 429756bcc4SClement Faure struct imx_mu_msg { 439756bcc4SClement Faure struct imx_mu_msg_header header; 449756bcc4SClement Faure union { 459756bcc4SClement Faure uint32_t u32[IMX_MU_MSG_SIZE]; 469756bcc4SClement Faure uint16_t u16[IMX_MU_MSG_SIZE * 2]; 479756bcc4SClement Faure uint8_t u8[IMX_MU_MSG_SIZE * 4]; 489756bcc4SClement Faure } data; 499756bcc4SClement Faure }; 5088544a9fSRemi Koman 5188544a9fSRemi Koman /* 529756bcc4SClement Faure * Initialize the MU interface 5388544a9fSRemi Koman * 549756bcc4SClement Faure * @base: virtual base address of the MU controller 5588544a9fSRemi Koman */ 569756bcc4SClement Faure void imx_mu_init(vaddr_t base); 5788544a9fSRemi Koman 5888544a9fSRemi Koman /* 599756bcc4SClement Faure * Initiate a communication with the external controller. It sends a message 609756bcc4SClement Faure * and return the answer of the controller. 6188544a9fSRemi Koman * 629756bcc4SClement Faure * @base: virtual base address of the MU controller 639756bcc4SClement Faure * @[in/out]msg: message sent and received 649756bcc4SClement Faure * @wait_for_answer: true if an answer from the controller is expected, false 659756bcc4SClement Faure * otherwise 6688544a9fSRemi Koman */ 679756bcc4SClement Faure TEE_Result imx_mu_call(vaddr_t base, struct imx_mu_msg *msg, 689756bcc4SClement Faure bool wait_for_answer); 6988544a9fSRemi Koman #endif /* __DRIVERS_IMX_MU_H */ 70