xref: /optee_os/core/include/drivers/imx/dcp.h (revision fbe66cf83199aa6a2aca9f93384cf1ad9185a5f6)
193e678edSClement Faure /* SPDX-License-Identifier: BSD-2-Clause */
293e678edSClement Faure /*
393e678edSClement Faure  * Copyright 2020 NXP
493e678edSClement Faure  */
5*fbe66cf8SEtienne Carriere #ifndef __DRIVERS_IMX_DCP_H
6*fbe66cf8SEtienne Carriere #define __DRIVERS_IMX_DCP_H
793e678edSClement Faure 
893e678edSClement Faure #include <compiler.h>
993e678edSClement Faure #include <tee_api_types.h>
1093e678edSClement Faure #include <types_ext.h>
1193e678edSClement Faure #include <util.h>
1293e678edSClement Faure 
13b4bfc9a9SJens Wiklander #define DCP_SHA_BLOCK_SIZE    U(64)
14b4bfc9a9SJens Wiklander #define DCP_AES128_BLOCK_SIZE U(16)
1593e678edSClement Faure #define DCP_AES128_KEY_SIZE   DCP_AES128_BLOCK_SIZE
1693e678edSClement Faure #define DCP_AES128_IV_SIZE    DCP_AES128_BLOCK_SIZE
1793e678edSClement Faure 
1893e678edSClement Faure enum dcp_key_mode {
1993e678edSClement Faure 	DCP_SRAM0 = 0,
2093e678edSClement Faure 	DCP_SRAM1,
2193e678edSClement Faure 	DCP_SRAM2,
2293e678edSClement Faure 	DCP_SRAM3,
2393e678edSClement Faure 	DCP_PAYLOAD,
2493e678edSClement Faure 	DCP_OTP,
2593e678edSClement Faure };
2693e678edSClement Faure 
2793e678edSClement Faure enum dcp_aes_mode {
2893e678edSClement Faure 	DCP_ECB = 0,
2993e678edSClement Faure 	DCP_CBC,
3093e678edSClement Faure };
3193e678edSClement Faure 
3293e678edSClement Faure enum dcp_aes_op {
3393e678edSClement Faure 	DCP_ENCRYPT = 0,
3493e678edSClement Faure 	DCP_DECRYPT,
3593e678edSClement Faure };
3693e678edSClement Faure 
3793e678edSClement Faure enum dcp_hash_config {
3893e678edSClement Faure 	DCP_SHA1 = 0,
3993e678edSClement Faure 	DCP_SHA256,
4093e678edSClement Faure };
4193e678edSClement Faure 
4293e678edSClement Faure enum dcp_channel {
4393e678edSClement Faure 	DCP_CHANN0 = 0,
4493e678edSClement Faure 	DCP_CHANN1,
4593e678edSClement Faure 	DCP_CHANN2,
4693e678edSClement Faure 	DCP_CHANN3,
4793e678edSClement Faure 	DCP_NB_CHANNELS,
4893e678edSClement Faure };
4993e678edSClement Faure 
5093e678edSClement Faure /* DCP work packet descriptor is a hardware data structure */
5193e678edSClement Faure struct dcp_descriptor {
5293e678edSClement Faure 	uint32_t next;
5393e678edSClement Faure 	uint32_t ctrl0;
5493e678edSClement Faure 	uint32_t ctrl1;
5593e678edSClement Faure 	/* Source buffer physical address */
5693e678edSClement Faure 	uint32_t src_buffer;
5793e678edSClement Faure 	/* Destination buffer physical address */
5893e678edSClement Faure 	uint32_t dest_buffer;
5993e678edSClement Faure 	uint32_t buff_size;
6093e678edSClement Faure 	/* Payload buffer physical address */
6193e678edSClement Faure 	uint32_t payload;
6293e678edSClement Faure 	uint32_t status;
6393e678edSClement Faure };
6493e678edSClement Faure 
6593e678edSClement Faure struct dcp_align_buf {
6693e678edSClement Faure 	uint8_t *data;
6793e678edSClement Faure 	paddr_t paddr;
6893e678edSClement Faure 	size_t size;
6993e678edSClement Faure };
7093e678edSClement Faure 
7193e678edSClement Faure struct dcp_data {
7293e678edSClement Faure 	struct dcp_descriptor desc;
7393e678edSClement Faure 	enum dcp_channel channel;
7493e678edSClement Faure };
7593e678edSClement Faure 
7693e678edSClement Faure struct dcp_hash_data {
7793e678edSClement Faure 	struct dcp_data dcp_data;
7893e678edSClement Faure 	bool initialized;
7993e678edSClement Faure 	enum dcp_hash_config alg;
8093e678edSClement Faure 	struct dcp_align_buf ctx;
8193e678edSClement Faure 	size_t ctx_size;
8293e678edSClement Faure };
8393e678edSClement Faure 
8493e678edSClement Faure struct dcp_hashalg {
8593e678edSClement Faure 	unsigned int type;
8693e678edSClement Faure 	unsigned int size;
8793e678edSClement Faure };
8893e678edSClement Faure 
8993e678edSClement Faure struct dcp_cipher_data {
9093e678edSClement Faure 	struct dcp_data dcp_data;
9193e678edSClement Faure 	bool initialized;
9293e678edSClement Faure 	uint8_t iv[DCP_AES128_IV_SIZE];
9393e678edSClement Faure 	uint8_t key[DCP_AES128_KEY_SIZE];
9493e678edSClement Faure 	/* payload buffer holds the key and the iv */
9593e678edSClement Faure 	struct dcp_align_buf payload;
9693e678edSClement Faure 	size_t payload_size;
9793e678edSClement Faure };
9893e678edSClement Faure 
9993e678edSClement Faure struct dcp_cipher_init {
10093e678edSClement Faure 	enum dcp_aes_op op;
10193e678edSClement Faure 	enum dcp_aes_mode mode;
10293e678edSClement Faure 	enum dcp_key_mode key_mode;
10393e678edSClement Faure 	uint8_t *key;
10493e678edSClement Faure 	uint8_t *iv;
10593e678edSClement Faure };
10693e678edSClement Faure 
10793e678edSClement Faure /*
10893e678edSClement Faure  * Perform AES-CMAC operation
10993e678edSClement Faure  *
11093e678edSClement Faure  * @init       Cipher operation context
11193e678edSClement Faure  * @input      Input message
11293e678edSClement Faure  * @input_size Input message size
11393e678edSClement Faure  * @output     Output MAC
11493e678edSClement Faure  */
11593e678edSClement Faure TEE_Result dcp_cmac(struct dcp_cipher_init *init, uint8_t *input,
11693e678edSClement Faure 		    size_t input_size, uint8_t *output);
11793e678edSClement Faure 
11893e678edSClement Faure /*
11993e678edSClement Faure  * Store key in the SRAM
12093e678edSClement Faure  *
12193e678edSClement Faure  * @key    Buffer containing the key to store (128 bit)
12293e678edSClement Faure  * @index  Index of the key (0, 1, 2 or 3)
12393e678edSClement Faure  */
12493e678edSClement Faure TEE_Result dcp_store_key(uint32_t *key, unsigned int index);
12593e678edSClement Faure 
12693e678edSClement Faure /*
12793e678edSClement Faure  * Initialize AES-128 operation
12893e678edSClement Faure  *
12993e678edSClement Faure  * @data   Cipher operation context
13093e678edSClement Faure  * @init   Data for aesdata initialization
13193e678edSClement Faure  */
13293e678edSClement Faure TEE_Result dcp_cipher_do_init(struct dcp_cipher_data *data,
13393e678edSClement Faure 			      struct dcp_cipher_init *init);
13493e678edSClement Faure 
13593e678edSClement Faure /*
13693e678edSClement Faure  * Update AES-128 operation
13793e678edSClement Faure  *
13893e678edSClement Faure  * @data  Cipher operation context
13993e678edSClement Faure  * @src   Source data to encrypt/decrypt
14093e678edSClement Faure  * @dst   [out] Destination buffer
14193e678edSClement Faure  * @size  Size of source data in bytes, must be 16 bytes multiple
14293e678edSClement Faure  */
14393e678edSClement Faure TEE_Result dcp_cipher_do_update(struct dcp_cipher_data *data,
14493e678edSClement Faure 				const uint8_t *src, uint8_t *dst, size_t size);
14593e678edSClement Faure 
14693e678edSClement Faure /*
14793e678edSClement Faure  * Finalize AES-128 operation
14893e678edSClement Faure  *
14993e678edSClement Faure  * @data Cipher operation context
15093e678edSClement Faure  */
15193e678edSClement Faure void dcp_cipher_do_final(struct dcp_cipher_data *data);
15293e678edSClement Faure 
15393e678edSClement Faure /*
15493e678edSClement Faure  * Initialize hash operation
15593e678edSClement Faure  *
15693e678edSClement Faure  * @hashdata   Hash operation context
15793e678edSClement Faure  */
15893e678edSClement Faure TEE_Result dcp_sha_do_init(struct dcp_hash_data *hashdata);
15993e678edSClement Faure 
16093e678edSClement Faure /*
16193e678edSClement Faure  * Update hash operation
16293e678edSClement Faure  *
16393e678edSClement Faure  * @hashdata   Hash operation context
16493e678edSClement Faure  * @data       Buffer to hash
16593e678edSClement Faure  * @len        Size of the input buffer in bytes
16693e678edSClement Faure  */
16793e678edSClement Faure TEE_Result dcp_sha_do_update(struct dcp_hash_data *hashdata,
16893e678edSClement Faure 			     const uint8_t *data, size_t len);
16993e678edSClement Faure 
17093e678edSClement Faure /*
17193e678edSClement Faure  * Finalize the hash operation
17293e678edSClement Faure  *
17393e678edSClement Faure  * @hashdata      Hash operation context
17493e678edSClement Faure  * @digest        [out] Result of the hash operation
17593e678edSClement Faure  * @digest_size   Digest buffer size in bytes
17693e678edSClement Faure  */
17793e678edSClement Faure TEE_Result dcp_sha_do_final(struct dcp_hash_data *hashdata, uint8_t *digest,
17893e678edSClement Faure 			    size_t digest_size);
17993e678edSClement Faure 
1803fc5c287SClement Faure /*
1813fc5c287SClement Faure  * Disable the use of the DCP unique key (0xFE in the DCP key-select field).
1823fc5c287SClement Faure  */
1833fc5c287SClement Faure void dcp_disable_unique_key(void);
1843fc5c287SClement Faure 
18593e678edSClement Faure /* Initialize DCP */
18693e678edSClement Faure TEE_Result dcp_init(void);
18793e678edSClement Faure 
18893e678edSClement Faure #ifndef CFG_DT
dcp_vbase(vaddr_t * base __unused)18993e678edSClement Faure static inline TEE_Result dcp_vbase(vaddr_t *base __unused)
19093e678edSClement Faure {
19193e678edSClement Faure 	return TEE_ERROR_NOT_SUPPORTED;
19293e678edSClement Faure }
19393e678edSClement Faure #endif /* CFG_DT */
19493e678edSClement Faure 
195*fbe66cf8SEtienne Carriere #endif /* __DRIVERS_IMX_DCP_H */
196