xref: /optee_os/core/include/drivers/clk_qcom.h (revision ed9b177e198fdd4423c69ace34e6d362717d25a1)
18444b75fSSumit Garg /* SPDX-License-Identifier: BSD-2-Clause */
28444b75fSSumit Garg /*
38444b75fSSumit Garg  * Copyright (c) 2025, Linaro Limited
48444b75fSSumit Garg  * Copyright (c) 2026, Qualcomm Technologies, Inc. and/or its subsidiaries.
58444b75fSSumit Garg  */
68444b75fSSumit Garg 
78444b75fSSumit Garg #ifndef _CLK_QCOM_H_
88444b75fSSumit Garg #define _CLK_QCOM_H_
98444b75fSSumit Garg 
108444b75fSSumit Garg #include <stdint.h>
118444b75fSSumit Garg #include <tee_api_types.h>
128444b75fSSumit Garg 
13*ed9b177eSJorge Ramirez-Ortiz #define REG_POLL_TIMEOUT(_addr, _timeout_us, _delay_us, _retp, _match)	\
14*ed9b177eSJorge Ramirez-Ortiz 	do {								\
15*ed9b177eSJorge Ramirez-Ortiz 		uint32_t __val;						\
16*ed9b177eSJorge Ramirez-Ortiz 		int __rc;						\
17*ed9b177eSJorge Ramirez-Ortiz 									\
18*ed9b177eSJorge Ramirez-Ortiz 		__rc = IO_READ32_POLL_TIMEOUT(_addr, __val,		\
19*ed9b177eSJorge Ramirez-Ortiz 					     (_match)(__val),		\
20*ed9b177eSJorge Ramirez-Ortiz 					     _delay_us, _timeout_us);	\
21*ed9b177eSJorge Ramirez-Ortiz 		*(_retp) = __rc ? -1 : 0;				\
22*ed9b177eSJorge Ramirez-Ortiz 	} while (0)
23*ed9b177eSJorge Ramirez-Ortiz 
248444b75fSSumit Garg enum qcom_clk_group {
258444b75fSSumit Garg 	QCOM_CLKS_WPSS,
26594035b1SJorge Ramirez-Ortiz 	QCOM_CLKS_TURING,
273fff682dSJorge Ramirez-Ortiz 	QCOM_CLKS_LPASS,
288444b75fSSumit Garg 	QCOM_CLKS_MAX,
298444b75fSSumit Garg };
308444b75fSSumit Garg 
318444b75fSSumit Garg TEE_Result qcom_clock_enable(enum qcom_clk_group group);
32*ed9b177eSJorge Ramirez-Ortiz TEE_Result qcom_clock_enable_cbc(vaddr_t cbcr);
33*ed9b177eSJorge Ramirez-Ortiz TEE_Result qcom_clock_enable_pas(enum qcom_clk_group group);
348444b75fSSumit Garg 
358444b75fSSumit Garg #endif /* _CLK_QCOM_H_ */
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