1 /* SPDX-License-Identifier: BSD-2-Clause */ 2 /* 3 * Copyright (c) 2021 Western Digital Corporation or its affiliates. 4 * Copyright (c) 2022 Ventana Micro Systems Inc. 5 * Copyright (c) 2025 Beijing Institute of Open Source Chip (BOSC) 6 * 7 * Authors: 8 * Anup Patel <anup.patel@wdc.com> 9 * Huang Borong <huangborong@bosc.ac.cn> 10 */ 11 12 #ifndef __DRIVERS_APLIC_PRIV_H 13 #define __DRIVERS_APLIC_PRIV_H 14 15 #include <io.h> 16 #include <kernel/interrupt.h> 17 #include <types_ext.h> 18 #include <util.h> 19 20 #define APLIC_MAX_SOURCE 1024 21 #define APLIC_COMPATIBLE "riscv,aplic" 22 23 /* APLIC registers */ 24 #define APLIC_DOMAINCFG 0x0000 25 #define APLIC_DOMAINCFG_RDONLY 0x80000000 26 #define APLIC_DOMAINCFG_IE BIT(8) 27 #define APLIC_DOMAINCFG_DM BIT(2) 28 #define APLIC_DOMAINCFG_BE BIT(0) 29 30 #define APLIC_SOURCECFG_BASE 0x0004 /* sourcecfg[1] */ 31 #define APLIC_SOURCECFG_D BIT(10) 32 #define APLIC_SOURCECFG_CHILDIDX_MASK GENMASK_32(9, 0) 33 #define APLIC_SOURCECFG_SM_MASK GENMASK_32(2, 0) 34 #define APLIC_SOURCECFG_SM_INACTIVE 0x0 35 #define APLIC_SOURCECFG_SM_DETACHED 0x1 36 #define APLIC_SOURCECFG_SM_EDGE_RISE 0x4 37 #define APLIC_SOURCECFG_SM_EDGE_FALL 0x5 38 #define APLIC_SOURCECFG_SM_LEVEL_HIGH 0x6 39 #define APLIC_SOURCECFG_SM_LEVEL_LOW 0x7 40 41 #define APLIC_MMSIADDRCFG 0x1BC0 42 #define APLIC_MMSIADDRCFGH 0x1BC4 43 #define APLIC_SMSIADDRCFG 0x1BC8 44 #define APLIC_SMSIADDRCFGH 0x1BCC 45 46 #define APLIC_SETIP_BASE 0x1C00 47 #define APLIC_SETIPNUM 0x1CDC 48 #define APLIC_IN_CLRIP_BASE 0x1D00 49 #define APLIC_CLRIPNUM 0x1DDC 50 #define APLIC_SETIE_BASE 0x1E00 51 #define APLIC_SETIENUM 0x1EDC 52 #define APLIC_CLRIE_BASE 0x1F00 53 #define APLIC_CLRIENUM 0x1FDC 54 #define APLIC_SETIPNUM_LE 0x2000 55 #define APLIC_SETIPNUM_BE 0x2004 56 #define APLIC_GENMSI 0x3000 57 58 #define APLIC_TARGET_BASE 0x3004 /* target[1] */ 59 #define APLIC_TARGET_HART_IDX_SHIFT 18 60 #define APLIC_TARGET_HART_IDX_MASK GENMASK_32(31, 18) 61 #define APLIC_TARGET_GUEST_IDX_SHIFT 12 62 #define APLIC_TARGET_GUEST_IDX_MASK GENMASK_32(17, 12) 63 #define APLIC_TARGET_EIID_MASK GENMASK_32(10, 0) 64 #define APLIC_TARGET_IPRIO_MASK GENMASK_32(7, 0) 65 66 /* 67 * struct aplic_data - APLIC interrupt controller 68 * @aplic_base: Base address of the APLIC 69 * @size: Size of the APLIC in bytes 70 * @targets_mmode: Indicates if APLIC targets Machine mode (true) or not (false) 71 * @num_idc: Number of interrupt delivery control structures supported by APLIC 72 * @num_source: Number of interrupt sources supported by APLIC 73 * @chip: Interrupt controller base class 74 */ 75 struct aplic_data { 76 vaddr_t aplic_base; 77 uint32_t size; 78 bool targets_mmode; 79 uint32_t num_idc; 80 uint32_t num_source; 81 struct itr_chip chip; 82 }; 83 84 static inline void aplic_enable_interrupt(struct aplic_data *aplic, 85 uint32_t source) 86 { 87 io_write32(aplic->aplic_base + APLIC_SETIENUM, source); 88 } 89 90 static inline void aplic_disable_interrupt(struct aplic_data *aplic, 91 uint32_t source) 92 { 93 io_write32(aplic->aplic_base + APLIC_CLRIENUM, source); 94 } 95 96 static inline void aplic_set_pending(struct aplic_data *aplic, uint32_t source) 97 { 98 io_write32(aplic->aplic_base + APLIC_SETIPNUM, source); 99 } 100 101 static inline void aplic_clear_pending(struct aplic_data *aplic, 102 uint32_t source) 103 { 104 io_write32(aplic->aplic_base + APLIC_CLRIPNUM, source); 105 } 106 107 static inline bool aplic_is_bad_it(struct aplic_data *aplic, size_t it) 108 { 109 return !it || it > aplic->num_source; 110 } 111 112 TEE_Result aplic_init_from_device_tree(struct aplic_data *aplic); 113 TEE_Result aplic_set_source_mode(struct aplic_data *aplic, uint32_t source, 114 uint32_t type); 115 116 #endif /* __DRIVERS_APLIC_PRIV_H */ 117