1*7f2d4e10SAkshay Belsare /* SPDX-License-Identifier: BSD-2-Clause */ 2*7f2d4e10SAkshay Belsare /* 3*7f2d4e10SAkshay Belsare * Copyright (c) 2024-2026, Advanced Micro Devices, Inc. All rights reserved. 4*7f2d4e10SAkshay Belsare * 5*7f2d4e10SAkshay Belsare */ 6*7f2d4e10SAkshay Belsare 7*7f2d4e10SAkshay Belsare #ifndef __ASU_SHAREDMEM_H_ 8*7f2d4e10SAkshay Belsare #define __ASU_SHAREDMEM_H_ 9*7f2d4e10SAkshay Belsare 10*7f2d4e10SAkshay Belsare #include <stdint.h> 11*7f2d4e10SAkshay Belsare #include <util.h> 12*7f2d4e10SAkshay Belsare 13*7f2d4e10SAkshay Belsare #define ASU_MAX_BUFFERS 8U 14*7f2d4e10SAkshay Belsare #define ASU_CHANNEL_RESERVED_MEM 1188U 15*7f2d4e10SAkshay Belsare #define ASU_COMMAND_IS_PRESENT 0x1U 16*7f2d4e10SAkshay Belsare #define ASU_RESPONSE_IS_PRESENT 0x1U 17*7f2d4e10SAkshay Belsare #define ASU_RESPONSE_STATUS_INDEX 0U 18*7f2d4e10SAkshay Belsare #define ASU_RESPONSE_BUFF_ADDR_INDEX 1U 19*7f2d4e10SAkshay Belsare #define ASU_COMMAND_ID_MASK 0x0000003FU 20*7f2d4e10SAkshay Belsare #define ASU_UNIQUE_REQ_ID_MASK 0x00000FC0U 21*7f2d4e10SAkshay Belsare #define ASU_UNIQUE_REQ_ID_SHIFT 6U 22*7f2d4e10SAkshay Belsare #define ASU_UNIQUE_ID_MAX SHIFT_U32(ASU_MAX_BUFFERS, 1U) 23*7f2d4e10SAkshay Belsare #define ASU_MODULE_ID_MASK 0x0003F000U 24*7f2d4e10SAkshay Belsare #define ASU_MODULE_ID_SHIFT 12U 25*7f2d4e10SAkshay Belsare #define ASU_COMMAND_LENGTH_SHIFT 18U 26*7f2d4e10SAkshay Belsare #define ASU_COMMAND_REQ_ARGS 22U 27*7f2d4e10SAkshay Belsare #define ASU_COMMAND_RESP_ARGS 17U 28*7f2d4e10SAkshay Belsare #define ASU_RTCA_BASEADDR 0xEBE40000U 29*7f2d4e10SAkshay Belsare #define ASU_RTCA_COMM_CHANNEL_INFO_ADDR (ASU_RTCA_BASEADDR + 0x10U) 30*7f2d4e10SAkshay Belsare #define ASU_RTCA_CHANNEL_BASE_OFFSET 0x18U 31*7f2d4e10SAkshay Belsare #define ASU_RTCA_CHANNEL_INFO_LEN 0x8U 32*7f2d4e10SAkshay Belsare #define ASU_MAX_IPI_CHANNELS 8U 33*7f2d4e10SAkshay Belsare #define ASU_CHANNEL_MEMORY_OFFSET 0x1000U 34*7f2d4e10SAkshay Belsare #define ASU_CHANNEL_MEMORY_BASEADDR (ASU_RTCA_BASEADDR + \ 35*7f2d4e10SAkshay Belsare ASU_CHANNEL_MEMORY_OFFSET) 36*7f2d4e10SAkshay Belsare 37*7f2d4e10SAkshay Belsare struct asu_req_buf { 38*7f2d4e10SAkshay Belsare uint32_t header; 39*7f2d4e10SAkshay Belsare uint32_t arg[ASU_COMMAND_REQ_ARGS]; 40*7f2d4e10SAkshay Belsare uint32_t reserved; 41*7f2d4e10SAkshay Belsare }; 42*7f2d4e10SAkshay Belsare 43*7f2d4e10SAkshay Belsare struct asu_resp_buf { 44*7f2d4e10SAkshay Belsare uint32_t header; 45*7f2d4e10SAkshay Belsare uint32_t arg[ASU_COMMAND_RESP_ARGS]; 46*7f2d4e10SAkshay Belsare uint32_t additionalstatus; 47*7f2d4e10SAkshay Belsare uint32_t reserved; 48*7f2d4e10SAkshay Belsare }; 49*7f2d4e10SAkshay Belsare 50*7f2d4e10SAkshay Belsare struct asu_channel_queue_buf { 51*7f2d4e10SAkshay Belsare uint8_t reqbufstatus; 52*7f2d4e10SAkshay Belsare uint8_t respbufstatus; 53*7f2d4e10SAkshay Belsare uint16_t reserved; 54*7f2d4e10SAkshay Belsare struct asu_req_buf req; 55*7f2d4e10SAkshay Belsare struct asu_resp_buf resp; 56*7f2d4e10SAkshay Belsare }; 57*7f2d4e10SAkshay Belsare 58*7f2d4e10SAkshay Belsare struct asu_channel_queue { 59*7f2d4e10SAkshay Belsare bool cmd_is_present; 60*7f2d4e10SAkshay Belsare uint32_t req_sent; 61*7f2d4e10SAkshay Belsare uint32_t req_served; 62*7f2d4e10SAkshay Belsare struct asu_channel_queue_buf queue_bufs[ASU_MAX_BUFFERS]; 63*7f2d4e10SAkshay Belsare }; 64*7f2d4e10SAkshay Belsare 65*7f2d4e10SAkshay Belsare struct asu_channel_memory { 66*7f2d4e10SAkshay Belsare uint32_t version; 67*7f2d4e10SAkshay Belsare uint8_t reserved[ASU_CHANNEL_RESERVED_MEM]; 68*7f2d4e10SAkshay Belsare struct asu_channel_queue p0_chnl_q; 69*7f2d4e10SAkshay Belsare struct asu_channel_queue p1_chnl_q; 70*7f2d4e10SAkshay Belsare }; 71*7f2d4e10SAkshay Belsare 72*7f2d4e10SAkshay Belsare #endif /* __ASU_SHAREDMEM_H_ */ 73