xref: /optee_os/core/drivers/stpmic1.c (revision f7e289510543e04cd68f484fec816a5b0af726bc)
1c7cf2933SEtienne Carriere // SPDX-License-Identifier: BSD-3-Clause
2c7cf2933SEtienne Carriere /*
3c7cf2933SEtienne Carriere  * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
4c7cf2933SEtienne Carriere  */
5c7cf2933SEtienne Carriere 
6c7cf2933SEtienne Carriere #include <assert.h>
7c7cf2933SEtienne Carriere #include <drivers/stpmic1.h>
8c7cf2933SEtienne Carriere #include <kernel/panic.h>
9c7cf2933SEtienne Carriere #include <platform_config.h>
10c7cf2933SEtienne Carriere #include <stdint.h>
11c7cf2933SEtienne Carriere #include <string.h>
12c7cf2933SEtienne Carriere #include <trace.h>
13c7cf2933SEtienne Carriere 
14c7cf2933SEtienne Carriere struct regul_struct {
15c7cf2933SEtienne Carriere 	const char *dt_node_name;
16c7cf2933SEtienne Carriere 	const uint16_t *voltage_table;
17c7cf2933SEtienne Carriere 	uint8_t voltage_table_size;
18c7cf2933SEtienne Carriere 	uint8_t control_reg;
19c7cf2933SEtienne Carriere 	uint8_t low_power_reg;
20c7cf2933SEtienne Carriere 	uint8_t pull_down_reg;
21c7cf2933SEtienne Carriere 	uint8_t pull_down_pos;
22c7cf2933SEtienne Carriere 	uint8_t mask_reset_reg;
23c7cf2933SEtienne Carriere 	uint8_t mask_reset_pos;
24c7cf2933SEtienne Carriere };
25c7cf2933SEtienne Carriere 
26c7cf2933SEtienne Carriere static struct i2c_handle_s *pmic_i2c_handle;
27c7cf2933SEtienne Carriere static uint16_t pmic_i2c_addr;
28c7cf2933SEtienne Carriere 
29c7cf2933SEtienne Carriere /* Voltage tables in mV */
30c7cf2933SEtienne Carriere static const uint16_t buck1_voltage_table[] = {
31c7cf2933SEtienne Carriere 	725,
32c7cf2933SEtienne Carriere 	725,
33c7cf2933SEtienne Carriere 	725,
34c7cf2933SEtienne Carriere 	725,
35c7cf2933SEtienne Carriere 	725,
36c7cf2933SEtienne Carriere 	725,
37c7cf2933SEtienne Carriere 	750,
38c7cf2933SEtienne Carriere 	775,
39c7cf2933SEtienne Carriere 	800,
40c7cf2933SEtienne Carriere 	825,
41c7cf2933SEtienne Carriere 	850,
42c7cf2933SEtienne Carriere 	875,
43c7cf2933SEtienne Carriere 	900,
44c7cf2933SEtienne Carriere 	925,
45c7cf2933SEtienne Carriere 	950,
46c7cf2933SEtienne Carriere 	975,
47c7cf2933SEtienne Carriere 	1000,
48c7cf2933SEtienne Carriere 	1025,
49c7cf2933SEtienne Carriere 	1050,
50c7cf2933SEtienne Carriere 	1075,
51c7cf2933SEtienne Carriere 	1100,
52c7cf2933SEtienne Carriere 	1125,
53c7cf2933SEtienne Carriere 	1150,
54c7cf2933SEtienne Carriere 	1175,
55c7cf2933SEtienne Carriere 	1200,
56c7cf2933SEtienne Carriere 	1225,
57c7cf2933SEtienne Carriere 	1250,
58c7cf2933SEtienne Carriere 	1275,
59c7cf2933SEtienne Carriere 	1300,
60c7cf2933SEtienne Carriere 	1325,
61c7cf2933SEtienne Carriere 	1350,
62c7cf2933SEtienne Carriere 	1375,
63c7cf2933SEtienne Carriere 	1400,
64c7cf2933SEtienne Carriere 	1425,
65c7cf2933SEtienne Carriere 	1450,
66c7cf2933SEtienne Carriere 	1475,
67c7cf2933SEtienne Carriere 	1500,
68c7cf2933SEtienne Carriere 	1500,
69c7cf2933SEtienne Carriere 	1500,
70c7cf2933SEtienne Carriere 	1500,
71c7cf2933SEtienne Carriere 	1500,
72c7cf2933SEtienne Carriere 	1500,
73c7cf2933SEtienne Carriere 	1500,
74c7cf2933SEtienne Carriere 	1500,
75c7cf2933SEtienne Carriere 	1500,
76c7cf2933SEtienne Carriere 	1500,
77c7cf2933SEtienne Carriere 	1500,
78c7cf2933SEtienne Carriere 	1500,
79c7cf2933SEtienne Carriere 	1500,
80c7cf2933SEtienne Carriere 	1500,
81c7cf2933SEtienne Carriere 	1500,
82c7cf2933SEtienne Carriere 	1500,
83c7cf2933SEtienne Carriere 	1500,
84c7cf2933SEtienne Carriere 	1500,
85c7cf2933SEtienne Carriere 	1500,
86c7cf2933SEtienne Carriere 	1500,
87c7cf2933SEtienne Carriere 	1500,
88c7cf2933SEtienne Carriere 	1500,
89c7cf2933SEtienne Carriere 	1500,
90c7cf2933SEtienne Carriere 	1500,
91c7cf2933SEtienne Carriere 	1500,
92c7cf2933SEtienne Carriere 	1500,
93c7cf2933SEtienne Carriere 	1500,
94c7cf2933SEtienne Carriere 	1500,
95c7cf2933SEtienne Carriere };
96c7cf2933SEtienne Carriere 
97c7cf2933SEtienne Carriere static const uint16_t buck2_voltage_table[] = {
98c7cf2933SEtienne Carriere 	1000,
99c7cf2933SEtienne Carriere 	1000,
100c7cf2933SEtienne Carriere 	1000,
101c7cf2933SEtienne Carriere 	1000,
102c7cf2933SEtienne Carriere 	1000,
103c7cf2933SEtienne Carriere 	1000,
104c7cf2933SEtienne Carriere 	1000,
105c7cf2933SEtienne Carriere 	1000,
106c7cf2933SEtienne Carriere 	1000,
107c7cf2933SEtienne Carriere 	1000,
108c7cf2933SEtienne Carriere 	1000,
109c7cf2933SEtienne Carriere 	1000,
110c7cf2933SEtienne Carriere 	1000,
111c7cf2933SEtienne Carriere 	1000,
112c7cf2933SEtienne Carriere 	1000,
113c7cf2933SEtienne Carriere 	1000,
114c7cf2933SEtienne Carriere 	1000,
115c7cf2933SEtienne Carriere 	1000,
116c7cf2933SEtienne Carriere 	1050,
117c7cf2933SEtienne Carriere 	1050,
118c7cf2933SEtienne Carriere 	1100,
119c7cf2933SEtienne Carriere 	1100,
120c7cf2933SEtienne Carriere 	1150,
121c7cf2933SEtienne Carriere 	1150,
122c7cf2933SEtienne Carriere 	1200,
123c7cf2933SEtienne Carriere 	1200,
124c7cf2933SEtienne Carriere 	1250,
125c7cf2933SEtienne Carriere 	1250,
126c7cf2933SEtienne Carriere 	1300,
127c7cf2933SEtienne Carriere 	1300,
128c7cf2933SEtienne Carriere 	1350,
129c7cf2933SEtienne Carriere 	1350,
130c7cf2933SEtienne Carriere 	1400,
131c7cf2933SEtienne Carriere 	1400,
132c7cf2933SEtienne Carriere 	1450,
133c7cf2933SEtienne Carriere 	1450,
134c7cf2933SEtienne Carriere 	1500,
135c7cf2933SEtienne Carriere };
136c7cf2933SEtienne Carriere 
137c7cf2933SEtienne Carriere static const uint16_t buck3_voltage_table[] = {
138c7cf2933SEtienne Carriere 	1000,
139c7cf2933SEtienne Carriere 	1000,
140c7cf2933SEtienne Carriere 	1000,
141c7cf2933SEtienne Carriere 	1000,
142c7cf2933SEtienne Carriere 	1000,
143c7cf2933SEtienne Carriere 	1000,
144c7cf2933SEtienne Carriere 	1000,
145c7cf2933SEtienne Carriere 	1000,
146c7cf2933SEtienne Carriere 	1000,
147c7cf2933SEtienne Carriere 	1000,
148c7cf2933SEtienne Carriere 	1000,
149c7cf2933SEtienne Carriere 	1000,
150c7cf2933SEtienne Carriere 	1000,
151c7cf2933SEtienne Carriere 	1000,
152c7cf2933SEtienne Carriere 	1000,
153c7cf2933SEtienne Carriere 	1000,
154c7cf2933SEtienne Carriere 	1000,
155c7cf2933SEtienne Carriere 	1000,
156c7cf2933SEtienne Carriere 	1000,
157c7cf2933SEtienne Carriere 	1000,
158c7cf2933SEtienne Carriere 	1100,
159c7cf2933SEtienne Carriere 	1100,
160c7cf2933SEtienne Carriere 	1100,
161c7cf2933SEtienne Carriere 	1100,
162c7cf2933SEtienne Carriere 	1200,
163c7cf2933SEtienne Carriere 	1200,
164c7cf2933SEtienne Carriere 	1200,
165c7cf2933SEtienne Carriere 	1200,
166c7cf2933SEtienne Carriere 	1300,
167c7cf2933SEtienne Carriere 	1300,
168c7cf2933SEtienne Carriere 	1300,
169c7cf2933SEtienne Carriere 	1300,
170c7cf2933SEtienne Carriere 	1400,
171c7cf2933SEtienne Carriere 	1400,
172c7cf2933SEtienne Carriere 	1400,
173c7cf2933SEtienne Carriere 	1400,
174c7cf2933SEtienne Carriere 	1500,
175c7cf2933SEtienne Carriere 	1600,
176c7cf2933SEtienne Carriere 	1700,
177c7cf2933SEtienne Carriere 	1800,
178c7cf2933SEtienne Carriere 	1900,
179c7cf2933SEtienne Carriere 	2000,
180c7cf2933SEtienne Carriere 	2100,
181c7cf2933SEtienne Carriere 	2200,
182c7cf2933SEtienne Carriere 	2300,
183c7cf2933SEtienne Carriere 	2400,
184c7cf2933SEtienne Carriere 	2500,
185c7cf2933SEtienne Carriere 	2600,
186c7cf2933SEtienne Carriere 	2700,
187c7cf2933SEtienne Carriere 	2800,
188c7cf2933SEtienne Carriere 	2900,
189c7cf2933SEtienne Carriere 	3000,
190c7cf2933SEtienne Carriere 	3100,
191c7cf2933SEtienne Carriere 	3200,
192c7cf2933SEtienne Carriere 	3300,
193c7cf2933SEtienne Carriere 	3400,
194c7cf2933SEtienne Carriere };
195c7cf2933SEtienne Carriere 
196c7cf2933SEtienne Carriere static const uint16_t buck4_voltage_table[] = {
197c7cf2933SEtienne Carriere 	600,
198c7cf2933SEtienne Carriere 	625,
199c7cf2933SEtienne Carriere 	650,
200c7cf2933SEtienne Carriere 	675,
201c7cf2933SEtienne Carriere 	700,
202c7cf2933SEtienne Carriere 	725,
203c7cf2933SEtienne Carriere 	750,
204c7cf2933SEtienne Carriere 	775,
205c7cf2933SEtienne Carriere 	800,
206c7cf2933SEtienne Carriere 	825,
207c7cf2933SEtienne Carriere 	850,
208c7cf2933SEtienne Carriere 	875,
209c7cf2933SEtienne Carriere 	900,
210c7cf2933SEtienne Carriere 	925,
211c7cf2933SEtienne Carriere 	950,
212c7cf2933SEtienne Carriere 	975,
213c7cf2933SEtienne Carriere 	1000,
214c7cf2933SEtienne Carriere 	1025,
215c7cf2933SEtienne Carriere 	1050,
216c7cf2933SEtienne Carriere 	1075,
217c7cf2933SEtienne Carriere 	1100,
218c7cf2933SEtienne Carriere 	1125,
219c7cf2933SEtienne Carriere 	1150,
220c7cf2933SEtienne Carriere 	1175,
221c7cf2933SEtienne Carriere 	1200,
222c7cf2933SEtienne Carriere 	1225,
223c7cf2933SEtienne Carriere 	1250,
224c7cf2933SEtienne Carriere 	1275,
225c7cf2933SEtienne Carriere 	1300,
226c7cf2933SEtienne Carriere 	1300,
227c7cf2933SEtienne Carriere 	1350,
228c7cf2933SEtienne Carriere 	1350,
229c7cf2933SEtienne Carriere 	1400,
230c7cf2933SEtienne Carriere 	1400,
231c7cf2933SEtienne Carriere 	1450,
232c7cf2933SEtienne Carriere 	1450,
233c7cf2933SEtienne Carriere 	1500,
234c7cf2933SEtienne Carriere 	1600,
235c7cf2933SEtienne Carriere 	1700,
236c7cf2933SEtienne Carriere 	1800,
237c7cf2933SEtienne Carriere 	1900,
238c7cf2933SEtienne Carriere 	2000,
239c7cf2933SEtienne Carriere 	2100,
240c7cf2933SEtienne Carriere 	2200,
241c7cf2933SEtienne Carriere 	2300,
242c7cf2933SEtienne Carriere 	2400,
243c7cf2933SEtienne Carriere 	2500,
244c7cf2933SEtienne Carriere 	2600,
245c7cf2933SEtienne Carriere 	2700,
246c7cf2933SEtienne Carriere 	2800,
247c7cf2933SEtienne Carriere 	2900,
248c7cf2933SEtienne Carriere 	3000,
249c7cf2933SEtienne Carriere 	3100,
250c7cf2933SEtienne Carriere 	3200,
251c7cf2933SEtienne Carriere 	3300,
252c7cf2933SEtienne Carriere 	3400,
253c7cf2933SEtienne Carriere 	3500,
254c7cf2933SEtienne Carriere 	3600,
255c7cf2933SEtienne Carriere 	3700,
256c7cf2933SEtienne Carriere 	3800,
257c7cf2933SEtienne Carriere 	3900,
258c7cf2933SEtienne Carriere };
259c7cf2933SEtienne Carriere 
260c7cf2933SEtienne Carriere static const uint16_t ldo1_voltage_table[] = {
261c7cf2933SEtienne Carriere 	1700,
262c7cf2933SEtienne Carriere 	1700,
263c7cf2933SEtienne Carriere 	1700,
264c7cf2933SEtienne Carriere 	1700,
265c7cf2933SEtienne Carriere 	1700,
266c7cf2933SEtienne Carriere 	1700,
267c7cf2933SEtienne Carriere 	1700,
268c7cf2933SEtienne Carriere 	1700,
269c7cf2933SEtienne Carriere 	1700,
270c7cf2933SEtienne Carriere 	1800,
271c7cf2933SEtienne Carriere 	1900,
272c7cf2933SEtienne Carriere 	2000,
273c7cf2933SEtienne Carriere 	2100,
274c7cf2933SEtienne Carriere 	2200,
275c7cf2933SEtienne Carriere 	2300,
276c7cf2933SEtienne Carriere 	2400,
277c7cf2933SEtienne Carriere 	2500,
278c7cf2933SEtienne Carriere 	2600,
279c7cf2933SEtienne Carriere 	2700,
280c7cf2933SEtienne Carriere 	2800,
281c7cf2933SEtienne Carriere 	2900,
282c7cf2933SEtienne Carriere 	3000,
283c7cf2933SEtienne Carriere 	3100,
284c7cf2933SEtienne Carriere 	3200,
285c7cf2933SEtienne Carriere 	3300,
286c7cf2933SEtienne Carriere };
287c7cf2933SEtienne Carriere 
288c7cf2933SEtienne Carriere static const uint16_t ldo2_voltage_table[] = {
289c7cf2933SEtienne Carriere 	1700,
290c7cf2933SEtienne Carriere 	1700,
291c7cf2933SEtienne Carriere 	1700,
292c7cf2933SEtienne Carriere 	1700,
293c7cf2933SEtienne Carriere 	1700,
294c7cf2933SEtienne Carriere 	1700,
295c7cf2933SEtienne Carriere 	1700,
296c7cf2933SEtienne Carriere 	1700,
297c7cf2933SEtienne Carriere 	1700,
298c7cf2933SEtienne Carriere 	1800,
299c7cf2933SEtienne Carriere 	1900,
300c7cf2933SEtienne Carriere 	2000,
301c7cf2933SEtienne Carriere 	2100,
302c7cf2933SEtienne Carriere 	2200,
303c7cf2933SEtienne Carriere 	2300,
304c7cf2933SEtienne Carriere 	2400,
305c7cf2933SEtienne Carriere 	2500,
306c7cf2933SEtienne Carriere 	2600,
307c7cf2933SEtienne Carriere 	2700,
308c7cf2933SEtienne Carriere 	2800,
309c7cf2933SEtienne Carriere 	2900,
310c7cf2933SEtienne Carriere 	3000,
311c7cf2933SEtienne Carriere 	3100,
312c7cf2933SEtienne Carriere 	3200,
313c7cf2933SEtienne Carriere 	3300,
314c7cf2933SEtienne Carriere };
315c7cf2933SEtienne Carriere 
316c7cf2933SEtienne Carriere static const uint16_t ldo3_voltage_table[] = {
317c7cf2933SEtienne Carriere 	1700,
318c7cf2933SEtienne Carriere 	1700,
319c7cf2933SEtienne Carriere 	1700,
320c7cf2933SEtienne Carriere 	1700,
321c7cf2933SEtienne Carriere 	1700,
322c7cf2933SEtienne Carriere 	1700,
323c7cf2933SEtienne Carriere 	1700,
324c7cf2933SEtienne Carriere 	1700,
325c7cf2933SEtienne Carriere 	1700,
326c7cf2933SEtienne Carriere 	1800,
327c7cf2933SEtienne Carriere 	1900,
328c7cf2933SEtienne Carriere 	2000,
329c7cf2933SEtienne Carriere 	2100,
330c7cf2933SEtienne Carriere 	2200,
331c7cf2933SEtienne Carriere 	2300,
332c7cf2933SEtienne Carriere 	2400,
333c7cf2933SEtienne Carriere 	2500,
334c7cf2933SEtienne Carriere 	2600,
335c7cf2933SEtienne Carriere 	2700,
336c7cf2933SEtienne Carriere 	2800,
337c7cf2933SEtienne Carriere 	2900,
338c7cf2933SEtienne Carriere 	3000,
339c7cf2933SEtienne Carriere 	3100,
340c7cf2933SEtienne Carriere 	3200,
341c7cf2933SEtienne Carriere 	3300,
342c7cf2933SEtienne Carriere 	3300,
343c7cf2933SEtienne Carriere 	3300,
344c7cf2933SEtienne Carriere 	3300,
345c7cf2933SEtienne Carriere 	3300,
346c7cf2933SEtienne Carriere 	3300,
347c7cf2933SEtienne Carriere 	3300,
348*f7e28951SEtienne Carriere 	500,	/* VOUT2/2 (Sink/source mode) */
349c7cf2933SEtienne Carriere 	0xFFFF, /* VREFDDR */
350c7cf2933SEtienne Carriere };
351c7cf2933SEtienne Carriere 
352c7cf2933SEtienne Carriere static const uint16_t ldo5_voltage_table[] = {
353c7cf2933SEtienne Carriere 	1700,
354c7cf2933SEtienne Carriere 	1700,
355c7cf2933SEtienne Carriere 	1700,
356c7cf2933SEtienne Carriere 	1700,
357c7cf2933SEtienne Carriere 	1700,
358c7cf2933SEtienne Carriere 	1700,
359c7cf2933SEtienne Carriere 	1700,
360c7cf2933SEtienne Carriere 	1700,
361c7cf2933SEtienne Carriere 	1700,
362c7cf2933SEtienne Carriere 	1800,
363c7cf2933SEtienne Carriere 	1900,
364c7cf2933SEtienne Carriere 	2000,
365c7cf2933SEtienne Carriere 	2100,
366c7cf2933SEtienne Carriere 	2200,
367c7cf2933SEtienne Carriere 	2300,
368c7cf2933SEtienne Carriere 	2400,
369c7cf2933SEtienne Carriere 	2500,
370c7cf2933SEtienne Carriere 	2600,
371c7cf2933SEtienne Carriere 	2700,
372c7cf2933SEtienne Carriere 	2800,
373c7cf2933SEtienne Carriere 	2900,
374c7cf2933SEtienne Carriere 	3000,
375c7cf2933SEtienne Carriere 	3100,
376c7cf2933SEtienne Carriere 	3200,
377c7cf2933SEtienne Carriere 	3300,
378c7cf2933SEtienne Carriere 	3400,
379c7cf2933SEtienne Carriere 	3500,
380c7cf2933SEtienne Carriere 	3600,
381c7cf2933SEtienne Carriere 	3700,
382c7cf2933SEtienne Carriere 	3800,
383c7cf2933SEtienne Carriere 	3900,
384c7cf2933SEtienne Carriere };
385c7cf2933SEtienne Carriere 
386c7cf2933SEtienne Carriere static const uint16_t ldo6_voltage_table[] = {
387c7cf2933SEtienne Carriere 	900,
388c7cf2933SEtienne Carriere 	1000,
389c7cf2933SEtienne Carriere 	1100,
390c7cf2933SEtienne Carriere 	1200,
391c7cf2933SEtienne Carriere 	1300,
392c7cf2933SEtienne Carriere 	1400,
393c7cf2933SEtienne Carriere 	1500,
394c7cf2933SEtienne Carriere 	1600,
395c7cf2933SEtienne Carriere 	1700,
396c7cf2933SEtienne Carriere 	1800,
397c7cf2933SEtienne Carriere 	1900,
398c7cf2933SEtienne Carriere 	2000,
399c7cf2933SEtienne Carriere 	2100,
400c7cf2933SEtienne Carriere 	2200,
401c7cf2933SEtienne Carriere 	2300,
402c7cf2933SEtienne Carriere 	2400,
403c7cf2933SEtienne Carriere 	2500,
404c7cf2933SEtienne Carriere 	2600,
405c7cf2933SEtienne Carriere 	2700,
406c7cf2933SEtienne Carriere 	2800,
407c7cf2933SEtienne Carriere 	2900,
408c7cf2933SEtienne Carriere 	3000,
409c7cf2933SEtienne Carriere 	3100,
410c7cf2933SEtienne Carriere 	3200,
411c7cf2933SEtienne Carriere 	3300,
412c7cf2933SEtienne Carriere };
413c7cf2933SEtienne Carriere 
414c7cf2933SEtienne Carriere static const uint16_t ldo4_voltage_table[] = {
415c7cf2933SEtienne Carriere 	3300,
416c7cf2933SEtienne Carriere };
417c7cf2933SEtienne Carriere 
418c7cf2933SEtienne Carriere static const uint16_t vref_ddr_voltage_table[] = {
419c7cf2933SEtienne Carriere 	3300,
420c7cf2933SEtienne Carriere };
421c7cf2933SEtienne Carriere 
422c7cf2933SEtienne Carriere /* Table of Regulators in PMIC SoC */
423c7cf2933SEtienne Carriere static const struct regul_struct regulators_table[] = {
424c7cf2933SEtienne Carriere 	{
425c7cf2933SEtienne Carriere 		.dt_node_name	= "buck1",
426c7cf2933SEtienne Carriere 		.voltage_table	= buck1_voltage_table,
427c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck1_voltage_table),
428c7cf2933SEtienne Carriere 		.control_reg	= BUCK1_CONTROL_REG,
429c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK1_PWRCTRL_REG,
430c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
431c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK1_PULL_DOWN_SHIFT,
432c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
433c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK1_MASK_RESET_SHIFT,
434c7cf2933SEtienne Carriere 	},
435c7cf2933SEtienne Carriere 	{
436c7cf2933SEtienne Carriere 		.dt_node_name	= "buck2",
437c7cf2933SEtienne Carriere 		.voltage_table	= buck2_voltage_table,
438c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck2_voltage_table),
439c7cf2933SEtienne Carriere 		.control_reg	= BUCK2_CONTROL_REG,
440c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK2_PWRCTRL_REG,
441c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
442c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK2_PULL_DOWN_SHIFT,
443c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
444c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK2_MASK_RESET_SHIFT,
445c7cf2933SEtienne Carriere 	},
446c7cf2933SEtienne Carriere 	{
447c7cf2933SEtienne Carriere 		.dt_node_name	= "buck3",
448c7cf2933SEtienne Carriere 		.voltage_table	= buck3_voltage_table,
449c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck3_voltage_table),
450c7cf2933SEtienne Carriere 		.control_reg	= BUCK3_CONTROL_REG,
451c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK3_PWRCTRL_REG,
452c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
453c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK3_PULL_DOWN_SHIFT,
454c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
455c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK3_MASK_RESET_SHIFT,
456c7cf2933SEtienne Carriere 	},
457c7cf2933SEtienne Carriere 	{
458c7cf2933SEtienne Carriere 		.dt_node_name	= "buck4",
459c7cf2933SEtienne Carriere 		.voltage_table	= buck4_voltage_table,
460c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck4_voltage_table),
461c7cf2933SEtienne Carriere 		.control_reg	= BUCK4_CONTROL_REG,
462c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK4_PWRCTRL_REG,
463c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
464c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK4_PULL_DOWN_SHIFT,
465c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
466c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK4_MASK_RESET_SHIFT,
467c7cf2933SEtienne Carriere 	},
468c7cf2933SEtienne Carriere 	{
469c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo1",
470c7cf2933SEtienne Carriere 		.voltage_table	= ldo1_voltage_table,
471c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo1_voltage_table),
472c7cf2933SEtienne Carriere 		.control_reg	= LDO1_CONTROL_REG,
473c7cf2933SEtienne Carriere 		.low_power_reg	= LDO1_PWRCTRL_REG,
474c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
475c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO1_MASK_RESET_SHIFT,
476c7cf2933SEtienne Carriere 	},
477c7cf2933SEtienne Carriere 	{
478c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo2",
479c7cf2933SEtienne Carriere 		.voltage_table	= ldo2_voltage_table,
480c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo2_voltage_table),
481c7cf2933SEtienne Carriere 		.control_reg	= LDO2_CONTROL_REG,
482c7cf2933SEtienne Carriere 		.low_power_reg	= LDO2_PWRCTRL_REG,
483c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
484c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO2_MASK_RESET_SHIFT,
485c7cf2933SEtienne Carriere 	},
486c7cf2933SEtienne Carriere 	{
487c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo3",
488c7cf2933SEtienne Carriere 		.voltage_table	= ldo3_voltage_table,
489c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo3_voltage_table),
490c7cf2933SEtienne Carriere 		.control_reg	= LDO3_CONTROL_REG,
491c7cf2933SEtienne Carriere 		.low_power_reg	= LDO3_PWRCTRL_REG,
492c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
493c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO3_MASK_RESET_SHIFT,
494c7cf2933SEtienne Carriere 	},
495c7cf2933SEtienne Carriere 	{
496c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo4",
497c7cf2933SEtienne Carriere 		.voltage_table	= ldo4_voltage_table,
498c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo4_voltage_table),
499c7cf2933SEtienne Carriere 		.control_reg	= LDO4_CONTROL_REG,
500c7cf2933SEtienne Carriere 		.low_power_reg	= LDO4_PWRCTRL_REG,
501c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
502c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO4_MASK_RESET_SHIFT,
503c7cf2933SEtienne Carriere 	},
504c7cf2933SEtienne Carriere 	{
505c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo5",
506c7cf2933SEtienne Carriere 		.voltage_table	= ldo5_voltage_table,
507c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo5_voltage_table),
508c7cf2933SEtienne Carriere 		.control_reg	= LDO5_CONTROL_REG,
509c7cf2933SEtienne Carriere 		.low_power_reg	= LDO5_PWRCTRL_REG,
510c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
511c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO5_MASK_RESET_SHIFT,
512c7cf2933SEtienne Carriere 	},
513c7cf2933SEtienne Carriere 	{
514c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo6",
515c7cf2933SEtienne Carriere 		.voltage_table	= ldo6_voltage_table,
516c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo6_voltage_table),
517c7cf2933SEtienne Carriere 		.control_reg	= LDO6_CONTROL_REG,
518c7cf2933SEtienne Carriere 		.low_power_reg	= LDO6_PWRCTRL_REG,
519c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
520c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO6_MASK_RESET_SHIFT,
521c7cf2933SEtienne Carriere 	},
522c7cf2933SEtienne Carriere 	{
523c7cf2933SEtienne Carriere 		.dt_node_name	= "vref_ddr",
524c7cf2933SEtienne Carriere 		.voltage_table	= vref_ddr_voltage_table,
525c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table),
526c7cf2933SEtienne Carriere 		.control_reg	= VREF_DDR_CONTROL_REG,
527c7cf2933SEtienne Carriere 		.low_power_reg	= VREF_DDR_PWRCTRL_REG,
528c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
529c7cf2933SEtienne Carriere 		.mask_reset_pos = VREF_DDR_MASK_RESET_SHIFT,
530c7cf2933SEtienne Carriere 	},
531c7cf2933SEtienne Carriere 	{
532c7cf2933SEtienne Carriere 		.dt_node_name = "boost",
533c7cf2933SEtienne Carriere 	},
534c7cf2933SEtienne Carriere 	{
535c7cf2933SEtienne Carriere 		.dt_node_name = "pwr_sw1",
536c7cf2933SEtienne Carriere 	},
537c7cf2933SEtienne Carriere 	{
538c7cf2933SEtienne Carriere 		.dt_node_name = "pwr_sw2",
539c7cf2933SEtienne Carriere 	},
540c7cf2933SEtienne Carriere };
541c7cf2933SEtienne Carriere 
542c7cf2933SEtienne Carriere static const struct regul_struct *get_regulator_data(const char *name)
543c7cf2933SEtienne Carriere {
544c7cf2933SEtienne Carriere 	unsigned int i = 0;
545c7cf2933SEtienne Carriere 
546c7cf2933SEtienne Carriere 	for (i = 0; i < ARRAY_SIZE(regulators_table); i++)
547c7cf2933SEtienne Carriere 		if (strcmp(name, regulators_table[i].dt_node_name) == 0)
548c7cf2933SEtienne Carriere 			return &regulators_table[i];
549c7cf2933SEtienne Carriere 
550c7cf2933SEtienne Carriere 	/* Regulator not found */
551c7cf2933SEtienne Carriere 	panic(name);
552c7cf2933SEtienne Carriere }
553c7cf2933SEtienne Carriere 
554c7cf2933SEtienne Carriere static uint8_t voltage_to_index(const char *name, uint16_t millivolts)
555c7cf2933SEtienne Carriere {
556c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
557c7cf2933SEtienne Carriere 	unsigned int i = 0;
558c7cf2933SEtienne Carriere 
559c7cf2933SEtienne Carriere 	assert(regul->voltage_table);
560c7cf2933SEtienne Carriere 	for (i = 0; i < regul->voltage_table_size; i++)
561c7cf2933SEtienne Carriere 		if (regul->voltage_table[i] == millivolts)
562c7cf2933SEtienne Carriere 			return i;
563c7cf2933SEtienne Carriere 
564c7cf2933SEtienne Carriere 	/* Voltage not found */
565c7cf2933SEtienne Carriere 	panic(name);
566c7cf2933SEtienne Carriere }
567c7cf2933SEtienne Carriere 
568c7cf2933SEtienne Carriere int stpmic1_powerctrl_on(void)
569c7cf2933SEtienne Carriere {
570c7cf2933SEtienne Carriere 	return stpmic1_register_update(MAIN_CONTROL_REG, PWRCTRL_PIN_VALID,
571c7cf2933SEtienne Carriere 				       PWRCTRL_PIN_VALID);
572c7cf2933SEtienne Carriere }
573c7cf2933SEtienne Carriere 
574c7cf2933SEtienne Carriere int stpmic1_switch_off(void)
575c7cf2933SEtienne Carriere {
576c7cf2933SEtienne Carriere 	return stpmic1_register_update(MAIN_CONTROL_REG, 1,
577c7cf2933SEtienne Carriere 				       SOFTWARE_SWITCH_OFF_ENABLED);
578c7cf2933SEtienne Carriere }
579c7cf2933SEtienne Carriere 
580c7cf2933SEtienne Carriere int stpmic1_regulator_enable(const char *name)
581c7cf2933SEtienne Carriere {
582c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
583c7cf2933SEtienne Carriere 
584c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg, BIT(0), BIT(0));
585c7cf2933SEtienne Carriere }
586c7cf2933SEtienne Carriere 
587c7cf2933SEtienne Carriere int stpmic1_regulator_disable(const char *name)
588c7cf2933SEtienne Carriere {
589c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
590c7cf2933SEtienne Carriere 
591c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg, 0, BIT(0));
592c7cf2933SEtienne Carriere }
593c7cf2933SEtienne Carriere 
594c7cf2933SEtienne Carriere uint8_t stpmic1_is_regulator_enabled(const char *name)
595c7cf2933SEtienne Carriere {
596c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
597c7cf2933SEtienne Carriere 	uint8_t val = 0;
598c7cf2933SEtienne Carriere 
599c7cf2933SEtienne Carriere 	if (stpmic1_register_read(regul->control_reg, &val))
600c7cf2933SEtienne Carriere 		panic();
601c7cf2933SEtienne Carriere 
602c7cf2933SEtienne Carriere 	return val & 0x1;
603c7cf2933SEtienne Carriere }
604c7cf2933SEtienne Carriere 
605c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts)
606c7cf2933SEtienne Carriere {
607c7cf2933SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
608c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
609c7cf2933SEtienne Carriere 	uint8_t mask = 0;
610c7cf2933SEtienne Carriere 
611c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
612c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
613c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
614c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
615c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
616c7cf2933SEtienne Carriere 	else
617c7cf2933SEtienne Carriere 		return 0;
618c7cf2933SEtienne Carriere 
619c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg,
620c7cf2933SEtienne Carriere 				       voltage_index << LDO_BUCK_VOLTAGE_SHIFT,
621c7cf2933SEtienne Carriere 				       mask);
622c7cf2933SEtienne Carriere }
623c7cf2933SEtienne Carriere 
624c7cf2933SEtienne Carriere int stpmic1_regulator_mask_reset_set(const char *name)
625c7cf2933SEtienne Carriere {
626c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
627c7cf2933SEtienne Carriere 
628c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->mask_reset_reg,
629c7cf2933SEtienne Carriere 				       BIT(regul->mask_reset_pos),
630c7cf2933SEtienne Carriere 				       LDO_BUCK_RESET_MASK <<
631c7cf2933SEtienne Carriere 				       regul->mask_reset_pos);
632c7cf2933SEtienne Carriere }
633c7cf2933SEtienne Carriere 
634eb5d5313SEtienne Carriere int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg)
635eb5d5313SEtienne Carriere {
636eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->ctrl_reg, BIT(0), BIT(0));
637eb5d5313SEtienne Carriere }
638eb5d5313SEtienne Carriere 
639eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */
640eb5d5313SEtienne Carriere int stpmic1_bo_voltage_cfg(const char *name, uint16_t millivolts,
641eb5d5313SEtienne Carriere 			   struct stpmic1_bo_cfg *cfg)
642eb5d5313SEtienne Carriere {
643eb5d5313SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
644eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
645eb5d5313SEtienne Carriere 	uint8_t mask = 0;
646eb5d5313SEtienne Carriere 
647eb5d5313SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
648eb5d5313SEtienne Carriere 	if (!strcmp(name, "buck"))
649eb5d5313SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
650eb5d5313SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
651eb5d5313SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
652eb5d5313SEtienne Carriere 	else
653eb5d5313SEtienne Carriere 		return 1;
654eb5d5313SEtienne Carriere 
655eb5d5313SEtienne Carriere 	cfg->ctrl_reg = regul->control_reg;
656eb5d5313SEtienne Carriere 	cfg->value = voltage_index << LDO_BUCK_VOLTAGE_SHIFT;
657eb5d5313SEtienne Carriere 	cfg->mask = mask;
658eb5d5313SEtienne Carriere 
659eb5d5313SEtienne Carriere 	return 0;
660eb5d5313SEtienne Carriere }
661eb5d5313SEtienne Carriere 
662eb5d5313SEtienne Carriere int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg)
663eb5d5313SEtienne Carriere {
664eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->ctrl_reg, cfg->value, cfg->mask);
665eb5d5313SEtienne Carriere }
666eb5d5313SEtienne Carriere 
667eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_cfg(const char *name, struct stpmic1_bo_cfg *cfg)
668eb5d5313SEtienne Carriere {
669eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
670eb5d5313SEtienne Carriere 
671eb5d5313SEtienne Carriere 	cfg->pd_reg = regul->pull_down_reg;
672eb5d5313SEtienne Carriere 	cfg->pd_value = BIT(regul->pull_down_pos);
673eb5d5313SEtienne Carriere 	cfg->pd_mask = LDO_BUCK_PULL_DOWN_MASK << regul->pull_down_pos;
674eb5d5313SEtienne Carriere 
675eb5d5313SEtienne Carriere 	return 0;
676eb5d5313SEtienne Carriere }
677eb5d5313SEtienne Carriere 
678eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg)
679eb5d5313SEtienne Carriere {
680eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->pd_reg, cfg->pd_value,
681eb5d5313SEtienne Carriere 				       cfg->pd_mask);
682eb5d5313SEtienne Carriere }
683eb5d5313SEtienne Carriere 
684eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg)
685eb5d5313SEtienne Carriere {
686eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
687eb5d5313SEtienne Carriere 
688eb5d5313SEtienne Carriere 	cfg->mrst_reg = regul->mask_reset_reg;
689eb5d5313SEtienne Carriere 	cfg->mrst_value = BIT(regul->mask_reset_pos);
690eb5d5313SEtienne Carriere 	cfg->mrst_mask = LDO_BUCK_RESET_MASK << regul->mask_reset_pos;
691eb5d5313SEtienne Carriere 
692eb5d5313SEtienne Carriere 	return 0;
693eb5d5313SEtienne Carriere }
694eb5d5313SEtienne Carriere 
695eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg)
696eb5d5313SEtienne Carriere {
697eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value,
698eb5d5313SEtienne Carriere 				       cfg->mrst_mask);
699eb5d5313SEtienne Carriere }
700eb5d5313SEtienne Carriere 
701c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_get(const char *name)
702c7cf2933SEtienne Carriere {
703c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
704c7cf2933SEtienne Carriere 	uint8_t value = 0;
705c7cf2933SEtienne Carriere 	uint8_t mask = 0;
706c7cf2933SEtienne Carriere 
707c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
708c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
709c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
710c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
711c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
712c7cf2933SEtienne Carriere 	else
713c7cf2933SEtienne Carriere 		return 0;
714c7cf2933SEtienne Carriere 
715c7cf2933SEtienne Carriere 	if (stpmic1_register_read(regul->control_reg, &value))
716c7cf2933SEtienne Carriere 		return -1;
717c7cf2933SEtienne Carriere 
718c7cf2933SEtienne Carriere 	value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT;
719c7cf2933SEtienne Carriere 
720c7cf2933SEtienne Carriere 	if (value > regul->voltage_table_size)
721c7cf2933SEtienne Carriere 		return -1;
722c7cf2933SEtienne Carriere 
723c7cf2933SEtienne Carriere 	return regul->voltage_table[value];
724c7cf2933SEtienne Carriere }
725c7cf2933SEtienne Carriere 
726c7cf2933SEtienne Carriere int stpmic1_lp_copy_reg(const char *name)
727c7cf2933SEtienne Carriere {
728c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
729c7cf2933SEtienne Carriere 	uint8_t val = 0;
730c7cf2933SEtienne Carriere 	int status = 0;
731c7cf2933SEtienne Carriere 
732c7cf2933SEtienne Carriere 	status = stpmic1_register_read(regul->control_reg, &val);
733c7cf2933SEtienne Carriere 	if (status)
734c7cf2933SEtienne Carriere 		return status;
735c7cf2933SEtienne Carriere 
736c7cf2933SEtienne Carriere 	return stpmic1_register_write(regul->low_power_reg, val);
737c7cf2933SEtienne Carriere }
738c7cf2933SEtienne Carriere 
739eb5d5313SEtienne Carriere int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg)
740eb5d5313SEtienne Carriere {
741eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
742eb5d5313SEtienne Carriere 
743eb5d5313SEtienne Carriere 	cfg->ctrl_reg = regul->control_reg;
744eb5d5313SEtienne Carriere 	cfg->lp_reg = regul->low_power_reg;
745eb5d5313SEtienne Carriere 
746eb5d5313SEtienne Carriere 	return 0;
747eb5d5313SEtienne Carriere }
748eb5d5313SEtienne Carriere 
749eb5d5313SEtienne Carriere int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg)
750eb5d5313SEtienne Carriere {
751eb5d5313SEtienne Carriere 	uint8_t val = 0;
752eb5d5313SEtienne Carriere 	int status = 0;
753eb5d5313SEtienne Carriere 
754eb5d5313SEtienne Carriere 	status = stpmic1_register_read(cfg->ctrl_reg, &val);
755eb5d5313SEtienne Carriere 	if (!status)
756eb5d5313SEtienne Carriere 		status = stpmic1_register_write(cfg->lp_reg, val);
757eb5d5313SEtienne Carriere 
758eb5d5313SEtienne Carriere 	return status;
759eb5d5313SEtienne Carriere }
760eb5d5313SEtienne Carriere 
761c7cf2933SEtienne Carriere int stpmic1_lp_reg_on_off(const char *name, uint8_t enable)
762c7cf2933SEtienne Carriere {
763c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
764c7cf2933SEtienne Carriere 
765c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg, enable,
766c7cf2933SEtienne Carriere 				       LDO_BUCK_ENABLE_MASK);
767c7cf2933SEtienne Carriere }
768c7cf2933SEtienne Carriere 
769eb5d5313SEtienne Carriere int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable)
770eb5d5313SEtienne Carriere {
771eb5d5313SEtienne Carriere 	assert(enable == 0 || enable == 1);
772eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg, enable,
773eb5d5313SEtienne Carriere 				       LDO_BUCK_ENABLE_MASK);
774eb5d5313SEtienne Carriere }
775eb5d5313SEtienne Carriere 
776c7cf2933SEtienne Carriere int stpmic1_lp_set_mode(const char *name, uint8_t hplp)
777c7cf2933SEtienne Carriere {
778c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
779c7cf2933SEtienne Carriere 
780c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg,
781c7cf2933SEtienne Carriere 				       hplp << LDO_BUCK_HPLP_SHIFT,
782c7cf2933SEtienne Carriere 				       LDO_BUCK_HPLP_ENABLE_MASK);
783c7cf2933SEtienne Carriere }
784c7cf2933SEtienne Carriere 
785eb5d5313SEtienne Carriere int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg, unsigned int mode)
786eb5d5313SEtienne Carriere {
787eb5d5313SEtienne Carriere 	assert(mode == 0 || mode == 1);
788eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg,
789eb5d5313SEtienne Carriere 				       mode << LDO_BUCK_HPLP_SHIFT,
790eb5d5313SEtienne Carriere 				       LDO_BUCK_HPLP_ENABLE_MASK);
791eb5d5313SEtienne Carriere }
792eb5d5313SEtienne Carriere 
793c7cf2933SEtienne Carriere int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts)
794c7cf2933SEtienne Carriere {
795c7cf2933SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
796c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
797c7cf2933SEtienne Carriere 	uint8_t mask = 0;
798c7cf2933SEtienne Carriere 
799c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
800c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
801c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
802c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
803c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
804c7cf2933SEtienne Carriere 	else
805c7cf2933SEtienne Carriere 		return 0;
806c7cf2933SEtienne Carriere 
807c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg, voltage_index << 2,
808c7cf2933SEtienne Carriere 				       mask);
809c7cf2933SEtienne Carriere }
810c7cf2933SEtienne Carriere 
811eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */
812eb5d5313SEtienne Carriere int stpmic1_lp_voltage_cfg(const char *name, uint16_t millivolts,
813eb5d5313SEtienne Carriere 			   struct stpmic1_lp_cfg *cfg)
814eb5d5313SEtienne Carriere 
815eb5d5313SEtienne Carriere {
816eb5d5313SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
817eb5d5313SEtienne Carriere 	uint8_t mask = 0;
818eb5d5313SEtienne Carriere 
819eb5d5313SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
820eb5d5313SEtienne Carriere 	if (!strcmp(name, "buck"))
821eb5d5313SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
822eb5d5313SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
823eb5d5313SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
824eb5d5313SEtienne Carriere 	else
825eb5d5313SEtienne Carriere 		return 1;
826eb5d5313SEtienne Carriere 
827eb5d5313SEtienne Carriere 	assert(cfg->lp_reg == get_regulator_data(name)->low_power_reg);
828eb5d5313SEtienne Carriere 	cfg->value = voltage_index << 2;
829eb5d5313SEtienne Carriere 	cfg->mask = mask;
830eb5d5313SEtienne Carriere 
831eb5d5313SEtienne Carriere 	return 0;
832eb5d5313SEtienne Carriere }
833eb5d5313SEtienne Carriere 
834eb5d5313SEtienne Carriere int stpmic1_lp_voltage_unpg(struct stpmic1_lp_cfg *cfg)
835eb5d5313SEtienne Carriere {
836eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg, cfg->value,	cfg->mask);
837eb5d5313SEtienne Carriere }
838eb5d5313SEtienne Carriere 
839c7cf2933SEtienne Carriere int stpmic1_register_read(uint8_t register_id,  uint8_t *value)
840c7cf2933SEtienne Carriere {
841c7cf2933SEtienne Carriere 	struct i2c_handle_s *i2c = pmic_i2c_handle;
842c7cf2933SEtienne Carriere 
843eb5d5313SEtienne Carriere 	return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr,
844eb5d5313SEtienne Carriere 					    register_id, value,
845eb5d5313SEtienne Carriere 					    false /* !write */);
846c7cf2933SEtienne Carriere }
847c7cf2933SEtienne Carriere 
848c7cf2933SEtienne Carriere int stpmic1_register_write(uint8_t register_id, uint8_t value)
849c7cf2933SEtienne Carriere {
850c7cf2933SEtienne Carriere 	struct i2c_handle_s *i2c = pmic_i2c_handle;
851c7cf2933SEtienne Carriere 	uint8_t val = value;
852c7cf2933SEtienne Carriere 
853eb5d5313SEtienne Carriere 	return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr,
854eb5d5313SEtienne Carriere 					    register_id, &val,
855eb5d5313SEtienne Carriere 					    true /* write */);
856c7cf2933SEtienne Carriere }
857c7cf2933SEtienne Carriere 
858c7cf2933SEtienne Carriere int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask)
859c7cf2933SEtienne Carriere {
860c7cf2933SEtienne Carriere 	int status = 0;
861c7cf2933SEtienne Carriere 	uint8_t val = 0;
862c7cf2933SEtienne Carriere 
863c7cf2933SEtienne Carriere 	status = stpmic1_register_read(register_id, &val);
864c7cf2933SEtienne Carriere 	if (status)
865c7cf2933SEtienne Carriere 		return status;
866c7cf2933SEtienne Carriere 
867c7cf2933SEtienne Carriere 	val = (val & ~mask) | (value & mask);
868c7cf2933SEtienne Carriere 
869c7cf2933SEtienne Carriere 	return stpmic1_register_write(register_id, val);
870c7cf2933SEtienne Carriere }
871c7cf2933SEtienne Carriere 
872c7cf2933SEtienne Carriere void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr)
873c7cf2933SEtienne Carriere {
874c7cf2933SEtienne Carriere 	pmic_i2c_handle = i2c_handle;
875c7cf2933SEtienne Carriere 	pmic_i2c_addr = i2c_addr;
876c7cf2933SEtienne Carriere }
877c7cf2933SEtienne Carriere 
878c7cf2933SEtienne Carriere void stpmic1_dump_regulators(void)
879c7cf2933SEtienne Carriere {
880c7cf2933SEtienne Carriere 	size_t i = 0;
881c7cf2933SEtienne Carriere 	char __maybe_unused const *name = NULL;
882c7cf2933SEtienne Carriere 
883c7cf2933SEtienne Carriere 	for (i = 0; i < ARRAY_SIZE(regulators_table); i++) {
884c7cf2933SEtienne Carriere 		if (!regulators_table[i].control_reg)
885c7cf2933SEtienne Carriere 			continue;
886c7cf2933SEtienne Carriere 
887c7cf2933SEtienne Carriere 		name = regulators_table[i].dt_node_name;
888c7cf2933SEtienne Carriere 		DMSG("PMIC regul %s: %sable, %dmV",
889c7cf2933SEtienne Carriere 		     name, stpmic1_is_regulator_enabled(name) ? "en" : "dis",
890c7cf2933SEtienne Carriere 		     stpmic1_regulator_voltage_get(name));
891c7cf2933SEtienne Carriere 	}
892c7cf2933SEtienne Carriere }
893c7cf2933SEtienne Carriere 
894c7cf2933SEtienne Carriere int stpmic1_get_version(unsigned long *version)
895c7cf2933SEtienne Carriere {
896c7cf2933SEtienne Carriere 	uint8_t read_val = 0;
897c7cf2933SEtienne Carriere 
898c7cf2933SEtienne Carriere 	if (stpmic1_register_read(VERSION_STATUS_REG, &read_val))
899c7cf2933SEtienne Carriere 		return -1;
900c7cf2933SEtienne Carriere 
901c7cf2933SEtienne Carriere 	*version = read_val;
902c7cf2933SEtienne Carriere 	return 0;
903c7cf2933SEtienne Carriere }
904