xref: /optee_os/core/drivers/stpmic1.c (revision eb5d53139be138b492cfbf5f324308bd381968de)
1c7cf2933SEtienne Carriere // SPDX-License-Identifier: BSD-3-Clause
2c7cf2933SEtienne Carriere /*
3c7cf2933SEtienne Carriere  * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved
4c7cf2933SEtienne Carriere  */
5c7cf2933SEtienne Carriere 
6c7cf2933SEtienne Carriere #include <assert.h>
7c7cf2933SEtienne Carriere #include <drivers/stpmic1.h>
8c7cf2933SEtienne Carriere #include <kernel/panic.h>
9c7cf2933SEtienne Carriere #include <platform_config.h>
10c7cf2933SEtienne Carriere #include <stdint.h>
11c7cf2933SEtienne Carriere #include <string.h>
12c7cf2933SEtienne Carriere #include <trace.h>
13c7cf2933SEtienne Carriere 
14c7cf2933SEtienne Carriere struct regul_struct {
15c7cf2933SEtienne Carriere 	const char *dt_node_name;
16c7cf2933SEtienne Carriere 	const uint16_t *voltage_table;
17c7cf2933SEtienne Carriere 	uint8_t voltage_table_size;
18c7cf2933SEtienne Carriere 	uint8_t control_reg;
19c7cf2933SEtienne Carriere 	uint8_t low_power_reg;
20c7cf2933SEtienne Carriere 	uint8_t pull_down_reg;
21c7cf2933SEtienne Carriere 	uint8_t pull_down_pos;
22c7cf2933SEtienne Carriere 	uint8_t mask_reset_reg;
23c7cf2933SEtienne Carriere 	uint8_t mask_reset_pos;
24c7cf2933SEtienne Carriere };
25c7cf2933SEtienne Carriere 
26c7cf2933SEtienne Carriere static struct i2c_handle_s *pmic_i2c_handle;
27c7cf2933SEtienne Carriere static uint16_t pmic_i2c_addr;
28c7cf2933SEtienne Carriere 
29c7cf2933SEtienne Carriere /* Voltage tables in mV */
30c7cf2933SEtienne Carriere static const uint16_t buck1_voltage_table[] = {
31c7cf2933SEtienne Carriere 	725,
32c7cf2933SEtienne Carriere 	725,
33c7cf2933SEtienne Carriere 	725,
34c7cf2933SEtienne Carriere 	725,
35c7cf2933SEtienne Carriere 	725,
36c7cf2933SEtienne Carriere 	725,
37c7cf2933SEtienne Carriere 	750,
38c7cf2933SEtienne Carriere 	775,
39c7cf2933SEtienne Carriere 	800,
40c7cf2933SEtienne Carriere 	825,
41c7cf2933SEtienne Carriere 	850,
42c7cf2933SEtienne Carriere 	875,
43c7cf2933SEtienne Carriere 	900,
44c7cf2933SEtienne Carriere 	925,
45c7cf2933SEtienne Carriere 	950,
46c7cf2933SEtienne Carriere 	975,
47c7cf2933SEtienne Carriere 	1000,
48c7cf2933SEtienne Carriere 	1025,
49c7cf2933SEtienne Carriere 	1050,
50c7cf2933SEtienne Carriere 	1075,
51c7cf2933SEtienne Carriere 	1100,
52c7cf2933SEtienne Carriere 	1125,
53c7cf2933SEtienne Carriere 	1150,
54c7cf2933SEtienne Carriere 	1175,
55c7cf2933SEtienne Carriere 	1200,
56c7cf2933SEtienne Carriere 	1225,
57c7cf2933SEtienne Carriere 	1250,
58c7cf2933SEtienne Carriere 	1275,
59c7cf2933SEtienne Carriere 	1300,
60c7cf2933SEtienne Carriere 	1325,
61c7cf2933SEtienne Carriere 	1350,
62c7cf2933SEtienne Carriere 	1375,
63c7cf2933SEtienne Carriere 	1400,
64c7cf2933SEtienne Carriere 	1425,
65c7cf2933SEtienne Carriere 	1450,
66c7cf2933SEtienne Carriere 	1475,
67c7cf2933SEtienne Carriere 	1500,
68c7cf2933SEtienne Carriere 	1500,
69c7cf2933SEtienne Carriere 	1500,
70c7cf2933SEtienne Carriere 	1500,
71c7cf2933SEtienne Carriere 	1500,
72c7cf2933SEtienne Carriere 	1500,
73c7cf2933SEtienne Carriere 	1500,
74c7cf2933SEtienne Carriere 	1500,
75c7cf2933SEtienne Carriere 	1500,
76c7cf2933SEtienne Carriere 	1500,
77c7cf2933SEtienne Carriere 	1500,
78c7cf2933SEtienne Carriere 	1500,
79c7cf2933SEtienne Carriere 	1500,
80c7cf2933SEtienne Carriere 	1500,
81c7cf2933SEtienne Carriere 	1500,
82c7cf2933SEtienne Carriere 	1500,
83c7cf2933SEtienne Carriere 	1500,
84c7cf2933SEtienne Carriere 	1500,
85c7cf2933SEtienne Carriere 	1500,
86c7cf2933SEtienne Carriere 	1500,
87c7cf2933SEtienne Carriere 	1500,
88c7cf2933SEtienne Carriere 	1500,
89c7cf2933SEtienne Carriere 	1500,
90c7cf2933SEtienne Carriere 	1500,
91c7cf2933SEtienne Carriere 	1500,
92c7cf2933SEtienne Carriere 	1500,
93c7cf2933SEtienne Carriere 	1500,
94c7cf2933SEtienne Carriere 	1500,
95c7cf2933SEtienne Carriere };
96c7cf2933SEtienne Carriere 
97c7cf2933SEtienne Carriere static const uint16_t buck2_voltage_table[] = {
98c7cf2933SEtienne Carriere 	1000,
99c7cf2933SEtienne Carriere 	1000,
100c7cf2933SEtienne Carriere 	1000,
101c7cf2933SEtienne Carriere 	1000,
102c7cf2933SEtienne Carriere 	1000,
103c7cf2933SEtienne Carriere 	1000,
104c7cf2933SEtienne Carriere 	1000,
105c7cf2933SEtienne Carriere 	1000,
106c7cf2933SEtienne Carriere 	1000,
107c7cf2933SEtienne Carriere 	1000,
108c7cf2933SEtienne Carriere 	1000,
109c7cf2933SEtienne Carriere 	1000,
110c7cf2933SEtienne Carriere 	1000,
111c7cf2933SEtienne Carriere 	1000,
112c7cf2933SEtienne Carriere 	1000,
113c7cf2933SEtienne Carriere 	1000,
114c7cf2933SEtienne Carriere 	1000,
115c7cf2933SEtienne Carriere 	1000,
116c7cf2933SEtienne Carriere 	1050,
117c7cf2933SEtienne Carriere 	1050,
118c7cf2933SEtienne Carriere 	1100,
119c7cf2933SEtienne Carriere 	1100,
120c7cf2933SEtienne Carriere 	1150,
121c7cf2933SEtienne Carriere 	1150,
122c7cf2933SEtienne Carriere 	1200,
123c7cf2933SEtienne Carriere 	1200,
124c7cf2933SEtienne Carriere 	1250,
125c7cf2933SEtienne Carriere 	1250,
126c7cf2933SEtienne Carriere 	1300,
127c7cf2933SEtienne Carriere 	1300,
128c7cf2933SEtienne Carriere 	1350,
129c7cf2933SEtienne Carriere 	1350,
130c7cf2933SEtienne Carriere 	1400,
131c7cf2933SEtienne Carriere 	1400,
132c7cf2933SEtienne Carriere 	1450,
133c7cf2933SEtienne Carriere 	1450,
134c7cf2933SEtienne Carriere 	1500,
135c7cf2933SEtienne Carriere };
136c7cf2933SEtienne Carriere 
137c7cf2933SEtienne Carriere static const uint16_t buck3_voltage_table[] = {
138c7cf2933SEtienne Carriere 	1000,
139c7cf2933SEtienne Carriere 	1000,
140c7cf2933SEtienne Carriere 	1000,
141c7cf2933SEtienne Carriere 	1000,
142c7cf2933SEtienne Carriere 	1000,
143c7cf2933SEtienne Carriere 	1000,
144c7cf2933SEtienne Carriere 	1000,
145c7cf2933SEtienne Carriere 	1000,
146c7cf2933SEtienne Carriere 	1000,
147c7cf2933SEtienne Carriere 	1000,
148c7cf2933SEtienne Carriere 	1000,
149c7cf2933SEtienne Carriere 	1000,
150c7cf2933SEtienne Carriere 	1000,
151c7cf2933SEtienne Carriere 	1000,
152c7cf2933SEtienne Carriere 	1000,
153c7cf2933SEtienne Carriere 	1000,
154c7cf2933SEtienne Carriere 	1000,
155c7cf2933SEtienne Carriere 	1000,
156c7cf2933SEtienne Carriere 	1000,
157c7cf2933SEtienne Carriere 	1000,
158c7cf2933SEtienne Carriere 	1100,
159c7cf2933SEtienne Carriere 	1100,
160c7cf2933SEtienne Carriere 	1100,
161c7cf2933SEtienne Carriere 	1100,
162c7cf2933SEtienne Carriere 	1200,
163c7cf2933SEtienne Carriere 	1200,
164c7cf2933SEtienne Carriere 	1200,
165c7cf2933SEtienne Carriere 	1200,
166c7cf2933SEtienne Carriere 	1300,
167c7cf2933SEtienne Carriere 	1300,
168c7cf2933SEtienne Carriere 	1300,
169c7cf2933SEtienne Carriere 	1300,
170c7cf2933SEtienne Carriere 	1400,
171c7cf2933SEtienne Carriere 	1400,
172c7cf2933SEtienne Carriere 	1400,
173c7cf2933SEtienne Carriere 	1400,
174c7cf2933SEtienne Carriere 	1500,
175c7cf2933SEtienne Carriere 	1600,
176c7cf2933SEtienne Carriere 	1700,
177c7cf2933SEtienne Carriere 	1800,
178c7cf2933SEtienne Carriere 	1900,
179c7cf2933SEtienne Carriere 	2000,
180c7cf2933SEtienne Carriere 	2100,
181c7cf2933SEtienne Carriere 	2200,
182c7cf2933SEtienne Carriere 	2300,
183c7cf2933SEtienne Carriere 	2400,
184c7cf2933SEtienne Carriere 	2500,
185c7cf2933SEtienne Carriere 	2600,
186c7cf2933SEtienne Carriere 	2700,
187c7cf2933SEtienne Carriere 	2800,
188c7cf2933SEtienne Carriere 	2900,
189c7cf2933SEtienne Carriere 	3000,
190c7cf2933SEtienne Carriere 	3100,
191c7cf2933SEtienne Carriere 	3200,
192c7cf2933SEtienne Carriere 	3300,
193c7cf2933SEtienne Carriere 	3400,
194c7cf2933SEtienne Carriere };
195c7cf2933SEtienne Carriere 
196c7cf2933SEtienne Carriere static const uint16_t buck4_voltage_table[] = {
197c7cf2933SEtienne Carriere 	600,
198c7cf2933SEtienne Carriere 	625,
199c7cf2933SEtienne Carriere 	650,
200c7cf2933SEtienne Carriere 	675,
201c7cf2933SEtienne Carriere 	700,
202c7cf2933SEtienne Carriere 	725,
203c7cf2933SEtienne Carriere 	750,
204c7cf2933SEtienne Carriere 	775,
205c7cf2933SEtienne Carriere 	800,
206c7cf2933SEtienne Carriere 	825,
207c7cf2933SEtienne Carriere 	850,
208c7cf2933SEtienne Carriere 	875,
209c7cf2933SEtienne Carriere 	900,
210c7cf2933SEtienne Carriere 	925,
211c7cf2933SEtienne Carriere 	950,
212c7cf2933SEtienne Carriere 	975,
213c7cf2933SEtienne Carriere 	1000,
214c7cf2933SEtienne Carriere 	1025,
215c7cf2933SEtienne Carriere 	1050,
216c7cf2933SEtienne Carriere 	1075,
217c7cf2933SEtienne Carriere 	1100,
218c7cf2933SEtienne Carriere 	1125,
219c7cf2933SEtienne Carriere 	1150,
220c7cf2933SEtienne Carriere 	1175,
221c7cf2933SEtienne Carriere 	1200,
222c7cf2933SEtienne Carriere 	1225,
223c7cf2933SEtienne Carriere 	1250,
224c7cf2933SEtienne Carriere 	1275,
225c7cf2933SEtienne Carriere 	1300,
226c7cf2933SEtienne Carriere 	1300,
227c7cf2933SEtienne Carriere 	1350,
228c7cf2933SEtienne Carriere 	1350,
229c7cf2933SEtienne Carriere 	1400,
230c7cf2933SEtienne Carriere 	1400,
231c7cf2933SEtienne Carriere 	1450,
232c7cf2933SEtienne Carriere 	1450,
233c7cf2933SEtienne Carriere 	1500,
234c7cf2933SEtienne Carriere 	1600,
235c7cf2933SEtienne Carriere 	1700,
236c7cf2933SEtienne Carriere 	1800,
237c7cf2933SEtienne Carriere 	1900,
238c7cf2933SEtienne Carriere 	2000,
239c7cf2933SEtienne Carriere 	2100,
240c7cf2933SEtienne Carriere 	2200,
241c7cf2933SEtienne Carriere 	2300,
242c7cf2933SEtienne Carriere 	2400,
243c7cf2933SEtienne Carriere 	2500,
244c7cf2933SEtienne Carriere 	2600,
245c7cf2933SEtienne Carriere 	2700,
246c7cf2933SEtienne Carriere 	2800,
247c7cf2933SEtienne Carriere 	2900,
248c7cf2933SEtienne Carriere 	3000,
249c7cf2933SEtienne Carriere 	3100,
250c7cf2933SEtienne Carriere 	3200,
251c7cf2933SEtienne Carriere 	3300,
252c7cf2933SEtienne Carriere 	3400,
253c7cf2933SEtienne Carriere 	3500,
254c7cf2933SEtienne Carriere 	3600,
255c7cf2933SEtienne Carriere 	3700,
256c7cf2933SEtienne Carriere 	3800,
257c7cf2933SEtienne Carriere 	3900,
258c7cf2933SEtienne Carriere };
259c7cf2933SEtienne Carriere 
260c7cf2933SEtienne Carriere static const uint16_t ldo1_voltage_table[] = {
261c7cf2933SEtienne Carriere 	1700,
262c7cf2933SEtienne Carriere 	1700,
263c7cf2933SEtienne Carriere 	1700,
264c7cf2933SEtienne Carriere 	1700,
265c7cf2933SEtienne Carriere 	1700,
266c7cf2933SEtienne Carriere 	1700,
267c7cf2933SEtienne Carriere 	1700,
268c7cf2933SEtienne Carriere 	1700,
269c7cf2933SEtienne Carriere 	1700,
270c7cf2933SEtienne Carriere 	1800,
271c7cf2933SEtienne Carriere 	1900,
272c7cf2933SEtienne Carriere 	2000,
273c7cf2933SEtienne Carriere 	2100,
274c7cf2933SEtienne Carriere 	2200,
275c7cf2933SEtienne Carriere 	2300,
276c7cf2933SEtienne Carriere 	2400,
277c7cf2933SEtienne Carriere 	2500,
278c7cf2933SEtienne Carriere 	2600,
279c7cf2933SEtienne Carriere 	2700,
280c7cf2933SEtienne Carriere 	2800,
281c7cf2933SEtienne Carriere 	2900,
282c7cf2933SEtienne Carriere 	3000,
283c7cf2933SEtienne Carriere 	3100,
284c7cf2933SEtienne Carriere 	3200,
285c7cf2933SEtienne Carriere 	3300,
286c7cf2933SEtienne Carriere };
287c7cf2933SEtienne Carriere 
288c7cf2933SEtienne Carriere static const uint16_t ldo2_voltage_table[] = {
289c7cf2933SEtienne Carriere 	1700,
290c7cf2933SEtienne Carriere 	1700,
291c7cf2933SEtienne Carriere 	1700,
292c7cf2933SEtienne Carriere 	1700,
293c7cf2933SEtienne Carriere 	1700,
294c7cf2933SEtienne Carriere 	1700,
295c7cf2933SEtienne Carriere 	1700,
296c7cf2933SEtienne Carriere 	1700,
297c7cf2933SEtienne Carriere 	1700,
298c7cf2933SEtienne Carriere 	1800,
299c7cf2933SEtienne Carriere 	1900,
300c7cf2933SEtienne Carriere 	2000,
301c7cf2933SEtienne Carriere 	2100,
302c7cf2933SEtienne Carriere 	2200,
303c7cf2933SEtienne Carriere 	2300,
304c7cf2933SEtienne Carriere 	2400,
305c7cf2933SEtienne Carriere 	2500,
306c7cf2933SEtienne Carriere 	2600,
307c7cf2933SEtienne Carriere 	2700,
308c7cf2933SEtienne Carriere 	2800,
309c7cf2933SEtienne Carriere 	2900,
310c7cf2933SEtienne Carriere 	3000,
311c7cf2933SEtienne Carriere 	3100,
312c7cf2933SEtienne Carriere 	3200,
313c7cf2933SEtienne Carriere 	3300,
314c7cf2933SEtienne Carriere };
315c7cf2933SEtienne Carriere 
316c7cf2933SEtienne Carriere static const uint16_t ldo3_voltage_table[] = {
317c7cf2933SEtienne Carriere 	1700,
318c7cf2933SEtienne Carriere 	1700,
319c7cf2933SEtienne Carriere 	1700,
320c7cf2933SEtienne Carriere 	1700,
321c7cf2933SEtienne Carriere 	1700,
322c7cf2933SEtienne Carriere 	1700,
323c7cf2933SEtienne Carriere 	1700,
324c7cf2933SEtienne Carriere 	1700,
325c7cf2933SEtienne Carriere 	1700,
326c7cf2933SEtienne Carriere 	1800,
327c7cf2933SEtienne Carriere 	1900,
328c7cf2933SEtienne Carriere 	2000,
329c7cf2933SEtienne Carriere 	2100,
330c7cf2933SEtienne Carriere 	2200,
331c7cf2933SEtienne Carriere 	2300,
332c7cf2933SEtienne Carriere 	2400,
333c7cf2933SEtienne Carriere 	2500,
334c7cf2933SEtienne Carriere 	2600,
335c7cf2933SEtienne Carriere 	2700,
336c7cf2933SEtienne Carriere 	2800,
337c7cf2933SEtienne Carriere 	2900,
338c7cf2933SEtienne Carriere 	3000,
339c7cf2933SEtienne Carriere 	3100,
340c7cf2933SEtienne Carriere 	3200,
341c7cf2933SEtienne Carriere 	3300,
342c7cf2933SEtienne Carriere 	3300,
343c7cf2933SEtienne Carriere 	3300,
344c7cf2933SEtienne Carriere 	3300,
345c7cf2933SEtienne Carriere 	3300,
346c7cf2933SEtienne Carriere 	3300,
347c7cf2933SEtienne Carriere 	3300,
348c7cf2933SEtienne Carriere 	0xFFFF, /* VREFDDR */
349c7cf2933SEtienne Carriere };
350c7cf2933SEtienne Carriere 
351c7cf2933SEtienne Carriere static const uint16_t ldo5_voltage_table[] = {
352c7cf2933SEtienne Carriere 	1700,
353c7cf2933SEtienne Carriere 	1700,
354c7cf2933SEtienne Carriere 	1700,
355c7cf2933SEtienne Carriere 	1700,
356c7cf2933SEtienne Carriere 	1700,
357c7cf2933SEtienne Carriere 	1700,
358c7cf2933SEtienne Carriere 	1700,
359c7cf2933SEtienne Carriere 	1700,
360c7cf2933SEtienne Carriere 	1700,
361c7cf2933SEtienne Carriere 	1800,
362c7cf2933SEtienne Carriere 	1900,
363c7cf2933SEtienne Carriere 	2000,
364c7cf2933SEtienne Carriere 	2100,
365c7cf2933SEtienne Carriere 	2200,
366c7cf2933SEtienne Carriere 	2300,
367c7cf2933SEtienne Carriere 	2400,
368c7cf2933SEtienne Carriere 	2500,
369c7cf2933SEtienne Carriere 	2600,
370c7cf2933SEtienne Carriere 	2700,
371c7cf2933SEtienne Carriere 	2800,
372c7cf2933SEtienne Carriere 	2900,
373c7cf2933SEtienne Carriere 	3000,
374c7cf2933SEtienne Carriere 	3100,
375c7cf2933SEtienne Carriere 	3200,
376c7cf2933SEtienne Carriere 	3300,
377c7cf2933SEtienne Carriere 	3400,
378c7cf2933SEtienne Carriere 	3500,
379c7cf2933SEtienne Carriere 	3600,
380c7cf2933SEtienne Carriere 	3700,
381c7cf2933SEtienne Carriere 	3800,
382c7cf2933SEtienne Carriere 	3900,
383c7cf2933SEtienne Carriere };
384c7cf2933SEtienne Carriere 
385c7cf2933SEtienne Carriere static const uint16_t ldo6_voltage_table[] = {
386c7cf2933SEtienne Carriere 	900,
387c7cf2933SEtienne Carriere 	1000,
388c7cf2933SEtienne Carriere 	1100,
389c7cf2933SEtienne Carriere 	1200,
390c7cf2933SEtienne Carriere 	1300,
391c7cf2933SEtienne Carriere 	1400,
392c7cf2933SEtienne Carriere 	1500,
393c7cf2933SEtienne Carriere 	1600,
394c7cf2933SEtienne Carriere 	1700,
395c7cf2933SEtienne Carriere 	1800,
396c7cf2933SEtienne Carriere 	1900,
397c7cf2933SEtienne Carriere 	2000,
398c7cf2933SEtienne Carriere 	2100,
399c7cf2933SEtienne Carriere 	2200,
400c7cf2933SEtienne Carriere 	2300,
401c7cf2933SEtienne Carriere 	2400,
402c7cf2933SEtienne Carriere 	2500,
403c7cf2933SEtienne Carriere 	2600,
404c7cf2933SEtienne Carriere 	2700,
405c7cf2933SEtienne Carriere 	2800,
406c7cf2933SEtienne Carriere 	2900,
407c7cf2933SEtienne Carriere 	3000,
408c7cf2933SEtienne Carriere 	3100,
409c7cf2933SEtienne Carriere 	3200,
410c7cf2933SEtienne Carriere 	3300,
411c7cf2933SEtienne Carriere };
412c7cf2933SEtienne Carriere 
413c7cf2933SEtienne Carriere static const uint16_t ldo4_voltage_table[] = {
414c7cf2933SEtienne Carriere 	3300,
415c7cf2933SEtienne Carriere };
416c7cf2933SEtienne Carriere 
417c7cf2933SEtienne Carriere static const uint16_t vref_ddr_voltage_table[] = {
418c7cf2933SEtienne Carriere 	3300,
419c7cf2933SEtienne Carriere };
420c7cf2933SEtienne Carriere 
421c7cf2933SEtienne Carriere /* Table of Regulators in PMIC SoC */
422c7cf2933SEtienne Carriere static const struct regul_struct regulators_table[] = {
423c7cf2933SEtienne Carriere 	{
424c7cf2933SEtienne Carriere 		.dt_node_name	= "buck1",
425c7cf2933SEtienne Carriere 		.voltage_table	= buck1_voltage_table,
426c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck1_voltage_table),
427c7cf2933SEtienne Carriere 		.control_reg	= BUCK1_CONTROL_REG,
428c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK1_PWRCTRL_REG,
429c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
430c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK1_PULL_DOWN_SHIFT,
431c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
432c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK1_MASK_RESET_SHIFT,
433c7cf2933SEtienne Carriere 	},
434c7cf2933SEtienne Carriere 	{
435c7cf2933SEtienne Carriere 		.dt_node_name	= "buck2",
436c7cf2933SEtienne Carriere 		.voltage_table	= buck2_voltage_table,
437c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck2_voltage_table),
438c7cf2933SEtienne Carriere 		.control_reg	= BUCK2_CONTROL_REG,
439c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK2_PWRCTRL_REG,
440c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
441c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK2_PULL_DOWN_SHIFT,
442c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
443c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK2_MASK_RESET_SHIFT,
444c7cf2933SEtienne Carriere 	},
445c7cf2933SEtienne Carriere 	{
446c7cf2933SEtienne Carriere 		.dt_node_name	= "buck3",
447c7cf2933SEtienne Carriere 		.voltage_table	= buck3_voltage_table,
448c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck3_voltage_table),
449c7cf2933SEtienne Carriere 		.control_reg	= BUCK3_CONTROL_REG,
450c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK3_PWRCTRL_REG,
451c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
452c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK3_PULL_DOWN_SHIFT,
453c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
454c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK3_MASK_RESET_SHIFT,
455c7cf2933SEtienne Carriere 	},
456c7cf2933SEtienne Carriere 	{
457c7cf2933SEtienne Carriere 		.dt_node_name	= "buck4",
458c7cf2933SEtienne Carriere 		.voltage_table	= buck4_voltage_table,
459c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(buck4_voltage_table),
460c7cf2933SEtienne Carriere 		.control_reg	= BUCK4_CONTROL_REG,
461c7cf2933SEtienne Carriere 		.low_power_reg	= BUCK4_PWRCTRL_REG,
462c7cf2933SEtienne Carriere 		.pull_down_reg	= BUCK_PULL_DOWN_REG,
463c7cf2933SEtienne Carriere 		.pull_down_pos	= BUCK4_PULL_DOWN_SHIFT,
464c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_BUCK_REG,
465c7cf2933SEtienne Carriere 		.mask_reset_pos = BUCK4_MASK_RESET_SHIFT,
466c7cf2933SEtienne Carriere 	},
467c7cf2933SEtienne Carriere 	{
468c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo1",
469c7cf2933SEtienne Carriere 		.voltage_table	= ldo1_voltage_table,
470c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo1_voltage_table),
471c7cf2933SEtienne Carriere 		.control_reg	= LDO1_CONTROL_REG,
472c7cf2933SEtienne Carriere 		.low_power_reg	= LDO1_PWRCTRL_REG,
473c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
474c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO1_MASK_RESET_SHIFT,
475c7cf2933SEtienne Carriere 	},
476c7cf2933SEtienne Carriere 	{
477c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo2",
478c7cf2933SEtienne Carriere 		.voltage_table	= ldo2_voltage_table,
479c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo2_voltage_table),
480c7cf2933SEtienne Carriere 		.control_reg	= LDO2_CONTROL_REG,
481c7cf2933SEtienne Carriere 		.low_power_reg	= LDO2_PWRCTRL_REG,
482c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
483c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO2_MASK_RESET_SHIFT,
484c7cf2933SEtienne Carriere 	},
485c7cf2933SEtienne Carriere 	{
486c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo3",
487c7cf2933SEtienne Carriere 		.voltage_table	= ldo3_voltage_table,
488c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo3_voltage_table),
489c7cf2933SEtienne Carriere 		.control_reg	= LDO3_CONTROL_REG,
490c7cf2933SEtienne Carriere 		.low_power_reg	= LDO3_PWRCTRL_REG,
491c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
492c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO3_MASK_RESET_SHIFT,
493c7cf2933SEtienne Carriere 	},
494c7cf2933SEtienne Carriere 	{
495c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo4",
496c7cf2933SEtienne Carriere 		.voltage_table	= ldo4_voltage_table,
497c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo4_voltage_table),
498c7cf2933SEtienne Carriere 		.control_reg	= LDO4_CONTROL_REG,
499c7cf2933SEtienne Carriere 		.low_power_reg	= LDO4_PWRCTRL_REG,
500c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
501c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO4_MASK_RESET_SHIFT,
502c7cf2933SEtienne Carriere 	},
503c7cf2933SEtienne Carriere 	{
504c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo5",
505c7cf2933SEtienne Carriere 		.voltage_table	= ldo5_voltage_table,
506c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo5_voltage_table),
507c7cf2933SEtienne Carriere 		.control_reg	= LDO5_CONTROL_REG,
508c7cf2933SEtienne Carriere 		.low_power_reg	= LDO5_PWRCTRL_REG,
509c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
510c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO5_MASK_RESET_SHIFT,
511c7cf2933SEtienne Carriere 	},
512c7cf2933SEtienne Carriere 	{
513c7cf2933SEtienne Carriere 		.dt_node_name	= "ldo6",
514c7cf2933SEtienne Carriere 		.voltage_table	= ldo6_voltage_table,
515c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(ldo6_voltage_table),
516c7cf2933SEtienne Carriere 		.control_reg	= LDO6_CONTROL_REG,
517c7cf2933SEtienne Carriere 		.low_power_reg	= LDO6_PWRCTRL_REG,
518c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
519c7cf2933SEtienne Carriere 		.mask_reset_pos = LDO6_MASK_RESET_SHIFT,
520c7cf2933SEtienne Carriere 	},
521c7cf2933SEtienne Carriere 	{
522c7cf2933SEtienne Carriere 		.dt_node_name	= "vref_ddr",
523c7cf2933SEtienne Carriere 		.voltage_table	= vref_ddr_voltage_table,
524c7cf2933SEtienne Carriere 		.voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table),
525c7cf2933SEtienne Carriere 		.control_reg	= VREF_DDR_CONTROL_REG,
526c7cf2933SEtienne Carriere 		.low_power_reg	= VREF_DDR_PWRCTRL_REG,
527c7cf2933SEtienne Carriere 		.mask_reset_reg = MASK_RESET_LDO_REG,
528c7cf2933SEtienne Carriere 		.mask_reset_pos = VREF_DDR_MASK_RESET_SHIFT,
529c7cf2933SEtienne Carriere 	},
530c7cf2933SEtienne Carriere 	{
531c7cf2933SEtienne Carriere 		.dt_node_name = "boost",
532c7cf2933SEtienne Carriere 	},
533c7cf2933SEtienne Carriere 	{
534c7cf2933SEtienne Carriere 		.dt_node_name = "pwr_sw1",
535c7cf2933SEtienne Carriere 	},
536c7cf2933SEtienne Carriere 	{
537c7cf2933SEtienne Carriere 		.dt_node_name = "pwr_sw2",
538c7cf2933SEtienne Carriere 	},
539c7cf2933SEtienne Carriere };
540c7cf2933SEtienne Carriere 
541c7cf2933SEtienne Carriere static const struct regul_struct *get_regulator_data(const char *name)
542c7cf2933SEtienne Carriere {
543c7cf2933SEtienne Carriere 	unsigned int i = 0;
544c7cf2933SEtienne Carriere 
545c7cf2933SEtienne Carriere 	for (i = 0; i < ARRAY_SIZE(regulators_table); i++)
546c7cf2933SEtienne Carriere 		if (strcmp(name, regulators_table[i].dt_node_name) == 0)
547c7cf2933SEtienne Carriere 			return &regulators_table[i];
548c7cf2933SEtienne Carriere 
549c7cf2933SEtienne Carriere 	/* Regulator not found */
550c7cf2933SEtienne Carriere 	panic(name);
551c7cf2933SEtienne Carriere }
552c7cf2933SEtienne Carriere 
553c7cf2933SEtienne Carriere static uint8_t voltage_to_index(const char *name, uint16_t millivolts)
554c7cf2933SEtienne Carriere {
555c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
556c7cf2933SEtienne Carriere 	unsigned int i = 0;
557c7cf2933SEtienne Carriere 
558c7cf2933SEtienne Carriere 	assert(regul->voltage_table);
559c7cf2933SEtienne Carriere 	for (i = 0; i < regul->voltage_table_size; i++)
560c7cf2933SEtienne Carriere 		if (regul->voltage_table[i] == millivolts)
561c7cf2933SEtienne Carriere 			return i;
562c7cf2933SEtienne Carriere 
563c7cf2933SEtienne Carriere 	/* Voltage not found */
564c7cf2933SEtienne Carriere 	panic(name);
565c7cf2933SEtienne Carriere }
566c7cf2933SEtienne Carriere 
567c7cf2933SEtienne Carriere int stpmic1_powerctrl_on(void)
568c7cf2933SEtienne Carriere {
569c7cf2933SEtienne Carriere 	return stpmic1_register_update(MAIN_CONTROL_REG, PWRCTRL_PIN_VALID,
570c7cf2933SEtienne Carriere 				       PWRCTRL_PIN_VALID);
571c7cf2933SEtienne Carriere }
572c7cf2933SEtienne Carriere 
573c7cf2933SEtienne Carriere int stpmic1_switch_off(void)
574c7cf2933SEtienne Carriere {
575c7cf2933SEtienne Carriere 	return stpmic1_register_update(MAIN_CONTROL_REG, 1,
576c7cf2933SEtienne Carriere 				       SOFTWARE_SWITCH_OFF_ENABLED);
577c7cf2933SEtienne Carriere }
578c7cf2933SEtienne Carriere 
579c7cf2933SEtienne Carriere int stpmic1_regulator_enable(const char *name)
580c7cf2933SEtienne Carriere {
581c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
582c7cf2933SEtienne Carriere 
583c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg, BIT(0), BIT(0));
584c7cf2933SEtienne Carriere }
585c7cf2933SEtienne Carriere 
586c7cf2933SEtienne Carriere int stpmic1_regulator_disable(const char *name)
587c7cf2933SEtienne Carriere {
588c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
589c7cf2933SEtienne Carriere 
590c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg, 0, BIT(0));
591c7cf2933SEtienne Carriere }
592c7cf2933SEtienne Carriere 
593c7cf2933SEtienne Carriere uint8_t stpmic1_is_regulator_enabled(const char *name)
594c7cf2933SEtienne Carriere {
595c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
596c7cf2933SEtienne Carriere 	uint8_t val = 0;
597c7cf2933SEtienne Carriere 
598c7cf2933SEtienne Carriere 	if (stpmic1_register_read(regul->control_reg, &val))
599c7cf2933SEtienne Carriere 		panic();
600c7cf2933SEtienne Carriere 
601c7cf2933SEtienne Carriere 	return val & 0x1;
602c7cf2933SEtienne Carriere }
603c7cf2933SEtienne Carriere 
604c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts)
605c7cf2933SEtienne Carriere {
606c7cf2933SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
607c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
608c7cf2933SEtienne Carriere 	uint8_t mask = 0;
609c7cf2933SEtienne Carriere 
610c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
611c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
612c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
613c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
614c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
615c7cf2933SEtienne Carriere 	else
616c7cf2933SEtienne Carriere 		return 0;
617c7cf2933SEtienne Carriere 
618c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->control_reg,
619c7cf2933SEtienne Carriere 				       voltage_index << LDO_BUCK_VOLTAGE_SHIFT,
620c7cf2933SEtienne Carriere 				       mask);
621c7cf2933SEtienne Carriere }
622c7cf2933SEtienne Carriere 
623c7cf2933SEtienne Carriere int stpmic1_regulator_mask_reset_set(const char *name)
624c7cf2933SEtienne Carriere {
625c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
626c7cf2933SEtienne Carriere 
627c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->mask_reset_reg,
628c7cf2933SEtienne Carriere 				       BIT(regul->mask_reset_pos),
629c7cf2933SEtienne Carriere 				       LDO_BUCK_RESET_MASK <<
630c7cf2933SEtienne Carriere 				       regul->mask_reset_pos);
631c7cf2933SEtienne Carriere }
632c7cf2933SEtienne Carriere 
633*eb5d5313SEtienne Carriere int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg)
634*eb5d5313SEtienne Carriere {
635*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->ctrl_reg, BIT(0), BIT(0));
636*eb5d5313SEtienne Carriere }
637*eb5d5313SEtienne Carriere 
638*eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */
639*eb5d5313SEtienne Carriere int stpmic1_bo_voltage_cfg(const char *name, uint16_t millivolts,
640*eb5d5313SEtienne Carriere 			   struct stpmic1_bo_cfg *cfg)
641*eb5d5313SEtienne Carriere {
642*eb5d5313SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
643*eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
644*eb5d5313SEtienne Carriere 	uint8_t mask = 0;
645*eb5d5313SEtienne Carriere 
646*eb5d5313SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
647*eb5d5313SEtienne Carriere 	if (!strcmp(name, "buck"))
648*eb5d5313SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
649*eb5d5313SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
650*eb5d5313SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
651*eb5d5313SEtienne Carriere 	else
652*eb5d5313SEtienne Carriere 		return 1;
653*eb5d5313SEtienne Carriere 
654*eb5d5313SEtienne Carriere 	cfg->ctrl_reg = regul->control_reg;
655*eb5d5313SEtienne Carriere 	cfg->value = voltage_index << LDO_BUCK_VOLTAGE_SHIFT;
656*eb5d5313SEtienne Carriere 	cfg->mask = mask;
657*eb5d5313SEtienne Carriere 
658*eb5d5313SEtienne Carriere 	return 0;
659*eb5d5313SEtienne Carriere }
660*eb5d5313SEtienne Carriere 
661*eb5d5313SEtienne Carriere int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg)
662*eb5d5313SEtienne Carriere {
663*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->ctrl_reg, cfg->value, cfg->mask);
664*eb5d5313SEtienne Carriere }
665*eb5d5313SEtienne Carriere 
666*eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_cfg(const char *name, struct stpmic1_bo_cfg *cfg)
667*eb5d5313SEtienne Carriere {
668*eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
669*eb5d5313SEtienne Carriere 
670*eb5d5313SEtienne Carriere 	cfg->pd_reg = regul->pull_down_reg;
671*eb5d5313SEtienne Carriere 	cfg->pd_value = BIT(regul->pull_down_pos);
672*eb5d5313SEtienne Carriere 	cfg->pd_mask = LDO_BUCK_PULL_DOWN_MASK << regul->pull_down_pos;
673*eb5d5313SEtienne Carriere 
674*eb5d5313SEtienne Carriere 	return 0;
675*eb5d5313SEtienne Carriere }
676*eb5d5313SEtienne Carriere 
677*eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg)
678*eb5d5313SEtienne Carriere {
679*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->pd_reg, cfg->pd_value,
680*eb5d5313SEtienne Carriere 				       cfg->pd_mask);
681*eb5d5313SEtienne Carriere }
682*eb5d5313SEtienne Carriere 
683*eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg)
684*eb5d5313SEtienne Carriere {
685*eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
686*eb5d5313SEtienne Carriere 
687*eb5d5313SEtienne Carriere 	cfg->mrst_reg = regul->mask_reset_reg;
688*eb5d5313SEtienne Carriere 	cfg->mrst_value = BIT(regul->mask_reset_pos);
689*eb5d5313SEtienne Carriere 	cfg->mrst_mask = LDO_BUCK_RESET_MASK << regul->mask_reset_pos;
690*eb5d5313SEtienne Carriere 
691*eb5d5313SEtienne Carriere 	return 0;
692*eb5d5313SEtienne Carriere }
693*eb5d5313SEtienne Carriere 
694*eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg)
695*eb5d5313SEtienne Carriere {
696*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value,
697*eb5d5313SEtienne Carriere 				       cfg->mrst_mask);
698*eb5d5313SEtienne Carriere }
699*eb5d5313SEtienne Carriere 
700c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_get(const char *name)
701c7cf2933SEtienne Carriere {
702c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
703c7cf2933SEtienne Carriere 	uint8_t value = 0;
704c7cf2933SEtienne Carriere 	uint8_t mask = 0;
705c7cf2933SEtienne Carriere 
706c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
707c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
708c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
709c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
710c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
711c7cf2933SEtienne Carriere 	else
712c7cf2933SEtienne Carriere 		return 0;
713c7cf2933SEtienne Carriere 
714c7cf2933SEtienne Carriere 	if (stpmic1_register_read(regul->control_reg, &value))
715c7cf2933SEtienne Carriere 		return -1;
716c7cf2933SEtienne Carriere 
717c7cf2933SEtienne Carriere 	value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT;
718c7cf2933SEtienne Carriere 
719c7cf2933SEtienne Carriere 	if (value > regul->voltage_table_size)
720c7cf2933SEtienne Carriere 		return -1;
721c7cf2933SEtienne Carriere 
722c7cf2933SEtienne Carriere 	return regul->voltage_table[value];
723c7cf2933SEtienne Carriere }
724c7cf2933SEtienne Carriere 
725c7cf2933SEtienne Carriere int stpmic1_lp_copy_reg(const char *name)
726c7cf2933SEtienne Carriere {
727c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
728c7cf2933SEtienne Carriere 	uint8_t val = 0;
729c7cf2933SEtienne Carriere 	int status = 0;
730c7cf2933SEtienne Carriere 
731c7cf2933SEtienne Carriere 	status = stpmic1_register_read(regul->control_reg, &val);
732c7cf2933SEtienne Carriere 	if (status)
733c7cf2933SEtienne Carriere 		return status;
734c7cf2933SEtienne Carriere 
735c7cf2933SEtienne Carriere 	return stpmic1_register_write(regul->low_power_reg, val);
736c7cf2933SEtienne Carriere }
737c7cf2933SEtienne Carriere 
738*eb5d5313SEtienne Carriere int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg)
739*eb5d5313SEtienne Carriere {
740*eb5d5313SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
741*eb5d5313SEtienne Carriere 
742*eb5d5313SEtienne Carriere 	cfg->ctrl_reg = regul->control_reg;
743*eb5d5313SEtienne Carriere 	cfg->lp_reg = regul->low_power_reg;
744*eb5d5313SEtienne Carriere 
745*eb5d5313SEtienne Carriere 	return 0;
746*eb5d5313SEtienne Carriere }
747*eb5d5313SEtienne Carriere 
748*eb5d5313SEtienne Carriere int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg)
749*eb5d5313SEtienne Carriere {
750*eb5d5313SEtienne Carriere 	uint8_t val = 0;
751*eb5d5313SEtienne Carriere 	int status = 0;
752*eb5d5313SEtienne Carriere 
753*eb5d5313SEtienne Carriere 	status = stpmic1_register_read(cfg->ctrl_reg, &val);
754*eb5d5313SEtienne Carriere 	if (!status)
755*eb5d5313SEtienne Carriere 		status = stpmic1_register_write(cfg->lp_reg, val);
756*eb5d5313SEtienne Carriere 
757*eb5d5313SEtienne Carriere 	return status;
758*eb5d5313SEtienne Carriere }
759*eb5d5313SEtienne Carriere 
760c7cf2933SEtienne Carriere int stpmic1_lp_reg_on_off(const char *name, uint8_t enable)
761c7cf2933SEtienne Carriere {
762c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
763c7cf2933SEtienne Carriere 
764c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg, enable,
765c7cf2933SEtienne Carriere 				       LDO_BUCK_ENABLE_MASK);
766c7cf2933SEtienne Carriere }
767c7cf2933SEtienne Carriere 
768*eb5d5313SEtienne Carriere int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable)
769*eb5d5313SEtienne Carriere {
770*eb5d5313SEtienne Carriere 	assert(enable == 0 || enable == 1);
771*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg, enable,
772*eb5d5313SEtienne Carriere 				       LDO_BUCK_ENABLE_MASK);
773*eb5d5313SEtienne Carriere }
774*eb5d5313SEtienne Carriere 
775c7cf2933SEtienne Carriere int stpmic1_lp_set_mode(const char *name, uint8_t hplp)
776c7cf2933SEtienne Carriere {
777c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
778c7cf2933SEtienne Carriere 
779c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg,
780c7cf2933SEtienne Carriere 				       hplp << LDO_BUCK_HPLP_SHIFT,
781c7cf2933SEtienne Carriere 				       LDO_BUCK_HPLP_ENABLE_MASK);
782c7cf2933SEtienne Carriere }
783c7cf2933SEtienne Carriere 
784*eb5d5313SEtienne Carriere int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg, unsigned int mode)
785*eb5d5313SEtienne Carriere {
786*eb5d5313SEtienne Carriere 	assert(mode == 0 || mode == 1);
787*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg,
788*eb5d5313SEtienne Carriere 				       mode << LDO_BUCK_HPLP_SHIFT,
789*eb5d5313SEtienne Carriere 				       LDO_BUCK_HPLP_ENABLE_MASK);
790*eb5d5313SEtienne Carriere }
791*eb5d5313SEtienne Carriere 
792c7cf2933SEtienne Carriere int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts)
793c7cf2933SEtienne Carriere {
794c7cf2933SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
795c7cf2933SEtienne Carriere 	const struct regul_struct *regul = get_regulator_data(name);
796c7cf2933SEtienne Carriere 	uint8_t mask = 0;
797c7cf2933SEtienne Carriere 
798c7cf2933SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
799c7cf2933SEtienne Carriere 	if (!strcmp(name, "buck"))
800c7cf2933SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
801c7cf2933SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
802c7cf2933SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
803c7cf2933SEtienne Carriere 	else
804c7cf2933SEtienne Carriere 		return 0;
805c7cf2933SEtienne Carriere 
806c7cf2933SEtienne Carriere 	return stpmic1_register_update(regul->low_power_reg, voltage_index << 2,
807c7cf2933SEtienne Carriere 				       mask);
808c7cf2933SEtienne Carriere }
809c7cf2933SEtienne Carriere 
810*eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */
811*eb5d5313SEtienne Carriere int stpmic1_lp_voltage_cfg(const char *name, uint16_t millivolts,
812*eb5d5313SEtienne Carriere 			   struct stpmic1_lp_cfg *cfg)
813*eb5d5313SEtienne Carriere 
814*eb5d5313SEtienne Carriere {
815*eb5d5313SEtienne Carriere 	uint8_t voltage_index = voltage_to_index(name, millivolts);
816*eb5d5313SEtienne Carriere 	uint8_t mask = 0;
817*eb5d5313SEtienne Carriere 
818*eb5d5313SEtienne Carriere 	/* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */
819*eb5d5313SEtienne Carriere 	if (!strcmp(name, "buck"))
820*eb5d5313SEtienne Carriere 		mask = BUCK_VOLTAGE_MASK;
821*eb5d5313SEtienne Carriere 	else if (!strcmp(name, "ldo") && strcmp(name, "ldo4"))
822*eb5d5313SEtienne Carriere 		mask = LDO_VOLTAGE_MASK;
823*eb5d5313SEtienne Carriere 	else
824*eb5d5313SEtienne Carriere 		return 1;
825*eb5d5313SEtienne Carriere 
826*eb5d5313SEtienne Carriere 	assert(cfg->lp_reg == get_regulator_data(name)->low_power_reg);
827*eb5d5313SEtienne Carriere 	cfg->value = voltage_index << 2;
828*eb5d5313SEtienne Carriere 	cfg->mask = mask;
829*eb5d5313SEtienne Carriere 
830*eb5d5313SEtienne Carriere 	return 0;
831*eb5d5313SEtienne Carriere }
832*eb5d5313SEtienne Carriere 
833*eb5d5313SEtienne Carriere int stpmic1_lp_voltage_unpg(struct stpmic1_lp_cfg *cfg)
834*eb5d5313SEtienne Carriere {
835*eb5d5313SEtienne Carriere 	return stpmic1_register_update(cfg->lp_reg, cfg->value,	cfg->mask);
836*eb5d5313SEtienne Carriere }
837*eb5d5313SEtienne Carriere 
838c7cf2933SEtienne Carriere int stpmic1_register_read(uint8_t register_id,  uint8_t *value)
839c7cf2933SEtienne Carriere {
840c7cf2933SEtienne Carriere 	struct i2c_handle_s *i2c = pmic_i2c_handle;
841c7cf2933SEtienne Carriere 
842*eb5d5313SEtienne Carriere 	return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr,
843*eb5d5313SEtienne Carriere 					    register_id, value,
844*eb5d5313SEtienne Carriere 					    false /* !write */);
845c7cf2933SEtienne Carriere }
846c7cf2933SEtienne Carriere 
847c7cf2933SEtienne Carriere int stpmic1_register_write(uint8_t register_id, uint8_t value)
848c7cf2933SEtienne Carriere {
849c7cf2933SEtienne Carriere 	struct i2c_handle_s *i2c = pmic_i2c_handle;
850c7cf2933SEtienne Carriere 	uint8_t val = value;
851c7cf2933SEtienne Carriere 
852*eb5d5313SEtienne Carriere 	return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr,
853*eb5d5313SEtienne Carriere 					    register_id, &val,
854*eb5d5313SEtienne Carriere 					    true /* write */);
855c7cf2933SEtienne Carriere }
856c7cf2933SEtienne Carriere 
857c7cf2933SEtienne Carriere int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask)
858c7cf2933SEtienne Carriere {
859c7cf2933SEtienne Carriere 	int status = 0;
860c7cf2933SEtienne Carriere 	uint8_t val = 0;
861c7cf2933SEtienne Carriere 
862c7cf2933SEtienne Carriere 	status = stpmic1_register_read(register_id, &val);
863c7cf2933SEtienne Carriere 	if (status)
864c7cf2933SEtienne Carriere 		return status;
865c7cf2933SEtienne Carriere 
866c7cf2933SEtienne Carriere 	val = (val & ~mask) | (value & mask);
867c7cf2933SEtienne Carriere 
868c7cf2933SEtienne Carriere 	return stpmic1_register_write(register_id, val);
869c7cf2933SEtienne Carriere }
870c7cf2933SEtienne Carriere 
871c7cf2933SEtienne Carriere void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr)
872c7cf2933SEtienne Carriere {
873c7cf2933SEtienne Carriere 	pmic_i2c_handle = i2c_handle;
874c7cf2933SEtienne Carriere 	pmic_i2c_addr = i2c_addr;
875c7cf2933SEtienne Carriere }
876c7cf2933SEtienne Carriere 
877c7cf2933SEtienne Carriere void stpmic1_dump_regulators(void)
878c7cf2933SEtienne Carriere {
879c7cf2933SEtienne Carriere 	size_t i = 0;
880c7cf2933SEtienne Carriere 	char __maybe_unused const *name = NULL;
881c7cf2933SEtienne Carriere 
882c7cf2933SEtienne Carriere 	for (i = 0; i < ARRAY_SIZE(regulators_table); i++) {
883c7cf2933SEtienne Carriere 		if (!regulators_table[i].control_reg)
884c7cf2933SEtienne Carriere 			continue;
885c7cf2933SEtienne Carriere 
886c7cf2933SEtienne Carriere 		name = regulators_table[i].dt_node_name;
887c7cf2933SEtienne Carriere 		DMSG("PMIC regul %s: %sable, %dmV",
888c7cf2933SEtienne Carriere 		     name, stpmic1_is_regulator_enabled(name) ? "en" : "dis",
889c7cf2933SEtienne Carriere 		     stpmic1_regulator_voltage_get(name));
890c7cf2933SEtienne Carriere 	}
891c7cf2933SEtienne Carriere }
892c7cf2933SEtienne Carriere 
893c7cf2933SEtienne Carriere int stpmic1_get_version(unsigned long *version)
894c7cf2933SEtienne Carriere {
895c7cf2933SEtienne Carriere 	uint8_t read_val = 0;
896c7cf2933SEtienne Carriere 
897c7cf2933SEtienne Carriere 	if (stpmic1_register_read(VERSION_STATUS_REG, &read_val))
898c7cf2933SEtienne Carriere 		return -1;
899c7cf2933SEtienne Carriere 
900c7cf2933SEtienne Carriere 	*version = read_val;
901c7cf2933SEtienne Carriere 	return 0;
902c7cf2933SEtienne Carriere }
903