1*c7cf2933SEtienne Carriere // SPDX-License-Identifier: BSD-3-Clause 2*c7cf2933SEtienne Carriere /* 3*c7cf2933SEtienne Carriere * Copyright (c) 2016-2018, STMicroelectronics - All Rights Reserved 4*c7cf2933SEtienne Carriere */ 5*c7cf2933SEtienne Carriere 6*c7cf2933SEtienne Carriere #include <assert.h> 7*c7cf2933SEtienne Carriere #include <drivers/stpmic1.h> 8*c7cf2933SEtienne Carriere #include <kernel/panic.h> 9*c7cf2933SEtienne Carriere #include <platform_config.h> 10*c7cf2933SEtienne Carriere #include <stdint.h> 11*c7cf2933SEtienne Carriere #include <string.h> 12*c7cf2933SEtienne Carriere #include <trace.h> 13*c7cf2933SEtienne Carriere 14*c7cf2933SEtienne Carriere #define STPMIC1_I2C_TIMEOUT_US (10 * 1000) 15*c7cf2933SEtienne Carriere 16*c7cf2933SEtienne Carriere struct regul_struct { 17*c7cf2933SEtienne Carriere const char *dt_node_name; 18*c7cf2933SEtienne Carriere const uint16_t *voltage_table; 19*c7cf2933SEtienne Carriere uint8_t voltage_table_size; 20*c7cf2933SEtienne Carriere uint8_t control_reg; 21*c7cf2933SEtienne Carriere uint8_t low_power_reg; 22*c7cf2933SEtienne Carriere uint8_t pull_down_reg; 23*c7cf2933SEtienne Carriere uint8_t pull_down_pos; 24*c7cf2933SEtienne Carriere uint8_t mask_reset_reg; 25*c7cf2933SEtienne Carriere uint8_t mask_reset_pos; 26*c7cf2933SEtienne Carriere }; 27*c7cf2933SEtienne Carriere 28*c7cf2933SEtienne Carriere static struct i2c_handle_s *pmic_i2c_handle; 29*c7cf2933SEtienne Carriere static uint16_t pmic_i2c_addr; 30*c7cf2933SEtienne Carriere 31*c7cf2933SEtienne Carriere /* Voltage tables in mV */ 32*c7cf2933SEtienne Carriere static const uint16_t buck1_voltage_table[] = { 33*c7cf2933SEtienne Carriere 725, 34*c7cf2933SEtienne Carriere 725, 35*c7cf2933SEtienne Carriere 725, 36*c7cf2933SEtienne Carriere 725, 37*c7cf2933SEtienne Carriere 725, 38*c7cf2933SEtienne Carriere 725, 39*c7cf2933SEtienne Carriere 750, 40*c7cf2933SEtienne Carriere 775, 41*c7cf2933SEtienne Carriere 800, 42*c7cf2933SEtienne Carriere 825, 43*c7cf2933SEtienne Carriere 850, 44*c7cf2933SEtienne Carriere 875, 45*c7cf2933SEtienne Carriere 900, 46*c7cf2933SEtienne Carriere 925, 47*c7cf2933SEtienne Carriere 950, 48*c7cf2933SEtienne Carriere 975, 49*c7cf2933SEtienne Carriere 1000, 50*c7cf2933SEtienne Carriere 1025, 51*c7cf2933SEtienne Carriere 1050, 52*c7cf2933SEtienne Carriere 1075, 53*c7cf2933SEtienne Carriere 1100, 54*c7cf2933SEtienne Carriere 1125, 55*c7cf2933SEtienne Carriere 1150, 56*c7cf2933SEtienne Carriere 1175, 57*c7cf2933SEtienne Carriere 1200, 58*c7cf2933SEtienne Carriere 1225, 59*c7cf2933SEtienne Carriere 1250, 60*c7cf2933SEtienne Carriere 1275, 61*c7cf2933SEtienne Carriere 1300, 62*c7cf2933SEtienne Carriere 1325, 63*c7cf2933SEtienne Carriere 1350, 64*c7cf2933SEtienne Carriere 1375, 65*c7cf2933SEtienne Carriere 1400, 66*c7cf2933SEtienne Carriere 1425, 67*c7cf2933SEtienne Carriere 1450, 68*c7cf2933SEtienne Carriere 1475, 69*c7cf2933SEtienne Carriere 1500, 70*c7cf2933SEtienne Carriere 1500, 71*c7cf2933SEtienne Carriere 1500, 72*c7cf2933SEtienne Carriere 1500, 73*c7cf2933SEtienne Carriere 1500, 74*c7cf2933SEtienne Carriere 1500, 75*c7cf2933SEtienne Carriere 1500, 76*c7cf2933SEtienne Carriere 1500, 77*c7cf2933SEtienne Carriere 1500, 78*c7cf2933SEtienne Carriere 1500, 79*c7cf2933SEtienne Carriere 1500, 80*c7cf2933SEtienne Carriere 1500, 81*c7cf2933SEtienne Carriere 1500, 82*c7cf2933SEtienne Carriere 1500, 83*c7cf2933SEtienne Carriere 1500, 84*c7cf2933SEtienne Carriere 1500, 85*c7cf2933SEtienne Carriere 1500, 86*c7cf2933SEtienne Carriere 1500, 87*c7cf2933SEtienne Carriere 1500, 88*c7cf2933SEtienne Carriere 1500, 89*c7cf2933SEtienne Carriere 1500, 90*c7cf2933SEtienne Carriere 1500, 91*c7cf2933SEtienne Carriere 1500, 92*c7cf2933SEtienne Carriere 1500, 93*c7cf2933SEtienne Carriere 1500, 94*c7cf2933SEtienne Carriere 1500, 95*c7cf2933SEtienne Carriere 1500, 96*c7cf2933SEtienne Carriere 1500, 97*c7cf2933SEtienne Carriere }; 98*c7cf2933SEtienne Carriere 99*c7cf2933SEtienne Carriere static const uint16_t buck2_voltage_table[] = { 100*c7cf2933SEtienne Carriere 1000, 101*c7cf2933SEtienne Carriere 1000, 102*c7cf2933SEtienne Carriere 1000, 103*c7cf2933SEtienne Carriere 1000, 104*c7cf2933SEtienne Carriere 1000, 105*c7cf2933SEtienne Carriere 1000, 106*c7cf2933SEtienne Carriere 1000, 107*c7cf2933SEtienne Carriere 1000, 108*c7cf2933SEtienne Carriere 1000, 109*c7cf2933SEtienne Carriere 1000, 110*c7cf2933SEtienne Carriere 1000, 111*c7cf2933SEtienne Carriere 1000, 112*c7cf2933SEtienne Carriere 1000, 113*c7cf2933SEtienne Carriere 1000, 114*c7cf2933SEtienne Carriere 1000, 115*c7cf2933SEtienne Carriere 1000, 116*c7cf2933SEtienne Carriere 1000, 117*c7cf2933SEtienne Carriere 1000, 118*c7cf2933SEtienne Carriere 1050, 119*c7cf2933SEtienne Carriere 1050, 120*c7cf2933SEtienne Carriere 1100, 121*c7cf2933SEtienne Carriere 1100, 122*c7cf2933SEtienne Carriere 1150, 123*c7cf2933SEtienne Carriere 1150, 124*c7cf2933SEtienne Carriere 1200, 125*c7cf2933SEtienne Carriere 1200, 126*c7cf2933SEtienne Carriere 1250, 127*c7cf2933SEtienne Carriere 1250, 128*c7cf2933SEtienne Carriere 1300, 129*c7cf2933SEtienne Carriere 1300, 130*c7cf2933SEtienne Carriere 1350, 131*c7cf2933SEtienne Carriere 1350, 132*c7cf2933SEtienne Carriere 1400, 133*c7cf2933SEtienne Carriere 1400, 134*c7cf2933SEtienne Carriere 1450, 135*c7cf2933SEtienne Carriere 1450, 136*c7cf2933SEtienne Carriere 1500, 137*c7cf2933SEtienne Carriere }; 138*c7cf2933SEtienne Carriere 139*c7cf2933SEtienne Carriere static const uint16_t buck3_voltage_table[] = { 140*c7cf2933SEtienne Carriere 1000, 141*c7cf2933SEtienne Carriere 1000, 142*c7cf2933SEtienne Carriere 1000, 143*c7cf2933SEtienne Carriere 1000, 144*c7cf2933SEtienne Carriere 1000, 145*c7cf2933SEtienne Carriere 1000, 146*c7cf2933SEtienne Carriere 1000, 147*c7cf2933SEtienne Carriere 1000, 148*c7cf2933SEtienne Carriere 1000, 149*c7cf2933SEtienne Carriere 1000, 150*c7cf2933SEtienne Carriere 1000, 151*c7cf2933SEtienne Carriere 1000, 152*c7cf2933SEtienne Carriere 1000, 153*c7cf2933SEtienne Carriere 1000, 154*c7cf2933SEtienne Carriere 1000, 155*c7cf2933SEtienne Carriere 1000, 156*c7cf2933SEtienne Carriere 1000, 157*c7cf2933SEtienne Carriere 1000, 158*c7cf2933SEtienne Carriere 1000, 159*c7cf2933SEtienne Carriere 1000, 160*c7cf2933SEtienne Carriere 1100, 161*c7cf2933SEtienne Carriere 1100, 162*c7cf2933SEtienne Carriere 1100, 163*c7cf2933SEtienne Carriere 1100, 164*c7cf2933SEtienne Carriere 1200, 165*c7cf2933SEtienne Carriere 1200, 166*c7cf2933SEtienne Carriere 1200, 167*c7cf2933SEtienne Carriere 1200, 168*c7cf2933SEtienne Carriere 1300, 169*c7cf2933SEtienne Carriere 1300, 170*c7cf2933SEtienne Carriere 1300, 171*c7cf2933SEtienne Carriere 1300, 172*c7cf2933SEtienne Carriere 1400, 173*c7cf2933SEtienne Carriere 1400, 174*c7cf2933SEtienne Carriere 1400, 175*c7cf2933SEtienne Carriere 1400, 176*c7cf2933SEtienne Carriere 1500, 177*c7cf2933SEtienne Carriere 1600, 178*c7cf2933SEtienne Carriere 1700, 179*c7cf2933SEtienne Carriere 1800, 180*c7cf2933SEtienne Carriere 1900, 181*c7cf2933SEtienne Carriere 2000, 182*c7cf2933SEtienne Carriere 2100, 183*c7cf2933SEtienne Carriere 2200, 184*c7cf2933SEtienne Carriere 2300, 185*c7cf2933SEtienne Carriere 2400, 186*c7cf2933SEtienne Carriere 2500, 187*c7cf2933SEtienne Carriere 2600, 188*c7cf2933SEtienne Carriere 2700, 189*c7cf2933SEtienne Carriere 2800, 190*c7cf2933SEtienne Carriere 2900, 191*c7cf2933SEtienne Carriere 3000, 192*c7cf2933SEtienne Carriere 3100, 193*c7cf2933SEtienne Carriere 3200, 194*c7cf2933SEtienne Carriere 3300, 195*c7cf2933SEtienne Carriere 3400, 196*c7cf2933SEtienne Carriere }; 197*c7cf2933SEtienne Carriere 198*c7cf2933SEtienne Carriere static const uint16_t buck4_voltage_table[] = { 199*c7cf2933SEtienne Carriere 600, 200*c7cf2933SEtienne Carriere 625, 201*c7cf2933SEtienne Carriere 650, 202*c7cf2933SEtienne Carriere 675, 203*c7cf2933SEtienne Carriere 700, 204*c7cf2933SEtienne Carriere 725, 205*c7cf2933SEtienne Carriere 750, 206*c7cf2933SEtienne Carriere 775, 207*c7cf2933SEtienne Carriere 800, 208*c7cf2933SEtienne Carriere 825, 209*c7cf2933SEtienne Carriere 850, 210*c7cf2933SEtienne Carriere 875, 211*c7cf2933SEtienne Carriere 900, 212*c7cf2933SEtienne Carriere 925, 213*c7cf2933SEtienne Carriere 950, 214*c7cf2933SEtienne Carriere 975, 215*c7cf2933SEtienne Carriere 1000, 216*c7cf2933SEtienne Carriere 1025, 217*c7cf2933SEtienne Carriere 1050, 218*c7cf2933SEtienne Carriere 1075, 219*c7cf2933SEtienne Carriere 1100, 220*c7cf2933SEtienne Carriere 1125, 221*c7cf2933SEtienne Carriere 1150, 222*c7cf2933SEtienne Carriere 1175, 223*c7cf2933SEtienne Carriere 1200, 224*c7cf2933SEtienne Carriere 1225, 225*c7cf2933SEtienne Carriere 1250, 226*c7cf2933SEtienne Carriere 1275, 227*c7cf2933SEtienne Carriere 1300, 228*c7cf2933SEtienne Carriere 1300, 229*c7cf2933SEtienne Carriere 1350, 230*c7cf2933SEtienne Carriere 1350, 231*c7cf2933SEtienne Carriere 1400, 232*c7cf2933SEtienne Carriere 1400, 233*c7cf2933SEtienne Carriere 1450, 234*c7cf2933SEtienne Carriere 1450, 235*c7cf2933SEtienne Carriere 1500, 236*c7cf2933SEtienne Carriere 1600, 237*c7cf2933SEtienne Carriere 1700, 238*c7cf2933SEtienne Carriere 1800, 239*c7cf2933SEtienne Carriere 1900, 240*c7cf2933SEtienne Carriere 2000, 241*c7cf2933SEtienne Carriere 2100, 242*c7cf2933SEtienne Carriere 2200, 243*c7cf2933SEtienne Carriere 2300, 244*c7cf2933SEtienne Carriere 2400, 245*c7cf2933SEtienne Carriere 2500, 246*c7cf2933SEtienne Carriere 2600, 247*c7cf2933SEtienne Carriere 2700, 248*c7cf2933SEtienne Carriere 2800, 249*c7cf2933SEtienne Carriere 2900, 250*c7cf2933SEtienne Carriere 3000, 251*c7cf2933SEtienne Carriere 3100, 252*c7cf2933SEtienne Carriere 3200, 253*c7cf2933SEtienne Carriere 3300, 254*c7cf2933SEtienne Carriere 3400, 255*c7cf2933SEtienne Carriere 3500, 256*c7cf2933SEtienne Carriere 3600, 257*c7cf2933SEtienne Carriere 3700, 258*c7cf2933SEtienne Carriere 3800, 259*c7cf2933SEtienne Carriere 3900, 260*c7cf2933SEtienne Carriere }; 261*c7cf2933SEtienne Carriere 262*c7cf2933SEtienne Carriere static const uint16_t ldo1_voltage_table[] = { 263*c7cf2933SEtienne Carriere 1700, 264*c7cf2933SEtienne Carriere 1700, 265*c7cf2933SEtienne Carriere 1700, 266*c7cf2933SEtienne Carriere 1700, 267*c7cf2933SEtienne Carriere 1700, 268*c7cf2933SEtienne Carriere 1700, 269*c7cf2933SEtienne Carriere 1700, 270*c7cf2933SEtienne Carriere 1700, 271*c7cf2933SEtienne Carriere 1700, 272*c7cf2933SEtienne Carriere 1800, 273*c7cf2933SEtienne Carriere 1900, 274*c7cf2933SEtienne Carriere 2000, 275*c7cf2933SEtienne Carriere 2100, 276*c7cf2933SEtienne Carriere 2200, 277*c7cf2933SEtienne Carriere 2300, 278*c7cf2933SEtienne Carriere 2400, 279*c7cf2933SEtienne Carriere 2500, 280*c7cf2933SEtienne Carriere 2600, 281*c7cf2933SEtienne Carriere 2700, 282*c7cf2933SEtienne Carriere 2800, 283*c7cf2933SEtienne Carriere 2900, 284*c7cf2933SEtienne Carriere 3000, 285*c7cf2933SEtienne Carriere 3100, 286*c7cf2933SEtienne Carriere 3200, 287*c7cf2933SEtienne Carriere 3300, 288*c7cf2933SEtienne Carriere }; 289*c7cf2933SEtienne Carriere 290*c7cf2933SEtienne Carriere static const uint16_t ldo2_voltage_table[] = { 291*c7cf2933SEtienne Carriere 1700, 292*c7cf2933SEtienne Carriere 1700, 293*c7cf2933SEtienne Carriere 1700, 294*c7cf2933SEtienne Carriere 1700, 295*c7cf2933SEtienne Carriere 1700, 296*c7cf2933SEtienne Carriere 1700, 297*c7cf2933SEtienne Carriere 1700, 298*c7cf2933SEtienne Carriere 1700, 299*c7cf2933SEtienne Carriere 1700, 300*c7cf2933SEtienne Carriere 1800, 301*c7cf2933SEtienne Carriere 1900, 302*c7cf2933SEtienne Carriere 2000, 303*c7cf2933SEtienne Carriere 2100, 304*c7cf2933SEtienne Carriere 2200, 305*c7cf2933SEtienne Carriere 2300, 306*c7cf2933SEtienne Carriere 2400, 307*c7cf2933SEtienne Carriere 2500, 308*c7cf2933SEtienne Carriere 2600, 309*c7cf2933SEtienne Carriere 2700, 310*c7cf2933SEtienne Carriere 2800, 311*c7cf2933SEtienne Carriere 2900, 312*c7cf2933SEtienne Carriere 3000, 313*c7cf2933SEtienne Carriere 3100, 314*c7cf2933SEtienne Carriere 3200, 315*c7cf2933SEtienne Carriere 3300, 316*c7cf2933SEtienne Carriere }; 317*c7cf2933SEtienne Carriere 318*c7cf2933SEtienne Carriere static const uint16_t ldo3_voltage_table[] = { 319*c7cf2933SEtienne Carriere 1700, 320*c7cf2933SEtienne Carriere 1700, 321*c7cf2933SEtienne Carriere 1700, 322*c7cf2933SEtienne Carriere 1700, 323*c7cf2933SEtienne Carriere 1700, 324*c7cf2933SEtienne Carriere 1700, 325*c7cf2933SEtienne Carriere 1700, 326*c7cf2933SEtienne Carriere 1700, 327*c7cf2933SEtienne Carriere 1700, 328*c7cf2933SEtienne Carriere 1800, 329*c7cf2933SEtienne Carriere 1900, 330*c7cf2933SEtienne Carriere 2000, 331*c7cf2933SEtienne Carriere 2100, 332*c7cf2933SEtienne Carriere 2200, 333*c7cf2933SEtienne Carriere 2300, 334*c7cf2933SEtienne Carriere 2400, 335*c7cf2933SEtienne Carriere 2500, 336*c7cf2933SEtienne Carriere 2600, 337*c7cf2933SEtienne Carriere 2700, 338*c7cf2933SEtienne Carriere 2800, 339*c7cf2933SEtienne Carriere 2900, 340*c7cf2933SEtienne Carriere 3000, 341*c7cf2933SEtienne Carriere 3100, 342*c7cf2933SEtienne Carriere 3200, 343*c7cf2933SEtienne Carriere 3300, 344*c7cf2933SEtienne Carriere 3300, 345*c7cf2933SEtienne Carriere 3300, 346*c7cf2933SEtienne Carriere 3300, 347*c7cf2933SEtienne Carriere 3300, 348*c7cf2933SEtienne Carriere 3300, 349*c7cf2933SEtienne Carriere 3300, 350*c7cf2933SEtienne Carriere 0xFFFF, /* VREFDDR */ 351*c7cf2933SEtienne Carriere }; 352*c7cf2933SEtienne Carriere 353*c7cf2933SEtienne Carriere static const uint16_t ldo5_voltage_table[] = { 354*c7cf2933SEtienne Carriere 1700, 355*c7cf2933SEtienne Carriere 1700, 356*c7cf2933SEtienne Carriere 1700, 357*c7cf2933SEtienne Carriere 1700, 358*c7cf2933SEtienne Carriere 1700, 359*c7cf2933SEtienne Carriere 1700, 360*c7cf2933SEtienne Carriere 1700, 361*c7cf2933SEtienne Carriere 1700, 362*c7cf2933SEtienne Carriere 1700, 363*c7cf2933SEtienne Carriere 1800, 364*c7cf2933SEtienne Carriere 1900, 365*c7cf2933SEtienne Carriere 2000, 366*c7cf2933SEtienne Carriere 2100, 367*c7cf2933SEtienne Carriere 2200, 368*c7cf2933SEtienne Carriere 2300, 369*c7cf2933SEtienne Carriere 2400, 370*c7cf2933SEtienne Carriere 2500, 371*c7cf2933SEtienne Carriere 2600, 372*c7cf2933SEtienne Carriere 2700, 373*c7cf2933SEtienne Carriere 2800, 374*c7cf2933SEtienne Carriere 2900, 375*c7cf2933SEtienne Carriere 3000, 376*c7cf2933SEtienne Carriere 3100, 377*c7cf2933SEtienne Carriere 3200, 378*c7cf2933SEtienne Carriere 3300, 379*c7cf2933SEtienne Carriere 3400, 380*c7cf2933SEtienne Carriere 3500, 381*c7cf2933SEtienne Carriere 3600, 382*c7cf2933SEtienne Carriere 3700, 383*c7cf2933SEtienne Carriere 3800, 384*c7cf2933SEtienne Carriere 3900, 385*c7cf2933SEtienne Carriere }; 386*c7cf2933SEtienne Carriere 387*c7cf2933SEtienne Carriere static const uint16_t ldo6_voltage_table[] = { 388*c7cf2933SEtienne Carriere 900, 389*c7cf2933SEtienne Carriere 1000, 390*c7cf2933SEtienne Carriere 1100, 391*c7cf2933SEtienne Carriere 1200, 392*c7cf2933SEtienne Carriere 1300, 393*c7cf2933SEtienne Carriere 1400, 394*c7cf2933SEtienne Carriere 1500, 395*c7cf2933SEtienne Carriere 1600, 396*c7cf2933SEtienne Carriere 1700, 397*c7cf2933SEtienne Carriere 1800, 398*c7cf2933SEtienne Carriere 1900, 399*c7cf2933SEtienne Carriere 2000, 400*c7cf2933SEtienne Carriere 2100, 401*c7cf2933SEtienne Carriere 2200, 402*c7cf2933SEtienne Carriere 2300, 403*c7cf2933SEtienne Carriere 2400, 404*c7cf2933SEtienne Carriere 2500, 405*c7cf2933SEtienne Carriere 2600, 406*c7cf2933SEtienne Carriere 2700, 407*c7cf2933SEtienne Carriere 2800, 408*c7cf2933SEtienne Carriere 2900, 409*c7cf2933SEtienne Carriere 3000, 410*c7cf2933SEtienne Carriere 3100, 411*c7cf2933SEtienne Carriere 3200, 412*c7cf2933SEtienne Carriere 3300, 413*c7cf2933SEtienne Carriere }; 414*c7cf2933SEtienne Carriere 415*c7cf2933SEtienne Carriere static const uint16_t ldo4_voltage_table[] = { 416*c7cf2933SEtienne Carriere 3300, 417*c7cf2933SEtienne Carriere }; 418*c7cf2933SEtienne Carriere 419*c7cf2933SEtienne Carriere static const uint16_t vref_ddr_voltage_table[] = { 420*c7cf2933SEtienne Carriere 3300, 421*c7cf2933SEtienne Carriere }; 422*c7cf2933SEtienne Carriere 423*c7cf2933SEtienne Carriere /* Table of Regulators in PMIC SoC */ 424*c7cf2933SEtienne Carriere static const struct regul_struct regulators_table[] = { 425*c7cf2933SEtienne Carriere { 426*c7cf2933SEtienne Carriere .dt_node_name = "buck1", 427*c7cf2933SEtienne Carriere .voltage_table = buck1_voltage_table, 428*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck1_voltage_table), 429*c7cf2933SEtienne Carriere .control_reg = BUCK1_CONTROL_REG, 430*c7cf2933SEtienne Carriere .low_power_reg = BUCK1_PWRCTRL_REG, 431*c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 432*c7cf2933SEtienne Carriere .pull_down_pos = BUCK1_PULL_DOWN_SHIFT, 433*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 434*c7cf2933SEtienne Carriere .mask_reset_pos = BUCK1_MASK_RESET_SHIFT, 435*c7cf2933SEtienne Carriere }, 436*c7cf2933SEtienne Carriere { 437*c7cf2933SEtienne Carriere .dt_node_name = "buck2", 438*c7cf2933SEtienne Carriere .voltage_table = buck2_voltage_table, 439*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck2_voltage_table), 440*c7cf2933SEtienne Carriere .control_reg = BUCK2_CONTROL_REG, 441*c7cf2933SEtienne Carriere .low_power_reg = BUCK2_PWRCTRL_REG, 442*c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 443*c7cf2933SEtienne Carriere .pull_down_pos = BUCK2_PULL_DOWN_SHIFT, 444*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 445*c7cf2933SEtienne Carriere .mask_reset_pos = BUCK2_MASK_RESET_SHIFT, 446*c7cf2933SEtienne Carriere }, 447*c7cf2933SEtienne Carriere { 448*c7cf2933SEtienne Carriere .dt_node_name = "buck3", 449*c7cf2933SEtienne Carriere .voltage_table = buck3_voltage_table, 450*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck3_voltage_table), 451*c7cf2933SEtienne Carriere .control_reg = BUCK3_CONTROL_REG, 452*c7cf2933SEtienne Carriere .low_power_reg = BUCK3_PWRCTRL_REG, 453*c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 454*c7cf2933SEtienne Carriere .pull_down_pos = BUCK3_PULL_DOWN_SHIFT, 455*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 456*c7cf2933SEtienne Carriere .mask_reset_pos = BUCK3_MASK_RESET_SHIFT, 457*c7cf2933SEtienne Carriere }, 458*c7cf2933SEtienne Carriere { 459*c7cf2933SEtienne Carriere .dt_node_name = "buck4", 460*c7cf2933SEtienne Carriere .voltage_table = buck4_voltage_table, 461*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck4_voltage_table), 462*c7cf2933SEtienne Carriere .control_reg = BUCK4_CONTROL_REG, 463*c7cf2933SEtienne Carriere .low_power_reg = BUCK4_PWRCTRL_REG, 464*c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 465*c7cf2933SEtienne Carriere .pull_down_pos = BUCK4_PULL_DOWN_SHIFT, 466*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 467*c7cf2933SEtienne Carriere .mask_reset_pos = BUCK4_MASK_RESET_SHIFT, 468*c7cf2933SEtienne Carriere }, 469*c7cf2933SEtienne Carriere { 470*c7cf2933SEtienne Carriere .dt_node_name = "ldo1", 471*c7cf2933SEtienne Carriere .voltage_table = ldo1_voltage_table, 472*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table), 473*c7cf2933SEtienne Carriere .control_reg = LDO1_CONTROL_REG, 474*c7cf2933SEtienne Carriere .low_power_reg = LDO1_PWRCTRL_REG, 475*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 476*c7cf2933SEtienne Carriere .mask_reset_pos = LDO1_MASK_RESET_SHIFT, 477*c7cf2933SEtienne Carriere }, 478*c7cf2933SEtienne Carriere { 479*c7cf2933SEtienne Carriere .dt_node_name = "ldo2", 480*c7cf2933SEtienne Carriere .voltage_table = ldo2_voltage_table, 481*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table), 482*c7cf2933SEtienne Carriere .control_reg = LDO2_CONTROL_REG, 483*c7cf2933SEtienne Carriere .low_power_reg = LDO2_PWRCTRL_REG, 484*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 485*c7cf2933SEtienne Carriere .mask_reset_pos = LDO2_MASK_RESET_SHIFT, 486*c7cf2933SEtienne Carriere }, 487*c7cf2933SEtienne Carriere { 488*c7cf2933SEtienne Carriere .dt_node_name = "ldo3", 489*c7cf2933SEtienne Carriere .voltage_table = ldo3_voltage_table, 490*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table), 491*c7cf2933SEtienne Carriere .control_reg = LDO3_CONTROL_REG, 492*c7cf2933SEtienne Carriere .low_power_reg = LDO3_PWRCTRL_REG, 493*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 494*c7cf2933SEtienne Carriere .mask_reset_pos = LDO3_MASK_RESET_SHIFT, 495*c7cf2933SEtienne Carriere }, 496*c7cf2933SEtienne Carriere { 497*c7cf2933SEtienne Carriere .dt_node_name = "ldo4", 498*c7cf2933SEtienne Carriere .voltage_table = ldo4_voltage_table, 499*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table), 500*c7cf2933SEtienne Carriere .control_reg = LDO4_CONTROL_REG, 501*c7cf2933SEtienne Carriere .low_power_reg = LDO4_PWRCTRL_REG, 502*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 503*c7cf2933SEtienne Carriere .mask_reset_pos = LDO4_MASK_RESET_SHIFT, 504*c7cf2933SEtienne Carriere }, 505*c7cf2933SEtienne Carriere { 506*c7cf2933SEtienne Carriere .dt_node_name = "ldo5", 507*c7cf2933SEtienne Carriere .voltage_table = ldo5_voltage_table, 508*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table), 509*c7cf2933SEtienne Carriere .control_reg = LDO5_CONTROL_REG, 510*c7cf2933SEtienne Carriere .low_power_reg = LDO5_PWRCTRL_REG, 511*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 512*c7cf2933SEtienne Carriere .mask_reset_pos = LDO5_MASK_RESET_SHIFT, 513*c7cf2933SEtienne Carriere }, 514*c7cf2933SEtienne Carriere { 515*c7cf2933SEtienne Carriere .dt_node_name = "ldo6", 516*c7cf2933SEtienne Carriere .voltage_table = ldo6_voltage_table, 517*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table), 518*c7cf2933SEtienne Carriere .control_reg = LDO6_CONTROL_REG, 519*c7cf2933SEtienne Carriere .low_power_reg = LDO6_PWRCTRL_REG, 520*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 521*c7cf2933SEtienne Carriere .mask_reset_pos = LDO6_MASK_RESET_SHIFT, 522*c7cf2933SEtienne Carriere }, 523*c7cf2933SEtienne Carriere { 524*c7cf2933SEtienne Carriere .dt_node_name = "vref_ddr", 525*c7cf2933SEtienne Carriere .voltage_table = vref_ddr_voltage_table, 526*c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table), 527*c7cf2933SEtienne Carriere .control_reg = VREF_DDR_CONTROL_REG, 528*c7cf2933SEtienne Carriere .low_power_reg = VREF_DDR_PWRCTRL_REG, 529*c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 530*c7cf2933SEtienne Carriere .mask_reset_pos = VREF_DDR_MASK_RESET_SHIFT, 531*c7cf2933SEtienne Carriere }, 532*c7cf2933SEtienne Carriere { 533*c7cf2933SEtienne Carriere .dt_node_name = "boost", 534*c7cf2933SEtienne Carriere }, 535*c7cf2933SEtienne Carriere { 536*c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw1", 537*c7cf2933SEtienne Carriere }, 538*c7cf2933SEtienne Carriere { 539*c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw2", 540*c7cf2933SEtienne Carriere }, 541*c7cf2933SEtienne Carriere }; 542*c7cf2933SEtienne Carriere 543*c7cf2933SEtienne Carriere static const struct regul_struct *get_regulator_data(const char *name) 544*c7cf2933SEtienne Carriere { 545*c7cf2933SEtienne Carriere unsigned int i = 0; 546*c7cf2933SEtienne Carriere 547*c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) 548*c7cf2933SEtienne Carriere if (strcmp(name, regulators_table[i].dt_node_name) == 0) 549*c7cf2933SEtienne Carriere return ®ulators_table[i]; 550*c7cf2933SEtienne Carriere 551*c7cf2933SEtienne Carriere /* Regulator not found */ 552*c7cf2933SEtienne Carriere panic(name); 553*c7cf2933SEtienne Carriere } 554*c7cf2933SEtienne Carriere 555*c7cf2933SEtienne Carriere static uint8_t voltage_to_index(const char *name, uint16_t millivolts) 556*c7cf2933SEtienne Carriere { 557*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 558*c7cf2933SEtienne Carriere unsigned int i = 0; 559*c7cf2933SEtienne Carriere 560*c7cf2933SEtienne Carriere assert(regul->voltage_table); 561*c7cf2933SEtienne Carriere for (i = 0; i < regul->voltage_table_size; i++) 562*c7cf2933SEtienne Carriere if (regul->voltage_table[i] == millivolts) 563*c7cf2933SEtienne Carriere return i; 564*c7cf2933SEtienne Carriere 565*c7cf2933SEtienne Carriere /* Voltage not found */ 566*c7cf2933SEtienne Carriere panic(name); 567*c7cf2933SEtienne Carriere } 568*c7cf2933SEtienne Carriere 569*c7cf2933SEtienne Carriere int stpmic1_powerctrl_on(void) 570*c7cf2933SEtienne Carriere { 571*c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, PWRCTRL_PIN_VALID, 572*c7cf2933SEtienne Carriere PWRCTRL_PIN_VALID); 573*c7cf2933SEtienne Carriere } 574*c7cf2933SEtienne Carriere 575*c7cf2933SEtienne Carriere int stpmic1_switch_off(void) 576*c7cf2933SEtienne Carriere { 577*c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, 1, 578*c7cf2933SEtienne Carriere SOFTWARE_SWITCH_OFF_ENABLED); 579*c7cf2933SEtienne Carriere } 580*c7cf2933SEtienne Carriere 581*c7cf2933SEtienne Carriere int stpmic1_regulator_enable(const char *name) 582*c7cf2933SEtienne Carriere { 583*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 584*c7cf2933SEtienne Carriere 585*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->control_reg, BIT(0), BIT(0)); 586*c7cf2933SEtienne Carriere } 587*c7cf2933SEtienne Carriere 588*c7cf2933SEtienne Carriere int stpmic1_regulator_disable(const char *name) 589*c7cf2933SEtienne Carriere { 590*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 591*c7cf2933SEtienne Carriere 592*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->control_reg, 0, BIT(0)); 593*c7cf2933SEtienne Carriere } 594*c7cf2933SEtienne Carriere 595*c7cf2933SEtienne Carriere uint8_t stpmic1_is_regulator_enabled(const char *name) 596*c7cf2933SEtienne Carriere { 597*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 598*c7cf2933SEtienne Carriere uint8_t val = 0; 599*c7cf2933SEtienne Carriere 600*c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &val)) 601*c7cf2933SEtienne Carriere panic(); 602*c7cf2933SEtienne Carriere 603*c7cf2933SEtienne Carriere return val & 0x1; 604*c7cf2933SEtienne Carriere } 605*c7cf2933SEtienne Carriere 606*c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts) 607*c7cf2933SEtienne Carriere { 608*c7cf2933SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 609*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 610*c7cf2933SEtienne Carriere uint8_t mask = 0; 611*c7cf2933SEtienne Carriere 612*c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 613*c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 614*c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 615*c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 616*c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 617*c7cf2933SEtienne Carriere else 618*c7cf2933SEtienne Carriere return 0; 619*c7cf2933SEtienne Carriere 620*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->control_reg, 621*c7cf2933SEtienne Carriere voltage_index << LDO_BUCK_VOLTAGE_SHIFT, 622*c7cf2933SEtienne Carriere mask); 623*c7cf2933SEtienne Carriere } 624*c7cf2933SEtienne Carriere 625*c7cf2933SEtienne Carriere int stpmic1_regulator_mask_reset_set(const char *name) 626*c7cf2933SEtienne Carriere { 627*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 628*c7cf2933SEtienne Carriere 629*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->mask_reset_reg, 630*c7cf2933SEtienne Carriere BIT(regul->mask_reset_pos), 631*c7cf2933SEtienne Carriere LDO_BUCK_RESET_MASK << 632*c7cf2933SEtienne Carriere regul->mask_reset_pos); 633*c7cf2933SEtienne Carriere } 634*c7cf2933SEtienne Carriere 635*c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_get(const char *name) 636*c7cf2933SEtienne Carriere { 637*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 638*c7cf2933SEtienne Carriere uint8_t value = 0; 639*c7cf2933SEtienne Carriere uint8_t mask = 0; 640*c7cf2933SEtienne Carriere 641*c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 642*c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 643*c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 644*c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 645*c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 646*c7cf2933SEtienne Carriere else 647*c7cf2933SEtienne Carriere return 0; 648*c7cf2933SEtienne Carriere 649*c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &value)) 650*c7cf2933SEtienne Carriere return -1; 651*c7cf2933SEtienne Carriere 652*c7cf2933SEtienne Carriere value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT; 653*c7cf2933SEtienne Carriere 654*c7cf2933SEtienne Carriere if (value > regul->voltage_table_size) 655*c7cf2933SEtienne Carriere return -1; 656*c7cf2933SEtienne Carriere 657*c7cf2933SEtienne Carriere return regul->voltage_table[value]; 658*c7cf2933SEtienne Carriere } 659*c7cf2933SEtienne Carriere 660*c7cf2933SEtienne Carriere int stpmic1_lp_copy_reg(const char *name) 661*c7cf2933SEtienne Carriere { 662*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 663*c7cf2933SEtienne Carriere uint8_t val = 0; 664*c7cf2933SEtienne Carriere int status = 0; 665*c7cf2933SEtienne Carriere 666*c7cf2933SEtienne Carriere status = stpmic1_register_read(regul->control_reg, &val); 667*c7cf2933SEtienne Carriere if (status) 668*c7cf2933SEtienne Carriere return status; 669*c7cf2933SEtienne Carriere 670*c7cf2933SEtienne Carriere return stpmic1_register_write(regul->low_power_reg, val); 671*c7cf2933SEtienne Carriere } 672*c7cf2933SEtienne Carriere 673*c7cf2933SEtienne Carriere int stpmic1_lp_reg_on_off(const char *name, uint8_t enable) 674*c7cf2933SEtienne Carriere { 675*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 676*c7cf2933SEtienne Carriere 677*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, enable, 678*c7cf2933SEtienne Carriere LDO_BUCK_ENABLE_MASK); 679*c7cf2933SEtienne Carriere } 680*c7cf2933SEtienne Carriere 681*c7cf2933SEtienne Carriere int stpmic1_lp_set_mode(const char *name, uint8_t hplp) 682*c7cf2933SEtienne Carriere { 683*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 684*c7cf2933SEtienne Carriere 685*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, 686*c7cf2933SEtienne Carriere hplp << LDO_BUCK_HPLP_SHIFT, 687*c7cf2933SEtienne Carriere LDO_BUCK_HPLP_ENABLE_MASK); 688*c7cf2933SEtienne Carriere } 689*c7cf2933SEtienne Carriere 690*c7cf2933SEtienne Carriere int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts) 691*c7cf2933SEtienne Carriere { 692*c7cf2933SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 693*c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 694*c7cf2933SEtienne Carriere uint8_t mask = 0; 695*c7cf2933SEtienne Carriere 696*c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 697*c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 698*c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 699*c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 700*c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 701*c7cf2933SEtienne Carriere else 702*c7cf2933SEtienne Carriere return 0; 703*c7cf2933SEtienne Carriere 704*c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, voltage_index << 2, 705*c7cf2933SEtienne Carriere mask); 706*c7cf2933SEtienne Carriere } 707*c7cf2933SEtienne Carriere 708*c7cf2933SEtienne Carriere int stpmic1_register_read(uint8_t register_id, uint8_t *value) 709*c7cf2933SEtienne Carriere { 710*c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 711*c7cf2933SEtienne Carriere 712*c7cf2933SEtienne Carriere return stm32_i2c_mem_read(i2c, pmic_i2c_addr, register_id, 1, 713*c7cf2933SEtienne Carriere value, 1, STPMIC1_I2C_TIMEOUT_US); 714*c7cf2933SEtienne Carriere } 715*c7cf2933SEtienne Carriere 716*c7cf2933SEtienne Carriere int stpmic1_register_write(uint8_t register_id, uint8_t value) 717*c7cf2933SEtienne Carriere { 718*c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 719*c7cf2933SEtienne Carriere uint8_t val = value; 720*c7cf2933SEtienne Carriere 721*c7cf2933SEtienne Carriere return stm32_i2c_mem_write(i2c, pmic_i2c_addr, register_id, 1, 722*c7cf2933SEtienne Carriere &val, 1, STPMIC1_I2C_TIMEOUT_US); 723*c7cf2933SEtienne Carriere } 724*c7cf2933SEtienne Carriere 725*c7cf2933SEtienne Carriere int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask) 726*c7cf2933SEtienne Carriere { 727*c7cf2933SEtienne Carriere int status = 0; 728*c7cf2933SEtienne Carriere uint8_t val = 0; 729*c7cf2933SEtienne Carriere 730*c7cf2933SEtienne Carriere status = stpmic1_register_read(register_id, &val); 731*c7cf2933SEtienne Carriere if (status) 732*c7cf2933SEtienne Carriere return status; 733*c7cf2933SEtienne Carriere 734*c7cf2933SEtienne Carriere val = (val & ~mask) | (value & mask); 735*c7cf2933SEtienne Carriere 736*c7cf2933SEtienne Carriere return stpmic1_register_write(register_id, val); 737*c7cf2933SEtienne Carriere } 738*c7cf2933SEtienne Carriere 739*c7cf2933SEtienne Carriere void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr) 740*c7cf2933SEtienne Carriere { 741*c7cf2933SEtienne Carriere pmic_i2c_handle = i2c_handle; 742*c7cf2933SEtienne Carriere pmic_i2c_addr = i2c_addr; 743*c7cf2933SEtienne Carriere } 744*c7cf2933SEtienne Carriere 745*c7cf2933SEtienne Carriere void stpmic1_dump_regulators(void) 746*c7cf2933SEtienne Carriere { 747*c7cf2933SEtienne Carriere size_t i = 0; 748*c7cf2933SEtienne Carriere char __maybe_unused const *name = NULL; 749*c7cf2933SEtienne Carriere 750*c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) { 751*c7cf2933SEtienne Carriere if (!regulators_table[i].control_reg) 752*c7cf2933SEtienne Carriere continue; 753*c7cf2933SEtienne Carriere 754*c7cf2933SEtienne Carriere name = regulators_table[i].dt_node_name; 755*c7cf2933SEtienne Carriere DMSG("PMIC regul %s: %sable, %dmV", 756*c7cf2933SEtienne Carriere name, stpmic1_is_regulator_enabled(name) ? "en" : "dis", 757*c7cf2933SEtienne Carriere stpmic1_regulator_voltage_get(name)); 758*c7cf2933SEtienne Carriere } 759*c7cf2933SEtienne Carriere } 760*c7cf2933SEtienne Carriere 761*c7cf2933SEtienne Carriere int stpmic1_get_version(unsigned long *version) 762*c7cf2933SEtienne Carriere { 763*c7cf2933SEtienne Carriere uint8_t read_val = 0; 764*c7cf2933SEtienne Carriere 765*c7cf2933SEtienne Carriere if (stpmic1_register_read(VERSION_STATUS_REG, &read_val)) 766*c7cf2933SEtienne Carriere return -1; 767*c7cf2933SEtienne Carriere 768*c7cf2933SEtienne Carriere *version = read_val; 769*c7cf2933SEtienne Carriere return 0; 770*c7cf2933SEtienne Carriere } 771