1c7cf2933SEtienne Carriere // SPDX-License-Identifier: BSD-3-Clause 2c7cf2933SEtienne Carriere /* 368cfb83dSEtienne Carriere * Copyright (c) 2016-2020, STMicroelectronics - All Rights Reserved 4c7cf2933SEtienne Carriere */ 5c7cf2933SEtienne Carriere 6c7cf2933SEtienne Carriere #include <assert.h> 7c7cf2933SEtienne Carriere #include <drivers/stpmic1.h> 8*9cb0d516SEtienne Carriere #include <drivers/stpmic1_regulator.h> 9c7cf2933SEtienne Carriere #include <kernel/panic.h> 10c7cf2933SEtienne Carriere #include <platform_config.h> 11c7cf2933SEtienne Carriere #include <stdint.h> 12c7cf2933SEtienne Carriere #include <string.h> 13c7cf2933SEtienne Carriere #include <trace.h> 1442032ea0SEtienne Carriere #include <util.h> 15c7cf2933SEtienne Carriere 166a63363bSEtienne Carriere #define VOLTAGE_INDEX_INVALID ((unsigned int)~0) 176a63363bSEtienne Carriere 18c7cf2933SEtienne Carriere struct regul_struct { 19c7cf2933SEtienne Carriere const char *dt_node_name; 20c7cf2933SEtienne Carriere const uint16_t *voltage_table; 21c7cf2933SEtienne Carriere uint8_t voltage_table_size; 22c7cf2933SEtienne Carriere uint8_t control_reg; 23c7cf2933SEtienne Carriere uint8_t low_power_reg; 2468cfb83dSEtienne Carriere uint8_t enable_pos; 25c7cf2933SEtienne Carriere uint8_t pull_down_reg; 26c7cf2933SEtienne Carriere uint8_t pull_down_pos; 27c7cf2933SEtienne Carriere uint8_t mask_reset_reg; 28c7cf2933SEtienne Carriere uint8_t mask_reset_pos; 29c7cf2933SEtienne Carriere }; 30c7cf2933SEtienne Carriere 31c7cf2933SEtienne Carriere static struct i2c_handle_s *pmic_i2c_handle; 32c7cf2933SEtienne Carriere static uint16_t pmic_i2c_addr; 33c7cf2933SEtienne Carriere 34c7cf2933SEtienne Carriere /* Voltage tables in mV */ 35c7cf2933SEtienne Carriere static const uint16_t buck1_voltage_table[] = { 36c7cf2933SEtienne Carriere 725, 37c7cf2933SEtienne Carriere 725, 38c7cf2933SEtienne Carriere 725, 39c7cf2933SEtienne Carriere 725, 40c7cf2933SEtienne Carriere 725, 41c7cf2933SEtienne Carriere 725, 42c7cf2933SEtienne Carriere 750, 43c7cf2933SEtienne Carriere 775, 44c7cf2933SEtienne Carriere 800, 45c7cf2933SEtienne Carriere 825, 46c7cf2933SEtienne Carriere 850, 47c7cf2933SEtienne Carriere 875, 48c7cf2933SEtienne Carriere 900, 49c7cf2933SEtienne Carriere 925, 50c7cf2933SEtienne Carriere 950, 51c7cf2933SEtienne Carriere 975, 52c7cf2933SEtienne Carriere 1000, 53c7cf2933SEtienne Carriere 1025, 54c7cf2933SEtienne Carriere 1050, 55c7cf2933SEtienne Carriere 1075, 56c7cf2933SEtienne Carriere 1100, 57c7cf2933SEtienne Carriere 1125, 58c7cf2933SEtienne Carriere 1150, 59c7cf2933SEtienne Carriere 1175, 60c7cf2933SEtienne Carriere 1200, 61c7cf2933SEtienne Carriere 1225, 62c7cf2933SEtienne Carriere 1250, 63c7cf2933SEtienne Carriere 1275, 64c7cf2933SEtienne Carriere 1300, 65c7cf2933SEtienne Carriere 1325, 66c7cf2933SEtienne Carriere 1350, 67c7cf2933SEtienne Carriere 1375, 68c7cf2933SEtienne Carriere 1400, 69c7cf2933SEtienne Carriere 1425, 70c7cf2933SEtienne Carriere 1450, 71c7cf2933SEtienne Carriere 1475, 72c7cf2933SEtienne Carriere 1500, 73c7cf2933SEtienne Carriere 1500, 74c7cf2933SEtienne Carriere 1500, 75c7cf2933SEtienne Carriere 1500, 76c7cf2933SEtienne Carriere 1500, 77c7cf2933SEtienne Carriere 1500, 78c7cf2933SEtienne Carriere 1500, 79c7cf2933SEtienne Carriere 1500, 80c7cf2933SEtienne Carriere 1500, 81c7cf2933SEtienne Carriere 1500, 82c7cf2933SEtienne Carriere 1500, 83c7cf2933SEtienne Carriere 1500, 84c7cf2933SEtienne Carriere 1500, 85c7cf2933SEtienne Carriere 1500, 86c7cf2933SEtienne Carriere 1500, 87c7cf2933SEtienne Carriere 1500, 88c7cf2933SEtienne Carriere 1500, 89c7cf2933SEtienne Carriere 1500, 90c7cf2933SEtienne Carriere 1500, 91c7cf2933SEtienne Carriere 1500, 92c7cf2933SEtienne Carriere 1500, 93c7cf2933SEtienne Carriere 1500, 94c7cf2933SEtienne Carriere 1500, 95c7cf2933SEtienne Carriere 1500, 96c7cf2933SEtienne Carriere 1500, 97c7cf2933SEtienne Carriere 1500, 98c7cf2933SEtienne Carriere 1500, 99c7cf2933SEtienne Carriere 1500, 100c7cf2933SEtienne Carriere }; 101c7cf2933SEtienne Carriere 102c7cf2933SEtienne Carriere static const uint16_t buck2_voltage_table[] = { 103c7cf2933SEtienne Carriere 1000, 104c7cf2933SEtienne Carriere 1000, 105c7cf2933SEtienne Carriere 1000, 106c7cf2933SEtienne Carriere 1000, 107c7cf2933SEtienne Carriere 1000, 108c7cf2933SEtienne Carriere 1000, 109c7cf2933SEtienne Carriere 1000, 110c7cf2933SEtienne Carriere 1000, 111c7cf2933SEtienne Carriere 1000, 112c7cf2933SEtienne Carriere 1000, 113c7cf2933SEtienne Carriere 1000, 114c7cf2933SEtienne Carriere 1000, 115c7cf2933SEtienne Carriere 1000, 116c7cf2933SEtienne Carriere 1000, 117c7cf2933SEtienne Carriere 1000, 118c7cf2933SEtienne Carriere 1000, 119c7cf2933SEtienne Carriere 1000, 120c7cf2933SEtienne Carriere 1000, 121c7cf2933SEtienne Carriere 1050, 122c7cf2933SEtienne Carriere 1050, 123c7cf2933SEtienne Carriere 1100, 124c7cf2933SEtienne Carriere 1100, 125c7cf2933SEtienne Carriere 1150, 126c7cf2933SEtienne Carriere 1150, 127c7cf2933SEtienne Carriere 1200, 128c7cf2933SEtienne Carriere 1200, 129c7cf2933SEtienne Carriere 1250, 130c7cf2933SEtienne Carriere 1250, 131c7cf2933SEtienne Carriere 1300, 132c7cf2933SEtienne Carriere 1300, 133c7cf2933SEtienne Carriere 1350, 134c7cf2933SEtienne Carriere 1350, 135c7cf2933SEtienne Carriere 1400, 136c7cf2933SEtienne Carriere 1400, 137c7cf2933SEtienne Carriere 1450, 138c7cf2933SEtienne Carriere 1450, 139c7cf2933SEtienne Carriere 1500, 140c7cf2933SEtienne Carriere }; 141c7cf2933SEtienne Carriere 142c7cf2933SEtienne Carriere static const uint16_t buck3_voltage_table[] = { 143c7cf2933SEtienne Carriere 1000, 144c7cf2933SEtienne Carriere 1000, 145c7cf2933SEtienne Carriere 1000, 146c7cf2933SEtienne Carriere 1000, 147c7cf2933SEtienne Carriere 1000, 148c7cf2933SEtienne Carriere 1000, 149c7cf2933SEtienne Carriere 1000, 150c7cf2933SEtienne Carriere 1000, 151c7cf2933SEtienne Carriere 1000, 152c7cf2933SEtienne Carriere 1000, 153c7cf2933SEtienne Carriere 1000, 154c7cf2933SEtienne Carriere 1000, 155c7cf2933SEtienne Carriere 1000, 156c7cf2933SEtienne Carriere 1000, 157c7cf2933SEtienne Carriere 1000, 158c7cf2933SEtienne Carriere 1000, 159c7cf2933SEtienne Carriere 1000, 160c7cf2933SEtienne Carriere 1000, 161c7cf2933SEtienne Carriere 1000, 162c7cf2933SEtienne Carriere 1000, 163c7cf2933SEtienne Carriere 1100, 164c7cf2933SEtienne Carriere 1100, 165c7cf2933SEtienne Carriere 1100, 166c7cf2933SEtienne Carriere 1100, 167c7cf2933SEtienne Carriere 1200, 168c7cf2933SEtienne Carriere 1200, 169c7cf2933SEtienne Carriere 1200, 170c7cf2933SEtienne Carriere 1200, 171c7cf2933SEtienne Carriere 1300, 172c7cf2933SEtienne Carriere 1300, 173c7cf2933SEtienne Carriere 1300, 174c7cf2933SEtienne Carriere 1300, 175c7cf2933SEtienne Carriere 1400, 176c7cf2933SEtienne Carriere 1400, 177c7cf2933SEtienne Carriere 1400, 178c7cf2933SEtienne Carriere 1400, 179c7cf2933SEtienne Carriere 1500, 180c7cf2933SEtienne Carriere 1600, 181c7cf2933SEtienne Carriere 1700, 182c7cf2933SEtienne Carriere 1800, 183c7cf2933SEtienne Carriere 1900, 184c7cf2933SEtienne Carriere 2000, 185c7cf2933SEtienne Carriere 2100, 186c7cf2933SEtienne Carriere 2200, 187c7cf2933SEtienne Carriere 2300, 188c7cf2933SEtienne Carriere 2400, 189c7cf2933SEtienne Carriere 2500, 190c7cf2933SEtienne Carriere 2600, 191c7cf2933SEtienne Carriere 2700, 192c7cf2933SEtienne Carriere 2800, 193c7cf2933SEtienne Carriere 2900, 194c7cf2933SEtienne Carriere 3000, 195c7cf2933SEtienne Carriere 3100, 196c7cf2933SEtienne Carriere 3200, 197c7cf2933SEtienne Carriere 3300, 198c7cf2933SEtienne Carriere 3400, 199c7cf2933SEtienne Carriere }; 200c7cf2933SEtienne Carriere 201c7cf2933SEtienne Carriere static const uint16_t buck4_voltage_table[] = { 202c7cf2933SEtienne Carriere 600, 203c7cf2933SEtienne Carriere 625, 204c7cf2933SEtienne Carriere 650, 205c7cf2933SEtienne Carriere 675, 206c7cf2933SEtienne Carriere 700, 207c7cf2933SEtienne Carriere 725, 208c7cf2933SEtienne Carriere 750, 209c7cf2933SEtienne Carriere 775, 210c7cf2933SEtienne Carriere 800, 211c7cf2933SEtienne Carriere 825, 212c7cf2933SEtienne Carriere 850, 213c7cf2933SEtienne Carriere 875, 214c7cf2933SEtienne Carriere 900, 215c7cf2933SEtienne Carriere 925, 216c7cf2933SEtienne Carriere 950, 217c7cf2933SEtienne Carriere 975, 218c7cf2933SEtienne Carriere 1000, 219c7cf2933SEtienne Carriere 1025, 220c7cf2933SEtienne Carriere 1050, 221c7cf2933SEtienne Carriere 1075, 222c7cf2933SEtienne Carriere 1100, 223c7cf2933SEtienne Carriere 1125, 224c7cf2933SEtienne Carriere 1150, 225c7cf2933SEtienne Carriere 1175, 226c7cf2933SEtienne Carriere 1200, 227c7cf2933SEtienne Carriere 1225, 228c7cf2933SEtienne Carriere 1250, 229c7cf2933SEtienne Carriere 1275, 230c7cf2933SEtienne Carriere 1300, 231c7cf2933SEtienne Carriere 1300, 232c7cf2933SEtienne Carriere 1350, 233c7cf2933SEtienne Carriere 1350, 234c7cf2933SEtienne Carriere 1400, 235c7cf2933SEtienne Carriere 1400, 236c7cf2933SEtienne Carriere 1450, 237c7cf2933SEtienne Carriere 1450, 238c7cf2933SEtienne Carriere 1500, 239c7cf2933SEtienne Carriere 1600, 240c7cf2933SEtienne Carriere 1700, 241c7cf2933SEtienne Carriere 1800, 242c7cf2933SEtienne Carriere 1900, 243c7cf2933SEtienne Carriere 2000, 244c7cf2933SEtienne Carriere 2100, 245c7cf2933SEtienne Carriere 2200, 246c7cf2933SEtienne Carriere 2300, 247c7cf2933SEtienne Carriere 2400, 248c7cf2933SEtienne Carriere 2500, 249c7cf2933SEtienne Carriere 2600, 250c7cf2933SEtienne Carriere 2700, 251c7cf2933SEtienne Carriere 2800, 252c7cf2933SEtienne Carriere 2900, 253c7cf2933SEtienne Carriere 3000, 254c7cf2933SEtienne Carriere 3100, 255c7cf2933SEtienne Carriere 3200, 256c7cf2933SEtienne Carriere 3300, 257c7cf2933SEtienne Carriere 3400, 258c7cf2933SEtienne Carriere 3500, 259c7cf2933SEtienne Carriere 3600, 260c7cf2933SEtienne Carriere 3700, 261c7cf2933SEtienne Carriere 3800, 262c7cf2933SEtienne Carriere 3900, 263c7cf2933SEtienne Carriere }; 264c7cf2933SEtienne Carriere 265c7cf2933SEtienne Carriere static const uint16_t ldo1_voltage_table[] = { 266c7cf2933SEtienne Carriere 1700, 267c7cf2933SEtienne Carriere 1700, 268c7cf2933SEtienne Carriere 1700, 269c7cf2933SEtienne Carriere 1700, 270c7cf2933SEtienne Carriere 1700, 271c7cf2933SEtienne Carriere 1700, 272c7cf2933SEtienne Carriere 1700, 273c7cf2933SEtienne Carriere 1700, 274c7cf2933SEtienne Carriere 1700, 275c7cf2933SEtienne Carriere 1800, 276c7cf2933SEtienne Carriere 1900, 277c7cf2933SEtienne Carriere 2000, 278c7cf2933SEtienne Carriere 2100, 279c7cf2933SEtienne Carriere 2200, 280c7cf2933SEtienne Carriere 2300, 281c7cf2933SEtienne Carriere 2400, 282c7cf2933SEtienne Carriere 2500, 283c7cf2933SEtienne Carriere 2600, 284c7cf2933SEtienne Carriere 2700, 285c7cf2933SEtienne Carriere 2800, 286c7cf2933SEtienne Carriere 2900, 287c7cf2933SEtienne Carriere 3000, 288c7cf2933SEtienne Carriere 3100, 289c7cf2933SEtienne Carriere 3200, 290c7cf2933SEtienne Carriere 3300, 291c7cf2933SEtienne Carriere }; 292c7cf2933SEtienne Carriere 293c7cf2933SEtienne Carriere static const uint16_t ldo2_voltage_table[] = { 294c7cf2933SEtienne Carriere 1700, 295c7cf2933SEtienne Carriere 1700, 296c7cf2933SEtienne Carriere 1700, 297c7cf2933SEtienne Carriere 1700, 298c7cf2933SEtienne Carriere 1700, 299c7cf2933SEtienne Carriere 1700, 300c7cf2933SEtienne Carriere 1700, 301c7cf2933SEtienne Carriere 1700, 302c7cf2933SEtienne Carriere 1700, 303c7cf2933SEtienne Carriere 1800, 304c7cf2933SEtienne Carriere 1900, 305c7cf2933SEtienne Carriere 2000, 306c7cf2933SEtienne Carriere 2100, 307c7cf2933SEtienne Carriere 2200, 308c7cf2933SEtienne Carriere 2300, 309c7cf2933SEtienne Carriere 2400, 310c7cf2933SEtienne Carriere 2500, 311c7cf2933SEtienne Carriere 2600, 312c7cf2933SEtienne Carriere 2700, 313c7cf2933SEtienne Carriere 2800, 314c7cf2933SEtienne Carriere 2900, 315c7cf2933SEtienne Carriere 3000, 316c7cf2933SEtienne Carriere 3100, 317c7cf2933SEtienne Carriere 3200, 318c7cf2933SEtienne Carriere 3300, 319c7cf2933SEtienne Carriere }; 320c7cf2933SEtienne Carriere 321c7cf2933SEtienne Carriere static const uint16_t ldo3_voltage_table[] = { 322c7cf2933SEtienne Carriere 1700, 323c7cf2933SEtienne Carriere 1700, 324c7cf2933SEtienne Carriere 1700, 325c7cf2933SEtienne Carriere 1700, 326c7cf2933SEtienne Carriere 1700, 327c7cf2933SEtienne Carriere 1700, 328c7cf2933SEtienne Carriere 1700, 329c7cf2933SEtienne Carriere 1700, 330c7cf2933SEtienne Carriere 1700, 331c7cf2933SEtienne Carriere 1800, 332c7cf2933SEtienne Carriere 1900, 333c7cf2933SEtienne Carriere 2000, 334c7cf2933SEtienne Carriere 2100, 335c7cf2933SEtienne Carriere 2200, 336c7cf2933SEtienne Carriere 2300, 337c7cf2933SEtienne Carriere 2400, 338c7cf2933SEtienne Carriere 2500, 339c7cf2933SEtienne Carriere 2600, 340c7cf2933SEtienne Carriere 2700, 341c7cf2933SEtienne Carriere 2800, 342c7cf2933SEtienne Carriere 2900, 343c7cf2933SEtienne Carriere 3000, 344c7cf2933SEtienne Carriere 3100, 345c7cf2933SEtienne Carriere 3200, 346c7cf2933SEtienne Carriere 3300, 347c7cf2933SEtienne Carriere 3300, 348c7cf2933SEtienne Carriere 3300, 349c7cf2933SEtienne Carriere 3300, 350c7cf2933SEtienne Carriere 3300, 351c7cf2933SEtienne Carriere 3300, 352c7cf2933SEtienne Carriere 3300, 353f7e28951SEtienne Carriere 500, /* VOUT2/2 (Sink/source mode) */ 354c7cf2933SEtienne Carriere 0xFFFF, /* VREFDDR */ 355c7cf2933SEtienne Carriere }; 356c7cf2933SEtienne Carriere 357c7cf2933SEtienne Carriere static const uint16_t ldo5_voltage_table[] = { 358c7cf2933SEtienne Carriere 1700, 359c7cf2933SEtienne Carriere 1700, 360c7cf2933SEtienne Carriere 1700, 361c7cf2933SEtienne Carriere 1700, 362c7cf2933SEtienne Carriere 1700, 363c7cf2933SEtienne Carriere 1700, 364c7cf2933SEtienne Carriere 1700, 365c7cf2933SEtienne Carriere 1700, 366c7cf2933SEtienne Carriere 1700, 367c7cf2933SEtienne Carriere 1800, 368c7cf2933SEtienne Carriere 1900, 369c7cf2933SEtienne Carriere 2000, 370c7cf2933SEtienne Carriere 2100, 371c7cf2933SEtienne Carriere 2200, 372c7cf2933SEtienne Carriere 2300, 373c7cf2933SEtienne Carriere 2400, 374c7cf2933SEtienne Carriere 2500, 375c7cf2933SEtienne Carriere 2600, 376c7cf2933SEtienne Carriere 2700, 377c7cf2933SEtienne Carriere 2800, 378c7cf2933SEtienne Carriere 2900, 379c7cf2933SEtienne Carriere 3000, 380c7cf2933SEtienne Carriere 3100, 381c7cf2933SEtienne Carriere 3200, 382c7cf2933SEtienne Carriere 3300, 383c7cf2933SEtienne Carriere 3400, 384c7cf2933SEtienne Carriere 3500, 385c7cf2933SEtienne Carriere 3600, 386c7cf2933SEtienne Carriere 3700, 387c7cf2933SEtienne Carriere 3800, 388c7cf2933SEtienne Carriere 3900, 389c7cf2933SEtienne Carriere }; 390c7cf2933SEtienne Carriere 391c7cf2933SEtienne Carriere static const uint16_t ldo6_voltage_table[] = { 392c7cf2933SEtienne Carriere 900, 393c7cf2933SEtienne Carriere 1000, 394c7cf2933SEtienne Carriere 1100, 395c7cf2933SEtienne Carriere 1200, 396c7cf2933SEtienne Carriere 1300, 397c7cf2933SEtienne Carriere 1400, 398c7cf2933SEtienne Carriere 1500, 399c7cf2933SEtienne Carriere 1600, 400c7cf2933SEtienne Carriere 1700, 401c7cf2933SEtienne Carriere 1800, 402c7cf2933SEtienne Carriere 1900, 403c7cf2933SEtienne Carriere 2000, 404c7cf2933SEtienne Carriere 2100, 405c7cf2933SEtienne Carriere 2200, 406c7cf2933SEtienne Carriere 2300, 407c7cf2933SEtienne Carriere 2400, 408c7cf2933SEtienne Carriere 2500, 409c7cf2933SEtienne Carriere 2600, 410c7cf2933SEtienne Carriere 2700, 411c7cf2933SEtienne Carriere 2800, 412c7cf2933SEtienne Carriere 2900, 413c7cf2933SEtienne Carriere 3000, 414c7cf2933SEtienne Carriere 3100, 415c7cf2933SEtienne Carriere 3200, 416c7cf2933SEtienne Carriere 3300, 417c7cf2933SEtienne Carriere }; 418c7cf2933SEtienne Carriere 419c7cf2933SEtienne Carriere static const uint16_t ldo4_voltage_table[] = { 420c7cf2933SEtienne Carriere 3300, 421c7cf2933SEtienne Carriere }; 422c7cf2933SEtienne Carriere 423c7cf2933SEtienne Carriere static const uint16_t vref_ddr_voltage_table[] = { 424c7cf2933SEtienne Carriere 3300, 425c7cf2933SEtienne Carriere }; 426c7cf2933SEtienne Carriere 4273f692bdfSEtienne Carriere static const uint16_t fixed_5v_voltage_table[] = { 4283f692bdfSEtienne Carriere 5000, 4293f692bdfSEtienne Carriere }; 4303f692bdfSEtienne Carriere 431c7cf2933SEtienne Carriere /* Table of Regulators in PMIC SoC */ 432c7cf2933SEtienne Carriere static const struct regul_struct regulators_table[] = { 433c7cf2933SEtienne Carriere { 434c7cf2933SEtienne Carriere .dt_node_name = "buck1", 435c7cf2933SEtienne Carriere .voltage_table = buck1_voltage_table, 436c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck1_voltage_table), 437c7cf2933SEtienne Carriere .control_reg = BUCK1_CONTROL_REG, 438c7cf2933SEtienne Carriere .low_power_reg = BUCK1_PWRCTRL_REG, 43968cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 440c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 441c7cf2933SEtienne Carriere .pull_down_pos = BUCK1_PULL_DOWN_SHIFT, 442c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 443c7cf2933SEtienne Carriere .mask_reset_pos = BUCK1_MASK_RESET_SHIFT, 444c7cf2933SEtienne Carriere }, 445c7cf2933SEtienne Carriere { 446c7cf2933SEtienne Carriere .dt_node_name = "buck2", 447c7cf2933SEtienne Carriere .voltage_table = buck2_voltage_table, 448c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck2_voltage_table), 449c7cf2933SEtienne Carriere .control_reg = BUCK2_CONTROL_REG, 450c7cf2933SEtienne Carriere .low_power_reg = BUCK2_PWRCTRL_REG, 45168cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 452c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 453c7cf2933SEtienne Carriere .pull_down_pos = BUCK2_PULL_DOWN_SHIFT, 454c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 455c7cf2933SEtienne Carriere .mask_reset_pos = BUCK2_MASK_RESET_SHIFT, 456c7cf2933SEtienne Carriere }, 457c7cf2933SEtienne Carriere { 458c7cf2933SEtienne Carriere .dt_node_name = "buck3", 459c7cf2933SEtienne Carriere .voltage_table = buck3_voltage_table, 460c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck3_voltage_table), 461c7cf2933SEtienne Carriere .control_reg = BUCK3_CONTROL_REG, 462c7cf2933SEtienne Carriere .low_power_reg = BUCK3_PWRCTRL_REG, 46368cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 464c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 465c7cf2933SEtienne Carriere .pull_down_pos = BUCK3_PULL_DOWN_SHIFT, 466c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 467c7cf2933SEtienne Carriere .mask_reset_pos = BUCK3_MASK_RESET_SHIFT, 468c7cf2933SEtienne Carriere }, 469c7cf2933SEtienne Carriere { 470c7cf2933SEtienne Carriere .dt_node_name = "buck4", 471c7cf2933SEtienne Carriere .voltage_table = buck4_voltage_table, 472c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck4_voltage_table), 473c7cf2933SEtienne Carriere .control_reg = BUCK4_CONTROL_REG, 474c7cf2933SEtienne Carriere .low_power_reg = BUCK4_PWRCTRL_REG, 47568cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 476c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 477c7cf2933SEtienne Carriere .pull_down_pos = BUCK4_PULL_DOWN_SHIFT, 478c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 479c7cf2933SEtienne Carriere .mask_reset_pos = BUCK4_MASK_RESET_SHIFT, 480c7cf2933SEtienne Carriere }, 481c7cf2933SEtienne Carriere { 482c7cf2933SEtienne Carriere .dt_node_name = "ldo1", 483c7cf2933SEtienne Carriere .voltage_table = ldo1_voltage_table, 484c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table), 485c7cf2933SEtienne Carriere .control_reg = LDO1_CONTROL_REG, 486c7cf2933SEtienne Carriere .low_power_reg = LDO1_PWRCTRL_REG, 48768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 488c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 489c7cf2933SEtienne Carriere .mask_reset_pos = LDO1_MASK_RESET_SHIFT, 490c7cf2933SEtienne Carriere }, 491c7cf2933SEtienne Carriere { 492c7cf2933SEtienne Carriere .dt_node_name = "ldo2", 493c7cf2933SEtienne Carriere .voltage_table = ldo2_voltage_table, 494c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table), 495c7cf2933SEtienne Carriere .control_reg = LDO2_CONTROL_REG, 496c7cf2933SEtienne Carriere .low_power_reg = LDO2_PWRCTRL_REG, 49768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 498c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 499c7cf2933SEtienne Carriere .mask_reset_pos = LDO2_MASK_RESET_SHIFT, 500c7cf2933SEtienne Carriere }, 501c7cf2933SEtienne Carriere { 502c7cf2933SEtienne Carriere .dt_node_name = "ldo3", 503c7cf2933SEtienne Carriere .voltage_table = ldo3_voltage_table, 504c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table), 505c7cf2933SEtienne Carriere .control_reg = LDO3_CONTROL_REG, 506c7cf2933SEtienne Carriere .low_power_reg = LDO3_PWRCTRL_REG, 50768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 508c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 509c7cf2933SEtienne Carriere .mask_reset_pos = LDO3_MASK_RESET_SHIFT, 510c7cf2933SEtienne Carriere }, 511c7cf2933SEtienne Carriere { 512c7cf2933SEtienne Carriere .dt_node_name = "ldo4", 513c7cf2933SEtienne Carriere .voltage_table = ldo4_voltage_table, 514c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table), 515c7cf2933SEtienne Carriere .control_reg = LDO4_CONTROL_REG, 516c7cf2933SEtienne Carriere .low_power_reg = LDO4_PWRCTRL_REG, 51768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 518c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 519c7cf2933SEtienne Carriere .mask_reset_pos = LDO4_MASK_RESET_SHIFT, 520c7cf2933SEtienne Carriere }, 521c7cf2933SEtienne Carriere { 522c7cf2933SEtienne Carriere .dt_node_name = "ldo5", 523c7cf2933SEtienne Carriere .voltage_table = ldo5_voltage_table, 524c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table), 525c7cf2933SEtienne Carriere .control_reg = LDO5_CONTROL_REG, 526c7cf2933SEtienne Carriere .low_power_reg = LDO5_PWRCTRL_REG, 52768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 528c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 529c7cf2933SEtienne Carriere .mask_reset_pos = LDO5_MASK_RESET_SHIFT, 530c7cf2933SEtienne Carriere }, 531c7cf2933SEtienne Carriere { 532c7cf2933SEtienne Carriere .dt_node_name = "ldo6", 533c7cf2933SEtienne Carriere .voltage_table = ldo6_voltage_table, 534c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table), 535c7cf2933SEtienne Carriere .control_reg = LDO6_CONTROL_REG, 536c7cf2933SEtienne Carriere .low_power_reg = LDO6_PWRCTRL_REG, 53768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 538c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 539c7cf2933SEtienne Carriere .mask_reset_pos = LDO6_MASK_RESET_SHIFT, 540c7cf2933SEtienne Carriere }, 541c7cf2933SEtienne Carriere { 542c7cf2933SEtienne Carriere .dt_node_name = "vref_ddr", 543c7cf2933SEtienne Carriere .voltage_table = vref_ddr_voltage_table, 544c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table), 545c7cf2933SEtienne Carriere .control_reg = VREF_DDR_CONTROL_REG, 546c7cf2933SEtienne Carriere .low_power_reg = VREF_DDR_PWRCTRL_REG, 54768cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 548c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 549c7cf2933SEtienne Carriere .mask_reset_pos = VREF_DDR_MASK_RESET_SHIFT, 550c7cf2933SEtienne Carriere }, 551c7cf2933SEtienne Carriere { 552c7cf2933SEtienne Carriere .dt_node_name = "boost", 5533f692bdfSEtienne Carriere .voltage_table = fixed_5v_voltage_table, 5543f692bdfSEtienne Carriere .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), 5553f692bdfSEtienne Carriere .control_reg = USB_CONTROL_REG, 5563f692bdfSEtienne Carriere .enable_pos = BOOST_ENABLED_POS, 557c7cf2933SEtienne Carriere }, 558c7cf2933SEtienne Carriere { 559c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw1", 5603f692bdfSEtienne Carriere .voltage_table = fixed_5v_voltage_table, 5613f692bdfSEtienne Carriere .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), 5623f692bdfSEtienne Carriere .control_reg = USB_CONTROL_REG, 5633f692bdfSEtienne Carriere .enable_pos = USBSW_OTG_SWITCH_ENABLED_POS, 564c7cf2933SEtienne Carriere }, 565c7cf2933SEtienne Carriere { 566c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw2", 5673f692bdfSEtienne Carriere .voltage_table = fixed_5v_voltage_table, 5683f692bdfSEtienne Carriere .voltage_table_size = ARRAY_SIZE(fixed_5v_voltage_table), 5693f692bdfSEtienne Carriere .control_reg = USB_CONTROL_REG, 5703f692bdfSEtienne Carriere .enable_pos = SWIN_SWOUT_ENABLED_POS, 571c7cf2933SEtienne Carriere }, 572c7cf2933SEtienne Carriere }; 573c7cf2933SEtienne Carriere 574c7cf2933SEtienne Carriere static const struct regul_struct *get_regulator_data(const char *name) 575c7cf2933SEtienne Carriere { 576c7cf2933SEtienne Carriere unsigned int i = 0; 577c7cf2933SEtienne Carriere 578c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) 579c7cf2933SEtienne Carriere if (strcmp(name, regulators_table[i].dt_node_name) == 0) 580c7cf2933SEtienne Carriere return ®ulators_table[i]; 581c7cf2933SEtienne Carriere 5826a63363bSEtienne Carriere DMSG("Regulator %s not found", name); 5836a63363bSEtienne Carriere return NULL; 584c7cf2933SEtienne Carriere } 585c7cf2933SEtienne Carriere 586e0f7e777SEtienne Carriere bool stpmic1_regulator_is_valid(const char *name) 587e0f7e777SEtienne Carriere { 588e0f7e777SEtienne Carriere return get_regulator_data(name); 589e0f7e777SEtienne Carriere } 590e0f7e777SEtienne Carriere 5918537f7ebSMarouene Boubakri void stpmic1_regulator_levels_mv(const char *name, 592c52a7c2eSEtienne Carriere const uint16_t **levels, 593c52a7c2eSEtienne Carriere size_t *levels_count) 594c52a7c2eSEtienne Carriere { 595c52a7c2eSEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 596c52a7c2eSEtienne Carriere 5978537f7ebSMarouene Boubakri assert(regul); 598c52a7c2eSEtienne Carriere 599c52a7c2eSEtienne Carriere if (levels_count) 600c52a7c2eSEtienne Carriere *levels_count = regul->voltage_table_size; 601c52a7c2eSEtienne Carriere 602c52a7c2eSEtienne Carriere if (levels) 603c52a7c2eSEtienne Carriere *levels = regul->voltage_table; 604c52a7c2eSEtienne Carriere } 605c52a7c2eSEtienne Carriere 6066a63363bSEtienne Carriere static size_t voltage_to_index(const char *name, uint16_t millivolts) 607c7cf2933SEtienne Carriere { 608c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 609c7cf2933SEtienne Carriere unsigned int i = 0; 610c7cf2933SEtienne Carriere 611c7cf2933SEtienne Carriere assert(regul->voltage_table); 612c7cf2933SEtienne Carriere for (i = 0; i < regul->voltage_table_size; i++) 613c7cf2933SEtienne Carriere if (regul->voltage_table[i] == millivolts) 614c7cf2933SEtienne Carriere return i; 615c7cf2933SEtienne Carriere 6166a63363bSEtienne Carriere return VOLTAGE_INDEX_INVALID; 617c7cf2933SEtienne Carriere } 618c7cf2933SEtienne Carriere 619c7cf2933SEtienne Carriere int stpmic1_powerctrl_on(void) 620c7cf2933SEtienne Carriere { 621c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, PWRCTRL_PIN_VALID, 622c7cf2933SEtienne Carriere PWRCTRL_PIN_VALID); 623c7cf2933SEtienne Carriere } 624c7cf2933SEtienne Carriere 625c7cf2933SEtienne Carriere int stpmic1_switch_off(void) 626c7cf2933SEtienne Carriere { 627c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, 1, 628c7cf2933SEtienne Carriere SOFTWARE_SWITCH_OFF_ENABLED); 629c7cf2933SEtienne Carriere } 630c7cf2933SEtienne Carriere 631c7cf2933SEtienne Carriere int stpmic1_regulator_enable(const char *name) 632c7cf2933SEtienne Carriere { 633c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 634c7cf2933SEtienne Carriere 63568cfb83dSEtienne Carriere return stpmic1_register_update(regul->control_reg, 63668cfb83dSEtienne Carriere BIT(regul->enable_pos), 63768cfb83dSEtienne Carriere BIT(regul->enable_pos)); 638c7cf2933SEtienne Carriere } 639c7cf2933SEtienne Carriere 640c7cf2933SEtienne Carriere int stpmic1_regulator_disable(const char *name) 641c7cf2933SEtienne Carriere { 642c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 643c7cf2933SEtienne Carriere 64468cfb83dSEtienne Carriere return stpmic1_register_update(regul->control_reg, 0, 64568cfb83dSEtienne Carriere BIT(regul->enable_pos)); 646c7cf2933SEtienne Carriere } 647c7cf2933SEtienne Carriere 6482619b28cSEtienne Carriere bool stpmic1_is_regulator_enabled(const char *name) 649c7cf2933SEtienne Carriere { 650c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 651c7cf2933SEtienne Carriere uint8_t val = 0; 652c7cf2933SEtienne Carriere 653c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &val)) 654c7cf2933SEtienne Carriere panic(); 655c7cf2933SEtienne Carriere 65668cfb83dSEtienne Carriere return val & BIT(regul->enable_pos); 657c7cf2933SEtienne Carriere } 658c7cf2933SEtienne Carriere 6591764a894SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 6601764a894SEtienne Carriere static uint8_t find_plat_mask(const char *name) 6611764a894SEtienne Carriere { 6621764a894SEtienne Carriere if (!strncmp(name, "buck", 4)) 6631764a894SEtienne Carriere return BUCK_VOLTAGE_MASK; 6641764a894SEtienne Carriere 6651764a894SEtienne Carriere if (!strncmp(name, "ldo", 3) && strcmp(name, "ldo4")) 6661764a894SEtienne Carriere return LDO_VOLTAGE_MASK; 6671764a894SEtienne Carriere 6681764a894SEtienne Carriere return 0; 6691764a894SEtienne Carriere } 6701764a894SEtienne Carriere 671c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts) 672c7cf2933SEtienne Carriere { 6736a63363bSEtienne Carriere size_t voltage_index = voltage_to_index(name, millivolts); 674c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 675c7cf2933SEtienne Carriere uint8_t mask = 0; 676c7cf2933SEtienne Carriere 6776a63363bSEtienne Carriere if (voltage_index == VOLTAGE_INDEX_INVALID) 6786a63363bSEtienne Carriere return -1; 6796a63363bSEtienne Carriere 6801764a894SEtienne Carriere mask = find_plat_mask(name); 6811764a894SEtienne Carriere if (!mask) 682c7cf2933SEtienne Carriere return 0; 683c7cf2933SEtienne Carriere 684c7cf2933SEtienne Carriere return stpmic1_register_update(regul->control_reg, 685c7cf2933SEtienne Carriere voltage_index << LDO_BUCK_VOLTAGE_SHIFT, 686c7cf2933SEtienne Carriere mask); 687c7cf2933SEtienne Carriere } 688c7cf2933SEtienne Carriere 689c7cf2933SEtienne Carriere int stpmic1_regulator_mask_reset_set(const char *name) 690c7cf2933SEtienne Carriere { 691c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 692c7cf2933SEtienne Carriere 6933f692bdfSEtienne Carriere if (regul->control_reg == USB_CONTROL_REG) { 6943f692bdfSEtienne Carriere DMSG("No reset for USB control"); 6953f692bdfSEtienne Carriere return -1; 6963f692bdfSEtienne Carriere } 6973f692bdfSEtienne Carriere 698c7cf2933SEtienne Carriere return stpmic1_register_update(regul->mask_reset_reg, 699c7cf2933SEtienne Carriere BIT(regul->mask_reset_pos), 700c7cf2933SEtienne Carriere LDO_BUCK_RESET_MASK << 701c7cf2933SEtienne Carriere regul->mask_reset_pos); 702c7cf2933SEtienne Carriere } 703c7cf2933SEtienne Carriere 7046149e2d8SEtienne Carriere int stpmic1_bo_enable_cfg(const char *name, struct stpmic1_bo_cfg *cfg) 7056149e2d8SEtienne Carriere { 7066149e2d8SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 7076149e2d8SEtienne Carriere 7086149e2d8SEtienne Carriere cfg->ctrl_reg = regul->control_reg; 7096149e2d8SEtienne Carriere cfg->enable_pos = regul->enable_pos; 7106149e2d8SEtienne Carriere 7116149e2d8SEtienne Carriere return 0; 7126149e2d8SEtienne Carriere } 7136149e2d8SEtienne Carriere 714eb5d5313SEtienne Carriere int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg) 715eb5d5313SEtienne Carriere { 71668cfb83dSEtienne Carriere return stpmic1_register_update(cfg->ctrl_reg, 71768cfb83dSEtienne Carriere BIT(cfg->enable_pos), 71868cfb83dSEtienne Carriere BIT(cfg->enable_pos)); 719eb5d5313SEtienne Carriere } 720eb5d5313SEtienne Carriere 721eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */ 72244219e70SEtienne Carriere int stpmic1_bo_voltage_cfg(const char *name, uint16_t min_millivolt, 723eb5d5313SEtienne Carriere struct stpmic1_bo_cfg *cfg) 724eb5d5313SEtienne Carriere { 7256a63363bSEtienne Carriere size_t min_index = voltage_to_index(name, min_millivolt); 726eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 727eb5d5313SEtienne Carriere uint8_t mask = 0; 728eb5d5313SEtienne Carriere 7296a63363bSEtienne Carriere if (min_index == VOLTAGE_INDEX_INVALID) 7306a63363bSEtienne Carriere panic(); 7316a63363bSEtienne Carriere 7321764a894SEtienne Carriere mask = find_plat_mask(name); 7331764a894SEtienne Carriere if (!mask) 734eb5d5313SEtienne Carriere return 1; 735eb5d5313SEtienne Carriere 736eb5d5313SEtienne Carriere cfg->ctrl_reg = regul->control_reg; 73744219e70SEtienne Carriere cfg->min_value = min_index << LDO_BUCK_VOLTAGE_SHIFT; 738eb5d5313SEtienne Carriere cfg->mask = mask; 739eb5d5313SEtienne Carriere 740eb5d5313SEtienne Carriere return 0; 741eb5d5313SEtienne Carriere } 742eb5d5313SEtienne Carriere 743eb5d5313SEtienne Carriere int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg) 744eb5d5313SEtienne Carriere { 74544219e70SEtienne Carriere uint8_t value = 0; 74644219e70SEtienne Carriere 74744219e70SEtienne Carriere assert(cfg->ctrl_reg); 74844219e70SEtienne Carriere 74944219e70SEtienne Carriere if (stpmic1_register_read(cfg->ctrl_reg, &value)) 75044219e70SEtienne Carriere return -1; 75144219e70SEtienne Carriere 752187ba5c2SEtienne Carriere if ((value & cfg->mask) >= cfg->min_value) 75344219e70SEtienne Carriere return 0; 75444219e70SEtienne Carriere 75544219e70SEtienne Carriere return stpmic1_register_update(cfg->ctrl_reg, cfg->min_value, 75644219e70SEtienne Carriere cfg->mask); 757eb5d5313SEtienne Carriere } 758eb5d5313SEtienne Carriere 759eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_cfg(const char *name, struct stpmic1_bo_cfg *cfg) 760eb5d5313SEtienne Carriere { 761eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 762eb5d5313SEtienne Carriere 763ef18a901SEtienne Carriere if (!regul->pull_down_reg) { 764ef18a901SEtienne Carriere DMSG("No pull down for regu %s", name); 765ef18a901SEtienne Carriere panic(); 766ef18a901SEtienne Carriere } 767ef18a901SEtienne Carriere 768eb5d5313SEtienne Carriere cfg->pd_reg = regul->pull_down_reg; 769eb5d5313SEtienne Carriere cfg->pd_value = BIT(regul->pull_down_pos); 770eb5d5313SEtienne Carriere cfg->pd_mask = LDO_BUCK_PULL_DOWN_MASK << regul->pull_down_pos; 771eb5d5313SEtienne Carriere 772eb5d5313SEtienne Carriere return 0; 773eb5d5313SEtienne Carriere } 774eb5d5313SEtienne Carriere 775eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg) 776eb5d5313SEtienne Carriere { 777ef18a901SEtienne Carriere assert(cfg->pd_reg); 778ef18a901SEtienne Carriere 779eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->pd_reg, cfg->pd_value, 780eb5d5313SEtienne Carriere cfg->pd_mask); 781eb5d5313SEtienne Carriere } 782eb5d5313SEtienne Carriere 783eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg) 784eb5d5313SEtienne Carriere { 785eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 786eb5d5313SEtienne Carriere 787ef18a901SEtienne Carriere if (!regul->mask_reset_reg) { 788ef18a901SEtienne Carriere DMSG("No reset mask for regu %s", name); 789ef18a901SEtienne Carriere panic(); 790ef18a901SEtienne Carriere } 791ef18a901SEtienne Carriere 792eb5d5313SEtienne Carriere cfg->mrst_reg = regul->mask_reset_reg; 793eb5d5313SEtienne Carriere cfg->mrst_value = BIT(regul->mask_reset_pos); 794eb5d5313SEtienne Carriere cfg->mrst_mask = LDO_BUCK_RESET_MASK << regul->mask_reset_pos; 795eb5d5313SEtienne Carriere 796eb5d5313SEtienne Carriere return 0; 797eb5d5313SEtienne Carriere } 798eb5d5313SEtienne Carriere 799eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg) 800eb5d5313SEtienne Carriere { 801ef18a901SEtienne Carriere assert(cfg->mrst_reg); 802ef18a901SEtienne Carriere 803eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value, 804eb5d5313SEtienne Carriere cfg->mrst_mask); 805eb5d5313SEtienne Carriere } 806eb5d5313SEtienne Carriere 807c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_get(const char *name) 808c7cf2933SEtienne Carriere { 809c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 810c7cf2933SEtienne Carriere uint8_t value = 0; 811c7cf2933SEtienne Carriere uint8_t mask = 0; 812c7cf2933SEtienne Carriere 8131764a894SEtienne Carriere mask = find_plat_mask(name); 8141764a894SEtienne Carriere if (!mask) 815c7cf2933SEtienne Carriere return 0; 816c7cf2933SEtienne Carriere 817c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &value)) 818c7cf2933SEtienne Carriere return -1; 819c7cf2933SEtienne Carriere 820c7cf2933SEtienne Carriere value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT; 821c7cf2933SEtienne Carriere 822c7cf2933SEtienne Carriere if (value > regul->voltage_table_size) 823c7cf2933SEtienne Carriere return -1; 824c7cf2933SEtienne Carriere 825c7cf2933SEtienne Carriere return regul->voltage_table[value]; 826c7cf2933SEtienne Carriere } 827c7cf2933SEtienne Carriere 828c7cf2933SEtienne Carriere int stpmic1_lp_copy_reg(const char *name) 829c7cf2933SEtienne Carriere { 830c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 831c7cf2933SEtienne Carriere uint8_t val = 0; 832c7cf2933SEtienne Carriere int status = 0; 833c7cf2933SEtienne Carriere 834972b3d9aSEtienne Carriere if (!regul->low_power_reg) 835972b3d9aSEtienne Carriere return -1; 836972b3d9aSEtienne Carriere 837c7cf2933SEtienne Carriere status = stpmic1_register_read(regul->control_reg, &val); 838c7cf2933SEtienne Carriere if (status) 839c7cf2933SEtienne Carriere return status; 840c7cf2933SEtienne Carriere 841c7cf2933SEtienne Carriere return stpmic1_register_write(regul->low_power_reg, val); 842c7cf2933SEtienne Carriere } 843c7cf2933SEtienne Carriere 844972b3d9aSEtienne Carriere bool stpmic1_regu_has_lp_cfg(const char *name) 845972b3d9aSEtienne Carriere { 846972b3d9aSEtienne Carriere return get_regulator_data(name)->low_power_reg; 847972b3d9aSEtienne Carriere } 848972b3d9aSEtienne Carriere 849eb5d5313SEtienne Carriere int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg) 850eb5d5313SEtienne Carriere { 851eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 852eb5d5313SEtienne Carriere 853972b3d9aSEtienne Carriere if (!regul->low_power_reg) 854972b3d9aSEtienne Carriere return -1; 855972b3d9aSEtienne Carriere 856eb5d5313SEtienne Carriere cfg->ctrl_reg = regul->control_reg; 857eb5d5313SEtienne Carriere cfg->lp_reg = regul->low_power_reg; 858eb5d5313SEtienne Carriere 859eb5d5313SEtienne Carriere return 0; 860eb5d5313SEtienne Carriere } 861eb5d5313SEtienne Carriere 862eb5d5313SEtienne Carriere int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg) 863eb5d5313SEtienne Carriere { 864eb5d5313SEtienne Carriere uint8_t val = 0; 865eb5d5313SEtienne Carriere int status = 0; 866eb5d5313SEtienne Carriere 867ef18a901SEtienne Carriere assert(cfg->lp_reg); 868ef18a901SEtienne Carriere 869eb5d5313SEtienne Carriere status = stpmic1_register_read(cfg->ctrl_reg, &val); 870eb5d5313SEtienne Carriere if (!status) 871eb5d5313SEtienne Carriere status = stpmic1_register_write(cfg->lp_reg, val); 872eb5d5313SEtienne Carriere 873eb5d5313SEtienne Carriere return status; 874eb5d5313SEtienne Carriere } 875eb5d5313SEtienne Carriere 876c7cf2933SEtienne Carriere int stpmic1_lp_reg_on_off(const char *name, uint8_t enable) 877c7cf2933SEtienne Carriere { 878c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 879c7cf2933SEtienne Carriere 880972b3d9aSEtienne Carriere if (!regul->low_power_reg) 881972b3d9aSEtienne Carriere return -1; 882972b3d9aSEtienne Carriere 883c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, enable, 884c7cf2933SEtienne Carriere LDO_BUCK_ENABLE_MASK); 885c7cf2933SEtienne Carriere } 886c7cf2933SEtienne Carriere 887eb5d5313SEtienne Carriere int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable) 888eb5d5313SEtienne Carriere { 889ef18a901SEtienne Carriere assert(cfg->lp_reg && (enable == 0 || enable == 1)); 890ef18a901SEtienne Carriere 891eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, enable, 892eb5d5313SEtienne Carriere LDO_BUCK_ENABLE_MASK); 893eb5d5313SEtienne Carriere } 894eb5d5313SEtienne Carriere 895c7cf2933SEtienne Carriere int stpmic1_lp_set_mode(const char *name, uint8_t hplp) 896c7cf2933SEtienne Carriere { 897c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 898c7cf2933SEtienne Carriere 899ef18a901SEtienne Carriere assert(regul->low_power_reg && (hplp == 0 || hplp == 1)); 900ef18a901SEtienne Carriere 901c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, 90242032ea0SEtienne Carriere hplp << LDO_BUCK_HPLP_POS, 90342032ea0SEtienne Carriere BIT(LDO_BUCK_HPLP_POS)); 904c7cf2933SEtienne Carriere } 905c7cf2933SEtienne Carriere 906eb5d5313SEtienne Carriere int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg, unsigned int mode) 907eb5d5313SEtienne Carriere { 908ef18a901SEtienne Carriere assert(cfg->lp_reg && (mode == 0 || mode == 1)); 909eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, 91042032ea0SEtienne Carriere mode << LDO_BUCK_HPLP_POS, 91142032ea0SEtienne Carriere BIT(LDO_BUCK_HPLP_POS)); 912eb5d5313SEtienne Carriere } 913eb5d5313SEtienne Carriere 914c7cf2933SEtienne Carriere int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts) 915c7cf2933SEtienne Carriere { 9166a63363bSEtienne Carriere size_t voltage_index = voltage_to_index(name, millivolts); 917c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 918c7cf2933SEtienne Carriere uint8_t mask = 0; 919c7cf2933SEtienne Carriere 9206a63363bSEtienne Carriere assert(voltage_index != VOLTAGE_INDEX_INVALID); 9216a63363bSEtienne Carriere 9221764a894SEtienne Carriere mask = find_plat_mask(name); 9231764a894SEtienne Carriere if (!mask) 924c7cf2933SEtienne Carriere return 0; 925c7cf2933SEtienne Carriere 926c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, voltage_index << 2, 927c7cf2933SEtienne Carriere mask); 928c7cf2933SEtienne Carriere } 929c7cf2933SEtienne Carriere 930eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */ 931eb5d5313SEtienne Carriere int stpmic1_lp_voltage_cfg(const char *name, uint16_t millivolts, 932eb5d5313SEtienne Carriere struct stpmic1_lp_cfg *cfg) 933eb5d5313SEtienne Carriere 934eb5d5313SEtienne Carriere { 9356a63363bSEtienne Carriere size_t voltage_index = voltage_to_index(name, millivolts); 936eb5d5313SEtienne Carriere uint8_t mask = 0; 937eb5d5313SEtienne Carriere 9381764a894SEtienne Carriere mask = find_plat_mask(name); 9391764a894SEtienne Carriere if (!mask) 940eb5d5313SEtienne Carriere return 1; 941eb5d5313SEtienne Carriere 9426a63363bSEtienne Carriere assert(voltage_index != VOLTAGE_INDEX_INVALID && 9436a63363bSEtienne Carriere cfg->lp_reg == get_regulator_data(name)->low_power_reg); 9446a63363bSEtienne Carriere 945eb5d5313SEtienne Carriere cfg->value = voltage_index << 2; 946eb5d5313SEtienne Carriere cfg->mask = mask; 947eb5d5313SEtienne Carriere 948eb5d5313SEtienne Carriere return 0; 949eb5d5313SEtienne Carriere } 950eb5d5313SEtienne Carriere 951eb5d5313SEtienne Carriere int stpmic1_lp_voltage_unpg(struct stpmic1_lp_cfg *cfg) 952eb5d5313SEtienne Carriere { 953ef18a901SEtienne Carriere assert(cfg->lp_reg); 954ef18a901SEtienne Carriere 955eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, cfg->value, cfg->mask); 956eb5d5313SEtienne Carriere } 957eb5d5313SEtienne Carriere 958c7cf2933SEtienne Carriere int stpmic1_register_read(uint8_t register_id, uint8_t *value) 959c7cf2933SEtienne Carriere { 960c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 961c7cf2933SEtienne Carriere 962eb5d5313SEtienne Carriere return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr, 963eb5d5313SEtienne Carriere register_id, value, 964eb5d5313SEtienne Carriere false /* !write */); 965c7cf2933SEtienne Carriere } 966c7cf2933SEtienne Carriere 967c7cf2933SEtienne Carriere int stpmic1_register_write(uint8_t register_id, uint8_t value) 968c7cf2933SEtienne Carriere { 969c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 970c7cf2933SEtienne Carriere uint8_t val = value; 971c7cf2933SEtienne Carriere 972eb5d5313SEtienne Carriere return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr, 973eb5d5313SEtienne Carriere register_id, &val, 974eb5d5313SEtienne Carriere true /* write */); 975c7cf2933SEtienne Carriere } 976c7cf2933SEtienne Carriere 977c7cf2933SEtienne Carriere int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask) 978c7cf2933SEtienne Carriere { 979c7cf2933SEtienne Carriere int status = 0; 980c7cf2933SEtienne Carriere uint8_t val = 0; 981c7cf2933SEtienne Carriere 982c7cf2933SEtienne Carriere status = stpmic1_register_read(register_id, &val); 983c7cf2933SEtienne Carriere if (status) 984c7cf2933SEtienne Carriere return status; 985c7cf2933SEtienne Carriere 986c7cf2933SEtienne Carriere val = (val & ~mask) | (value & mask); 987c7cf2933SEtienne Carriere 988c7cf2933SEtienne Carriere return stpmic1_register_write(register_id, val); 989c7cf2933SEtienne Carriere } 990c7cf2933SEtienne Carriere 991c7cf2933SEtienne Carriere void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr) 992c7cf2933SEtienne Carriere { 993c7cf2933SEtienne Carriere pmic_i2c_handle = i2c_handle; 994c7cf2933SEtienne Carriere pmic_i2c_addr = i2c_addr; 995c7cf2933SEtienne Carriere } 996c7cf2933SEtienne Carriere 997c7cf2933SEtienne Carriere void stpmic1_dump_regulators(void) 998c7cf2933SEtienne Carriere { 999c7cf2933SEtienne Carriere size_t i = 0; 1000c7cf2933SEtienne Carriere char __maybe_unused const *name = NULL; 1001c7cf2933SEtienne Carriere 1002c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) { 1003c7cf2933SEtienne Carriere if (!regulators_table[i].control_reg) 1004c7cf2933SEtienne Carriere continue; 1005c7cf2933SEtienne Carriere 1006c7cf2933SEtienne Carriere name = regulators_table[i].dt_node_name; 1007c7cf2933SEtienne Carriere DMSG("PMIC regul %s: %sable, %dmV", 1008c7cf2933SEtienne Carriere name, stpmic1_is_regulator_enabled(name) ? "en" : "dis", 1009c7cf2933SEtienne Carriere stpmic1_regulator_voltage_get(name)); 1010c7cf2933SEtienne Carriere } 1011c7cf2933SEtienne Carriere } 1012c7cf2933SEtienne Carriere 1013c7cf2933SEtienne Carriere int stpmic1_get_version(unsigned long *version) 1014c7cf2933SEtienne Carriere { 1015c7cf2933SEtienne Carriere uint8_t read_val = 0; 1016c7cf2933SEtienne Carriere 1017c7cf2933SEtienne Carriere if (stpmic1_register_read(VERSION_STATUS_REG, &read_val)) 1018c7cf2933SEtienne Carriere return -1; 1019c7cf2933SEtienne Carriere 1020c7cf2933SEtienne Carriere *version = read_val; 1021c7cf2933SEtienne Carriere return 0; 1022c7cf2933SEtienne Carriere } 1023