1c7cf2933SEtienne Carriere // SPDX-License-Identifier: BSD-3-Clause 2c7cf2933SEtienne Carriere /* 3*68cfb83dSEtienne Carriere * Copyright (c) 2016-2020, STMicroelectronics - All Rights Reserved 4c7cf2933SEtienne Carriere */ 5c7cf2933SEtienne Carriere 6c7cf2933SEtienne Carriere #include <assert.h> 7c7cf2933SEtienne Carriere #include <drivers/stpmic1.h> 8c7cf2933SEtienne Carriere #include <kernel/panic.h> 9c7cf2933SEtienne Carriere #include <platform_config.h> 10c7cf2933SEtienne Carriere #include <stdint.h> 11c7cf2933SEtienne Carriere #include <string.h> 12c7cf2933SEtienne Carriere #include <trace.h> 13c7cf2933SEtienne Carriere 14c7cf2933SEtienne Carriere struct regul_struct { 15c7cf2933SEtienne Carriere const char *dt_node_name; 16c7cf2933SEtienne Carriere const uint16_t *voltage_table; 17c7cf2933SEtienne Carriere uint8_t voltage_table_size; 18c7cf2933SEtienne Carriere uint8_t control_reg; 19c7cf2933SEtienne Carriere uint8_t low_power_reg; 20*68cfb83dSEtienne Carriere uint8_t enable_pos; 21c7cf2933SEtienne Carriere uint8_t pull_down_reg; 22c7cf2933SEtienne Carriere uint8_t pull_down_pos; 23c7cf2933SEtienne Carriere uint8_t mask_reset_reg; 24c7cf2933SEtienne Carriere uint8_t mask_reset_pos; 25c7cf2933SEtienne Carriere }; 26c7cf2933SEtienne Carriere 27c7cf2933SEtienne Carriere static struct i2c_handle_s *pmic_i2c_handle; 28c7cf2933SEtienne Carriere static uint16_t pmic_i2c_addr; 29c7cf2933SEtienne Carriere 30c7cf2933SEtienne Carriere /* Voltage tables in mV */ 31c7cf2933SEtienne Carriere static const uint16_t buck1_voltage_table[] = { 32c7cf2933SEtienne Carriere 725, 33c7cf2933SEtienne Carriere 725, 34c7cf2933SEtienne Carriere 725, 35c7cf2933SEtienne Carriere 725, 36c7cf2933SEtienne Carriere 725, 37c7cf2933SEtienne Carriere 725, 38c7cf2933SEtienne Carriere 750, 39c7cf2933SEtienne Carriere 775, 40c7cf2933SEtienne Carriere 800, 41c7cf2933SEtienne Carriere 825, 42c7cf2933SEtienne Carriere 850, 43c7cf2933SEtienne Carriere 875, 44c7cf2933SEtienne Carriere 900, 45c7cf2933SEtienne Carriere 925, 46c7cf2933SEtienne Carriere 950, 47c7cf2933SEtienne Carriere 975, 48c7cf2933SEtienne Carriere 1000, 49c7cf2933SEtienne Carriere 1025, 50c7cf2933SEtienne Carriere 1050, 51c7cf2933SEtienne Carriere 1075, 52c7cf2933SEtienne Carriere 1100, 53c7cf2933SEtienne Carriere 1125, 54c7cf2933SEtienne Carriere 1150, 55c7cf2933SEtienne Carriere 1175, 56c7cf2933SEtienne Carriere 1200, 57c7cf2933SEtienne Carriere 1225, 58c7cf2933SEtienne Carriere 1250, 59c7cf2933SEtienne Carriere 1275, 60c7cf2933SEtienne Carriere 1300, 61c7cf2933SEtienne Carriere 1325, 62c7cf2933SEtienne Carriere 1350, 63c7cf2933SEtienne Carriere 1375, 64c7cf2933SEtienne Carriere 1400, 65c7cf2933SEtienne Carriere 1425, 66c7cf2933SEtienne Carriere 1450, 67c7cf2933SEtienne Carriere 1475, 68c7cf2933SEtienne Carriere 1500, 69c7cf2933SEtienne Carriere 1500, 70c7cf2933SEtienne Carriere 1500, 71c7cf2933SEtienne Carriere 1500, 72c7cf2933SEtienne Carriere 1500, 73c7cf2933SEtienne Carriere 1500, 74c7cf2933SEtienne Carriere 1500, 75c7cf2933SEtienne Carriere 1500, 76c7cf2933SEtienne Carriere 1500, 77c7cf2933SEtienne Carriere 1500, 78c7cf2933SEtienne Carriere 1500, 79c7cf2933SEtienne Carriere 1500, 80c7cf2933SEtienne Carriere 1500, 81c7cf2933SEtienne Carriere 1500, 82c7cf2933SEtienne Carriere 1500, 83c7cf2933SEtienne Carriere 1500, 84c7cf2933SEtienne Carriere 1500, 85c7cf2933SEtienne Carriere 1500, 86c7cf2933SEtienne Carriere 1500, 87c7cf2933SEtienne Carriere 1500, 88c7cf2933SEtienne Carriere 1500, 89c7cf2933SEtienne Carriere 1500, 90c7cf2933SEtienne Carriere 1500, 91c7cf2933SEtienne Carriere 1500, 92c7cf2933SEtienne Carriere 1500, 93c7cf2933SEtienne Carriere 1500, 94c7cf2933SEtienne Carriere 1500, 95c7cf2933SEtienne Carriere 1500, 96c7cf2933SEtienne Carriere }; 97c7cf2933SEtienne Carriere 98c7cf2933SEtienne Carriere static const uint16_t buck2_voltage_table[] = { 99c7cf2933SEtienne Carriere 1000, 100c7cf2933SEtienne Carriere 1000, 101c7cf2933SEtienne Carriere 1000, 102c7cf2933SEtienne Carriere 1000, 103c7cf2933SEtienne Carriere 1000, 104c7cf2933SEtienne Carriere 1000, 105c7cf2933SEtienne Carriere 1000, 106c7cf2933SEtienne Carriere 1000, 107c7cf2933SEtienne Carriere 1000, 108c7cf2933SEtienne Carriere 1000, 109c7cf2933SEtienne Carriere 1000, 110c7cf2933SEtienne Carriere 1000, 111c7cf2933SEtienne Carriere 1000, 112c7cf2933SEtienne Carriere 1000, 113c7cf2933SEtienne Carriere 1000, 114c7cf2933SEtienne Carriere 1000, 115c7cf2933SEtienne Carriere 1000, 116c7cf2933SEtienne Carriere 1000, 117c7cf2933SEtienne Carriere 1050, 118c7cf2933SEtienne Carriere 1050, 119c7cf2933SEtienne Carriere 1100, 120c7cf2933SEtienne Carriere 1100, 121c7cf2933SEtienne Carriere 1150, 122c7cf2933SEtienne Carriere 1150, 123c7cf2933SEtienne Carriere 1200, 124c7cf2933SEtienne Carriere 1200, 125c7cf2933SEtienne Carriere 1250, 126c7cf2933SEtienne Carriere 1250, 127c7cf2933SEtienne Carriere 1300, 128c7cf2933SEtienne Carriere 1300, 129c7cf2933SEtienne Carriere 1350, 130c7cf2933SEtienne Carriere 1350, 131c7cf2933SEtienne Carriere 1400, 132c7cf2933SEtienne Carriere 1400, 133c7cf2933SEtienne Carriere 1450, 134c7cf2933SEtienne Carriere 1450, 135c7cf2933SEtienne Carriere 1500, 136c7cf2933SEtienne Carriere }; 137c7cf2933SEtienne Carriere 138c7cf2933SEtienne Carriere static const uint16_t buck3_voltage_table[] = { 139c7cf2933SEtienne Carriere 1000, 140c7cf2933SEtienne Carriere 1000, 141c7cf2933SEtienne Carriere 1000, 142c7cf2933SEtienne Carriere 1000, 143c7cf2933SEtienne Carriere 1000, 144c7cf2933SEtienne Carriere 1000, 145c7cf2933SEtienne Carriere 1000, 146c7cf2933SEtienne Carriere 1000, 147c7cf2933SEtienne Carriere 1000, 148c7cf2933SEtienne Carriere 1000, 149c7cf2933SEtienne Carriere 1000, 150c7cf2933SEtienne Carriere 1000, 151c7cf2933SEtienne Carriere 1000, 152c7cf2933SEtienne Carriere 1000, 153c7cf2933SEtienne Carriere 1000, 154c7cf2933SEtienne Carriere 1000, 155c7cf2933SEtienne Carriere 1000, 156c7cf2933SEtienne Carriere 1000, 157c7cf2933SEtienne Carriere 1000, 158c7cf2933SEtienne Carriere 1000, 159c7cf2933SEtienne Carriere 1100, 160c7cf2933SEtienne Carriere 1100, 161c7cf2933SEtienne Carriere 1100, 162c7cf2933SEtienne Carriere 1100, 163c7cf2933SEtienne Carriere 1200, 164c7cf2933SEtienne Carriere 1200, 165c7cf2933SEtienne Carriere 1200, 166c7cf2933SEtienne Carriere 1200, 167c7cf2933SEtienne Carriere 1300, 168c7cf2933SEtienne Carriere 1300, 169c7cf2933SEtienne Carriere 1300, 170c7cf2933SEtienne Carriere 1300, 171c7cf2933SEtienne Carriere 1400, 172c7cf2933SEtienne Carriere 1400, 173c7cf2933SEtienne Carriere 1400, 174c7cf2933SEtienne Carriere 1400, 175c7cf2933SEtienne Carriere 1500, 176c7cf2933SEtienne Carriere 1600, 177c7cf2933SEtienne Carriere 1700, 178c7cf2933SEtienne Carriere 1800, 179c7cf2933SEtienne Carriere 1900, 180c7cf2933SEtienne Carriere 2000, 181c7cf2933SEtienne Carriere 2100, 182c7cf2933SEtienne Carriere 2200, 183c7cf2933SEtienne Carriere 2300, 184c7cf2933SEtienne Carriere 2400, 185c7cf2933SEtienne Carriere 2500, 186c7cf2933SEtienne Carriere 2600, 187c7cf2933SEtienne Carriere 2700, 188c7cf2933SEtienne Carriere 2800, 189c7cf2933SEtienne Carriere 2900, 190c7cf2933SEtienne Carriere 3000, 191c7cf2933SEtienne Carriere 3100, 192c7cf2933SEtienne Carriere 3200, 193c7cf2933SEtienne Carriere 3300, 194c7cf2933SEtienne Carriere 3400, 195c7cf2933SEtienne Carriere }; 196c7cf2933SEtienne Carriere 197c7cf2933SEtienne Carriere static const uint16_t buck4_voltage_table[] = { 198c7cf2933SEtienne Carriere 600, 199c7cf2933SEtienne Carriere 625, 200c7cf2933SEtienne Carriere 650, 201c7cf2933SEtienne Carriere 675, 202c7cf2933SEtienne Carriere 700, 203c7cf2933SEtienne Carriere 725, 204c7cf2933SEtienne Carriere 750, 205c7cf2933SEtienne Carriere 775, 206c7cf2933SEtienne Carriere 800, 207c7cf2933SEtienne Carriere 825, 208c7cf2933SEtienne Carriere 850, 209c7cf2933SEtienne Carriere 875, 210c7cf2933SEtienne Carriere 900, 211c7cf2933SEtienne Carriere 925, 212c7cf2933SEtienne Carriere 950, 213c7cf2933SEtienne Carriere 975, 214c7cf2933SEtienne Carriere 1000, 215c7cf2933SEtienne Carriere 1025, 216c7cf2933SEtienne Carriere 1050, 217c7cf2933SEtienne Carriere 1075, 218c7cf2933SEtienne Carriere 1100, 219c7cf2933SEtienne Carriere 1125, 220c7cf2933SEtienne Carriere 1150, 221c7cf2933SEtienne Carriere 1175, 222c7cf2933SEtienne Carriere 1200, 223c7cf2933SEtienne Carriere 1225, 224c7cf2933SEtienne Carriere 1250, 225c7cf2933SEtienne Carriere 1275, 226c7cf2933SEtienne Carriere 1300, 227c7cf2933SEtienne Carriere 1300, 228c7cf2933SEtienne Carriere 1350, 229c7cf2933SEtienne Carriere 1350, 230c7cf2933SEtienne Carriere 1400, 231c7cf2933SEtienne Carriere 1400, 232c7cf2933SEtienne Carriere 1450, 233c7cf2933SEtienne Carriere 1450, 234c7cf2933SEtienne Carriere 1500, 235c7cf2933SEtienne Carriere 1600, 236c7cf2933SEtienne Carriere 1700, 237c7cf2933SEtienne Carriere 1800, 238c7cf2933SEtienne Carriere 1900, 239c7cf2933SEtienne Carriere 2000, 240c7cf2933SEtienne Carriere 2100, 241c7cf2933SEtienne Carriere 2200, 242c7cf2933SEtienne Carriere 2300, 243c7cf2933SEtienne Carriere 2400, 244c7cf2933SEtienne Carriere 2500, 245c7cf2933SEtienne Carriere 2600, 246c7cf2933SEtienne Carriere 2700, 247c7cf2933SEtienne Carriere 2800, 248c7cf2933SEtienne Carriere 2900, 249c7cf2933SEtienne Carriere 3000, 250c7cf2933SEtienne Carriere 3100, 251c7cf2933SEtienne Carriere 3200, 252c7cf2933SEtienne Carriere 3300, 253c7cf2933SEtienne Carriere 3400, 254c7cf2933SEtienne Carriere 3500, 255c7cf2933SEtienne Carriere 3600, 256c7cf2933SEtienne Carriere 3700, 257c7cf2933SEtienne Carriere 3800, 258c7cf2933SEtienne Carriere 3900, 259c7cf2933SEtienne Carriere }; 260c7cf2933SEtienne Carriere 261c7cf2933SEtienne Carriere static const uint16_t ldo1_voltage_table[] = { 262c7cf2933SEtienne Carriere 1700, 263c7cf2933SEtienne Carriere 1700, 264c7cf2933SEtienne Carriere 1700, 265c7cf2933SEtienne Carriere 1700, 266c7cf2933SEtienne Carriere 1700, 267c7cf2933SEtienne Carriere 1700, 268c7cf2933SEtienne Carriere 1700, 269c7cf2933SEtienne Carriere 1700, 270c7cf2933SEtienne Carriere 1700, 271c7cf2933SEtienne Carriere 1800, 272c7cf2933SEtienne Carriere 1900, 273c7cf2933SEtienne Carriere 2000, 274c7cf2933SEtienne Carriere 2100, 275c7cf2933SEtienne Carriere 2200, 276c7cf2933SEtienne Carriere 2300, 277c7cf2933SEtienne Carriere 2400, 278c7cf2933SEtienne Carriere 2500, 279c7cf2933SEtienne Carriere 2600, 280c7cf2933SEtienne Carriere 2700, 281c7cf2933SEtienne Carriere 2800, 282c7cf2933SEtienne Carriere 2900, 283c7cf2933SEtienne Carriere 3000, 284c7cf2933SEtienne Carriere 3100, 285c7cf2933SEtienne Carriere 3200, 286c7cf2933SEtienne Carriere 3300, 287c7cf2933SEtienne Carriere }; 288c7cf2933SEtienne Carriere 289c7cf2933SEtienne Carriere static const uint16_t ldo2_voltage_table[] = { 290c7cf2933SEtienne Carriere 1700, 291c7cf2933SEtienne Carriere 1700, 292c7cf2933SEtienne Carriere 1700, 293c7cf2933SEtienne Carriere 1700, 294c7cf2933SEtienne Carriere 1700, 295c7cf2933SEtienne Carriere 1700, 296c7cf2933SEtienne Carriere 1700, 297c7cf2933SEtienne Carriere 1700, 298c7cf2933SEtienne Carriere 1700, 299c7cf2933SEtienne Carriere 1800, 300c7cf2933SEtienne Carriere 1900, 301c7cf2933SEtienne Carriere 2000, 302c7cf2933SEtienne Carriere 2100, 303c7cf2933SEtienne Carriere 2200, 304c7cf2933SEtienne Carriere 2300, 305c7cf2933SEtienne Carriere 2400, 306c7cf2933SEtienne Carriere 2500, 307c7cf2933SEtienne Carriere 2600, 308c7cf2933SEtienne Carriere 2700, 309c7cf2933SEtienne Carriere 2800, 310c7cf2933SEtienne Carriere 2900, 311c7cf2933SEtienne Carriere 3000, 312c7cf2933SEtienne Carriere 3100, 313c7cf2933SEtienne Carriere 3200, 314c7cf2933SEtienne Carriere 3300, 315c7cf2933SEtienne Carriere }; 316c7cf2933SEtienne Carriere 317c7cf2933SEtienne Carriere static const uint16_t ldo3_voltage_table[] = { 318c7cf2933SEtienne Carriere 1700, 319c7cf2933SEtienne Carriere 1700, 320c7cf2933SEtienne Carriere 1700, 321c7cf2933SEtienne Carriere 1700, 322c7cf2933SEtienne Carriere 1700, 323c7cf2933SEtienne Carriere 1700, 324c7cf2933SEtienne Carriere 1700, 325c7cf2933SEtienne Carriere 1700, 326c7cf2933SEtienne Carriere 1700, 327c7cf2933SEtienne Carriere 1800, 328c7cf2933SEtienne Carriere 1900, 329c7cf2933SEtienne Carriere 2000, 330c7cf2933SEtienne Carriere 2100, 331c7cf2933SEtienne Carriere 2200, 332c7cf2933SEtienne Carriere 2300, 333c7cf2933SEtienne Carriere 2400, 334c7cf2933SEtienne Carriere 2500, 335c7cf2933SEtienne Carriere 2600, 336c7cf2933SEtienne Carriere 2700, 337c7cf2933SEtienne Carriere 2800, 338c7cf2933SEtienne Carriere 2900, 339c7cf2933SEtienne Carriere 3000, 340c7cf2933SEtienne Carriere 3100, 341c7cf2933SEtienne Carriere 3200, 342c7cf2933SEtienne Carriere 3300, 343c7cf2933SEtienne Carriere 3300, 344c7cf2933SEtienne Carriere 3300, 345c7cf2933SEtienne Carriere 3300, 346c7cf2933SEtienne Carriere 3300, 347c7cf2933SEtienne Carriere 3300, 348c7cf2933SEtienne Carriere 3300, 349f7e28951SEtienne Carriere 500, /* VOUT2/2 (Sink/source mode) */ 350c7cf2933SEtienne Carriere 0xFFFF, /* VREFDDR */ 351c7cf2933SEtienne Carriere }; 352c7cf2933SEtienne Carriere 353c7cf2933SEtienne Carriere static const uint16_t ldo5_voltage_table[] = { 354c7cf2933SEtienne Carriere 1700, 355c7cf2933SEtienne Carriere 1700, 356c7cf2933SEtienne Carriere 1700, 357c7cf2933SEtienne Carriere 1700, 358c7cf2933SEtienne Carriere 1700, 359c7cf2933SEtienne Carriere 1700, 360c7cf2933SEtienne Carriere 1700, 361c7cf2933SEtienne Carriere 1700, 362c7cf2933SEtienne Carriere 1700, 363c7cf2933SEtienne Carriere 1800, 364c7cf2933SEtienne Carriere 1900, 365c7cf2933SEtienne Carriere 2000, 366c7cf2933SEtienne Carriere 2100, 367c7cf2933SEtienne Carriere 2200, 368c7cf2933SEtienne Carriere 2300, 369c7cf2933SEtienne Carriere 2400, 370c7cf2933SEtienne Carriere 2500, 371c7cf2933SEtienne Carriere 2600, 372c7cf2933SEtienne Carriere 2700, 373c7cf2933SEtienne Carriere 2800, 374c7cf2933SEtienne Carriere 2900, 375c7cf2933SEtienne Carriere 3000, 376c7cf2933SEtienne Carriere 3100, 377c7cf2933SEtienne Carriere 3200, 378c7cf2933SEtienne Carriere 3300, 379c7cf2933SEtienne Carriere 3400, 380c7cf2933SEtienne Carriere 3500, 381c7cf2933SEtienne Carriere 3600, 382c7cf2933SEtienne Carriere 3700, 383c7cf2933SEtienne Carriere 3800, 384c7cf2933SEtienne Carriere 3900, 385c7cf2933SEtienne Carriere }; 386c7cf2933SEtienne Carriere 387c7cf2933SEtienne Carriere static const uint16_t ldo6_voltage_table[] = { 388c7cf2933SEtienne Carriere 900, 389c7cf2933SEtienne Carriere 1000, 390c7cf2933SEtienne Carriere 1100, 391c7cf2933SEtienne Carriere 1200, 392c7cf2933SEtienne Carriere 1300, 393c7cf2933SEtienne Carriere 1400, 394c7cf2933SEtienne Carriere 1500, 395c7cf2933SEtienne Carriere 1600, 396c7cf2933SEtienne Carriere 1700, 397c7cf2933SEtienne Carriere 1800, 398c7cf2933SEtienne Carriere 1900, 399c7cf2933SEtienne Carriere 2000, 400c7cf2933SEtienne Carriere 2100, 401c7cf2933SEtienne Carriere 2200, 402c7cf2933SEtienne Carriere 2300, 403c7cf2933SEtienne Carriere 2400, 404c7cf2933SEtienne Carriere 2500, 405c7cf2933SEtienne Carriere 2600, 406c7cf2933SEtienne Carriere 2700, 407c7cf2933SEtienne Carriere 2800, 408c7cf2933SEtienne Carriere 2900, 409c7cf2933SEtienne Carriere 3000, 410c7cf2933SEtienne Carriere 3100, 411c7cf2933SEtienne Carriere 3200, 412c7cf2933SEtienne Carriere 3300, 413c7cf2933SEtienne Carriere }; 414c7cf2933SEtienne Carriere 415c7cf2933SEtienne Carriere static const uint16_t ldo4_voltage_table[] = { 416c7cf2933SEtienne Carriere 3300, 417c7cf2933SEtienne Carriere }; 418c7cf2933SEtienne Carriere 419c7cf2933SEtienne Carriere static const uint16_t vref_ddr_voltage_table[] = { 420c7cf2933SEtienne Carriere 3300, 421c7cf2933SEtienne Carriere }; 422c7cf2933SEtienne Carriere 423c7cf2933SEtienne Carriere /* Table of Regulators in PMIC SoC */ 424c7cf2933SEtienne Carriere static const struct regul_struct regulators_table[] = { 425c7cf2933SEtienne Carriere { 426c7cf2933SEtienne Carriere .dt_node_name = "buck1", 427c7cf2933SEtienne Carriere .voltage_table = buck1_voltage_table, 428c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck1_voltage_table), 429c7cf2933SEtienne Carriere .control_reg = BUCK1_CONTROL_REG, 430c7cf2933SEtienne Carriere .low_power_reg = BUCK1_PWRCTRL_REG, 431*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 432c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 433c7cf2933SEtienne Carriere .pull_down_pos = BUCK1_PULL_DOWN_SHIFT, 434c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 435c7cf2933SEtienne Carriere .mask_reset_pos = BUCK1_MASK_RESET_SHIFT, 436c7cf2933SEtienne Carriere }, 437c7cf2933SEtienne Carriere { 438c7cf2933SEtienne Carriere .dt_node_name = "buck2", 439c7cf2933SEtienne Carriere .voltage_table = buck2_voltage_table, 440c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck2_voltage_table), 441c7cf2933SEtienne Carriere .control_reg = BUCK2_CONTROL_REG, 442c7cf2933SEtienne Carriere .low_power_reg = BUCK2_PWRCTRL_REG, 443*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 444c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 445c7cf2933SEtienne Carriere .pull_down_pos = BUCK2_PULL_DOWN_SHIFT, 446c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 447c7cf2933SEtienne Carriere .mask_reset_pos = BUCK2_MASK_RESET_SHIFT, 448c7cf2933SEtienne Carriere }, 449c7cf2933SEtienne Carriere { 450c7cf2933SEtienne Carriere .dt_node_name = "buck3", 451c7cf2933SEtienne Carriere .voltage_table = buck3_voltage_table, 452c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck3_voltage_table), 453c7cf2933SEtienne Carriere .control_reg = BUCK3_CONTROL_REG, 454c7cf2933SEtienne Carriere .low_power_reg = BUCK3_PWRCTRL_REG, 455*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 456c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 457c7cf2933SEtienne Carriere .pull_down_pos = BUCK3_PULL_DOWN_SHIFT, 458c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 459c7cf2933SEtienne Carriere .mask_reset_pos = BUCK3_MASK_RESET_SHIFT, 460c7cf2933SEtienne Carriere }, 461c7cf2933SEtienne Carriere { 462c7cf2933SEtienne Carriere .dt_node_name = "buck4", 463c7cf2933SEtienne Carriere .voltage_table = buck4_voltage_table, 464c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(buck4_voltage_table), 465c7cf2933SEtienne Carriere .control_reg = BUCK4_CONTROL_REG, 466c7cf2933SEtienne Carriere .low_power_reg = BUCK4_PWRCTRL_REG, 467*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 468c7cf2933SEtienne Carriere .pull_down_reg = BUCK_PULL_DOWN_REG, 469c7cf2933SEtienne Carriere .pull_down_pos = BUCK4_PULL_DOWN_SHIFT, 470c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_BUCK_REG, 471c7cf2933SEtienne Carriere .mask_reset_pos = BUCK4_MASK_RESET_SHIFT, 472c7cf2933SEtienne Carriere }, 473c7cf2933SEtienne Carriere { 474c7cf2933SEtienne Carriere .dt_node_name = "ldo1", 475c7cf2933SEtienne Carriere .voltage_table = ldo1_voltage_table, 476c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo1_voltage_table), 477c7cf2933SEtienne Carriere .control_reg = LDO1_CONTROL_REG, 478c7cf2933SEtienne Carriere .low_power_reg = LDO1_PWRCTRL_REG, 479*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 480c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 481c7cf2933SEtienne Carriere .mask_reset_pos = LDO1_MASK_RESET_SHIFT, 482c7cf2933SEtienne Carriere }, 483c7cf2933SEtienne Carriere { 484c7cf2933SEtienne Carriere .dt_node_name = "ldo2", 485c7cf2933SEtienne Carriere .voltage_table = ldo2_voltage_table, 486c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo2_voltage_table), 487c7cf2933SEtienne Carriere .control_reg = LDO2_CONTROL_REG, 488c7cf2933SEtienne Carriere .low_power_reg = LDO2_PWRCTRL_REG, 489*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 490c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 491c7cf2933SEtienne Carriere .mask_reset_pos = LDO2_MASK_RESET_SHIFT, 492c7cf2933SEtienne Carriere }, 493c7cf2933SEtienne Carriere { 494c7cf2933SEtienne Carriere .dt_node_name = "ldo3", 495c7cf2933SEtienne Carriere .voltage_table = ldo3_voltage_table, 496c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo3_voltage_table), 497c7cf2933SEtienne Carriere .control_reg = LDO3_CONTROL_REG, 498c7cf2933SEtienne Carriere .low_power_reg = LDO3_PWRCTRL_REG, 499*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 500c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 501c7cf2933SEtienne Carriere .mask_reset_pos = LDO3_MASK_RESET_SHIFT, 502c7cf2933SEtienne Carriere }, 503c7cf2933SEtienne Carriere { 504c7cf2933SEtienne Carriere .dt_node_name = "ldo4", 505c7cf2933SEtienne Carriere .voltage_table = ldo4_voltage_table, 506c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo4_voltage_table), 507c7cf2933SEtienne Carriere .control_reg = LDO4_CONTROL_REG, 508c7cf2933SEtienne Carriere .low_power_reg = LDO4_PWRCTRL_REG, 509*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 510c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 511c7cf2933SEtienne Carriere .mask_reset_pos = LDO4_MASK_RESET_SHIFT, 512c7cf2933SEtienne Carriere }, 513c7cf2933SEtienne Carriere { 514c7cf2933SEtienne Carriere .dt_node_name = "ldo5", 515c7cf2933SEtienne Carriere .voltage_table = ldo5_voltage_table, 516c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo5_voltage_table), 517c7cf2933SEtienne Carriere .control_reg = LDO5_CONTROL_REG, 518c7cf2933SEtienne Carriere .low_power_reg = LDO5_PWRCTRL_REG, 519*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 520c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 521c7cf2933SEtienne Carriere .mask_reset_pos = LDO5_MASK_RESET_SHIFT, 522c7cf2933SEtienne Carriere }, 523c7cf2933SEtienne Carriere { 524c7cf2933SEtienne Carriere .dt_node_name = "ldo6", 525c7cf2933SEtienne Carriere .voltage_table = ldo6_voltage_table, 526c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(ldo6_voltage_table), 527c7cf2933SEtienne Carriere .control_reg = LDO6_CONTROL_REG, 528c7cf2933SEtienne Carriere .low_power_reg = LDO6_PWRCTRL_REG, 529*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 530c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 531c7cf2933SEtienne Carriere .mask_reset_pos = LDO6_MASK_RESET_SHIFT, 532c7cf2933SEtienne Carriere }, 533c7cf2933SEtienne Carriere { 534c7cf2933SEtienne Carriere .dt_node_name = "vref_ddr", 535c7cf2933SEtienne Carriere .voltage_table = vref_ddr_voltage_table, 536c7cf2933SEtienne Carriere .voltage_table_size = ARRAY_SIZE(vref_ddr_voltage_table), 537c7cf2933SEtienne Carriere .control_reg = VREF_DDR_CONTROL_REG, 538c7cf2933SEtienne Carriere .low_power_reg = VREF_DDR_PWRCTRL_REG, 539*68cfb83dSEtienne Carriere .enable_pos = LDO_BUCK_ENABLE_POS, 540c7cf2933SEtienne Carriere .mask_reset_reg = MASK_RESET_LDO_REG, 541c7cf2933SEtienne Carriere .mask_reset_pos = VREF_DDR_MASK_RESET_SHIFT, 542c7cf2933SEtienne Carriere }, 543c7cf2933SEtienne Carriere { 544c7cf2933SEtienne Carriere .dt_node_name = "boost", 545c7cf2933SEtienne Carriere }, 546c7cf2933SEtienne Carriere { 547c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw1", 548c7cf2933SEtienne Carriere }, 549c7cf2933SEtienne Carriere { 550c7cf2933SEtienne Carriere .dt_node_name = "pwr_sw2", 551c7cf2933SEtienne Carriere }, 552c7cf2933SEtienne Carriere }; 553c7cf2933SEtienne Carriere 554c7cf2933SEtienne Carriere static const struct regul_struct *get_regulator_data(const char *name) 555c7cf2933SEtienne Carriere { 556c7cf2933SEtienne Carriere unsigned int i = 0; 557c7cf2933SEtienne Carriere 558c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) 559c7cf2933SEtienne Carriere if (strcmp(name, regulators_table[i].dt_node_name) == 0) 560c7cf2933SEtienne Carriere return ®ulators_table[i]; 561c7cf2933SEtienne Carriere 562c7cf2933SEtienne Carriere /* Regulator not found */ 563c7cf2933SEtienne Carriere panic(name); 564c7cf2933SEtienne Carriere } 565c7cf2933SEtienne Carriere 566c7cf2933SEtienne Carriere static uint8_t voltage_to_index(const char *name, uint16_t millivolts) 567c7cf2933SEtienne Carriere { 568c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 569c7cf2933SEtienne Carriere unsigned int i = 0; 570c7cf2933SEtienne Carriere 571c7cf2933SEtienne Carriere assert(regul->voltage_table); 572c7cf2933SEtienne Carriere for (i = 0; i < regul->voltage_table_size; i++) 573c7cf2933SEtienne Carriere if (regul->voltage_table[i] == millivolts) 574c7cf2933SEtienne Carriere return i; 575c7cf2933SEtienne Carriere 576c7cf2933SEtienne Carriere /* Voltage not found */ 577c7cf2933SEtienne Carriere panic(name); 578c7cf2933SEtienne Carriere } 579c7cf2933SEtienne Carriere 580c7cf2933SEtienne Carriere int stpmic1_powerctrl_on(void) 581c7cf2933SEtienne Carriere { 582c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, PWRCTRL_PIN_VALID, 583c7cf2933SEtienne Carriere PWRCTRL_PIN_VALID); 584c7cf2933SEtienne Carriere } 585c7cf2933SEtienne Carriere 586c7cf2933SEtienne Carriere int stpmic1_switch_off(void) 587c7cf2933SEtienne Carriere { 588c7cf2933SEtienne Carriere return stpmic1_register_update(MAIN_CONTROL_REG, 1, 589c7cf2933SEtienne Carriere SOFTWARE_SWITCH_OFF_ENABLED); 590c7cf2933SEtienne Carriere } 591c7cf2933SEtienne Carriere 592c7cf2933SEtienne Carriere int stpmic1_regulator_enable(const char *name) 593c7cf2933SEtienne Carriere { 594c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 595c7cf2933SEtienne Carriere 596*68cfb83dSEtienne Carriere return stpmic1_register_update(regul->control_reg, 597*68cfb83dSEtienne Carriere BIT(regul->enable_pos), 598*68cfb83dSEtienne Carriere BIT(regul->enable_pos)); 599c7cf2933SEtienne Carriere } 600c7cf2933SEtienne Carriere 601c7cf2933SEtienne Carriere int stpmic1_regulator_disable(const char *name) 602c7cf2933SEtienne Carriere { 603c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 604c7cf2933SEtienne Carriere 605*68cfb83dSEtienne Carriere return stpmic1_register_update(regul->control_reg, 0, 606*68cfb83dSEtienne Carriere BIT(regul->enable_pos)); 607c7cf2933SEtienne Carriere } 608c7cf2933SEtienne Carriere 6092619b28cSEtienne Carriere bool stpmic1_is_regulator_enabled(const char *name) 610c7cf2933SEtienne Carriere { 611c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 612c7cf2933SEtienne Carriere uint8_t val = 0; 613c7cf2933SEtienne Carriere 614c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &val)) 615c7cf2933SEtienne Carriere panic(); 616c7cf2933SEtienne Carriere 617*68cfb83dSEtienne Carriere return val & BIT(regul->enable_pos); 618c7cf2933SEtienne Carriere } 619c7cf2933SEtienne Carriere 620c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_set(const char *name, uint16_t millivolts) 621c7cf2933SEtienne Carriere { 622c7cf2933SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 623c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 624c7cf2933SEtienne Carriere uint8_t mask = 0; 625c7cf2933SEtienne Carriere 626c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 627c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 628c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 629c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 630c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 631c7cf2933SEtienne Carriere else 632c7cf2933SEtienne Carriere return 0; 633c7cf2933SEtienne Carriere 634c7cf2933SEtienne Carriere return stpmic1_register_update(regul->control_reg, 635c7cf2933SEtienne Carriere voltage_index << LDO_BUCK_VOLTAGE_SHIFT, 636c7cf2933SEtienne Carriere mask); 637c7cf2933SEtienne Carriere } 638c7cf2933SEtienne Carriere 639c7cf2933SEtienne Carriere int stpmic1_regulator_mask_reset_set(const char *name) 640c7cf2933SEtienne Carriere { 641c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 642c7cf2933SEtienne Carriere 643c7cf2933SEtienne Carriere return stpmic1_register_update(regul->mask_reset_reg, 644c7cf2933SEtienne Carriere BIT(regul->mask_reset_pos), 645c7cf2933SEtienne Carriere LDO_BUCK_RESET_MASK << 646c7cf2933SEtienne Carriere regul->mask_reset_pos); 647c7cf2933SEtienne Carriere } 648c7cf2933SEtienne Carriere 649eb5d5313SEtienne Carriere int stpmic1_bo_enable_unpg(struct stpmic1_bo_cfg *cfg) 650eb5d5313SEtienne Carriere { 651*68cfb83dSEtienne Carriere return stpmic1_register_update(cfg->ctrl_reg, 652*68cfb83dSEtienne Carriere BIT(cfg->enable_pos), 653*68cfb83dSEtienne Carriere BIT(cfg->enable_pos)); 654eb5d5313SEtienne Carriere } 655eb5d5313SEtienne Carriere 656eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */ 657eb5d5313SEtienne Carriere int stpmic1_bo_voltage_cfg(const char *name, uint16_t millivolts, 658eb5d5313SEtienne Carriere struct stpmic1_bo_cfg *cfg) 659eb5d5313SEtienne Carriere { 660eb5d5313SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 661eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 662eb5d5313SEtienne Carriere uint8_t mask = 0; 663eb5d5313SEtienne Carriere 664eb5d5313SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 665eb5d5313SEtienne Carriere if (!strcmp(name, "buck")) 666eb5d5313SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 667eb5d5313SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 668eb5d5313SEtienne Carriere mask = LDO_VOLTAGE_MASK; 669eb5d5313SEtienne Carriere else 670eb5d5313SEtienne Carriere return 1; 671eb5d5313SEtienne Carriere 672eb5d5313SEtienne Carriere cfg->ctrl_reg = regul->control_reg; 673eb5d5313SEtienne Carriere cfg->value = voltage_index << LDO_BUCK_VOLTAGE_SHIFT; 674eb5d5313SEtienne Carriere cfg->mask = mask; 675eb5d5313SEtienne Carriere 676eb5d5313SEtienne Carriere return 0; 677eb5d5313SEtienne Carriere } 678eb5d5313SEtienne Carriere 679eb5d5313SEtienne Carriere int stpmic1_bo_voltage_unpg(struct stpmic1_bo_cfg *cfg) 680eb5d5313SEtienne Carriere { 681eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->ctrl_reg, cfg->value, cfg->mask); 682eb5d5313SEtienne Carriere } 683eb5d5313SEtienne Carriere 684eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_cfg(const char *name, struct stpmic1_bo_cfg *cfg) 685eb5d5313SEtienne Carriere { 686eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 687eb5d5313SEtienne Carriere 688eb5d5313SEtienne Carriere cfg->pd_reg = regul->pull_down_reg; 689eb5d5313SEtienne Carriere cfg->pd_value = BIT(regul->pull_down_pos); 690eb5d5313SEtienne Carriere cfg->pd_mask = LDO_BUCK_PULL_DOWN_MASK << regul->pull_down_pos; 691eb5d5313SEtienne Carriere 692eb5d5313SEtienne Carriere return 0; 693eb5d5313SEtienne Carriere } 694eb5d5313SEtienne Carriere 695eb5d5313SEtienne Carriere int stpmic1_bo_pull_down_unpg(struct stpmic1_bo_cfg *cfg) 696eb5d5313SEtienne Carriere { 697eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->pd_reg, cfg->pd_value, 698eb5d5313SEtienne Carriere cfg->pd_mask); 699eb5d5313SEtienne Carriere } 700eb5d5313SEtienne Carriere 701eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_cfg(const char *name, struct stpmic1_bo_cfg *cfg) 702eb5d5313SEtienne Carriere { 703eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 704eb5d5313SEtienne Carriere 705eb5d5313SEtienne Carriere cfg->mrst_reg = regul->mask_reset_reg; 706eb5d5313SEtienne Carriere cfg->mrst_value = BIT(regul->mask_reset_pos); 707eb5d5313SEtienne Carriere cfg->mrst_mask = LDO_BUCK_RESET_MASK << regul->mask_reset_pos; 708eb5d5313SEtienne Carriere 709eb5d5313SEtienne Carriere return 0; 710eb5d5313SEtienne Carriere } 711eb5d5313SEtienne Carriere 712eb5d5313SEtienne Carriere int stpmic1_bo_mask_reset_unpg(struct stpmic1_bo_cfg *cfg) 713eb5d5313SEtienne Carriere { 714eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->mrst_reg, cfg->mrst_value, 715eb5d5313SEtienne Carriere cfg->mrst_mask); 716eb5d5313SEtienne Carriere } 717eb5d5313SEtienne Carriere 718c7cf2933SEtienne Carriere int stpmic1_regulator_voltage_get(const char *name) 719c7cf2933SEtienne Carriere { 720c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 721c7cf2933SEtienne Carriere uint8_t value = 0; 722c7cf2933SEtienne Carriere uint8_t mask = 0; 723c7cf2933SEtienne Carriere 724c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 725c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 726c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 727c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 728c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 729c7cf2933SEtienne Carriere else 730c7cf2933SEtienne Carriere return 0; 731c7cf2933SEtienne Carriere 732c7cf2933SEtienne Carriere if (stpmic1_register_read(regul->control_reg, &value)) 733c7cf2933SEtienne Carriere return -1; 734c7cf2933SEtienne Carriere 735c7cf2933SEtienne Carriere value = (value & mask) >> LDO_BUCK_VOLTAGE_SHIFT; 736c7cf2933SEtienne Carriere 737c7cf2933SEtienne Carriere if (value > regul->voltage_table_size) 738c7cf2933SEtienne Carriere return -1; 739c7cf2933SEtienne Carriere 740c7cf2933SEtienne Carriere return regul->voltage_table[value]; 741c7cf2933SEtienne Carriere } 742c7cf2933SEtienne Carriere 743c7cf2933SEtienne Carriere int stpmic1_lp_copy_reg(const char *name) 744c7cf2933SEtienne Carriere { 745c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 746c7cf2933SEtienne Carriere uint8_t val = 0; 747c7cf2933SEtienne Carriere int status = 0; 748c7cf2933SEtienne Carriere 749c7cf2933SEtienne Carriere status = stpmic1_register_read(regul->control_reg, &val); 750c7cf2933SEtienne Carriere if (status) 751c7cf2933SEtienne Carriere return status; 752c7cf2933SEtienne Carriere 753c7cf2933SEtienne Carriere return stpmic1_register_write(regul->low_power_reg, val); 754c7cf2933SEtienne Carriere } 755c7cf2933SEtienne Carriere 756eb5d5313SEtienne Carriere int stpmic1_lp_cfg(const char *name, struct stpmic1_lp_cfg *cfg) 757eb5d5313SEtienne Carriere { 758eb5d5313SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 759eb5d5313SEtienne Carriere 760eb5d5313SEtienne Carriere cfg->ctrl_reg = regul->control_reg; 761eb5d5313SEtienne Carriere cfg->lp_reg = regul->low_power_reg; 762eb5d5313SEtienne Carriere 763eb5d5313SEtienne Carriere return 0; 764eb5d5313SEtienne Carriere } 765eb5d5313SEtienne Carriere 766eb5d5313SEtienne Carriere int stpmic1_lp_load_unpg(struct stpmic1_lp_cfg *cfg) 767eb5d5313SEtienne Carriere { 768eb5d5313SEtienne Carriere uint8_t val = 0; 769eb5d5313SEtienne Carriere int status = 0; 770eb5d5313SEtienne Carriere 771eb5d5313SEtienne Carriere status = stpmic1_register_read(cfg->ctrl_reg, &val); 772eb5d5313SEtienne Carriere if (!status) 773eb5d5313SEtienne Carriere status = stpmic1_register_write(cfg->lp_reg, val); 774eb5d5313SEtienne Carriere 775eb5d5313SEtienne Carriere return status; 776eb5d5313SEtienne Carriere } 777eb5d5313SEtienne Carriere 778c7cf2933SEtienne Carriere int stpmic1_lp_reg_on_off(const char *name, uint8_t enable) 779c7cf2933SEtienne Carriere { 780c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 781c7cf2933SEtienne Carriere 782c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, enable, 783c7cf2933SEtienne Carriere LDO_BUCK_ENABLE_MASK); 784c7cf2933SEtienne Carriere } 785c7cf2933SEtienne Carriere 786eb5d5313SEtienne Carriere int stpmic1_lp_on_off_unpg(struct stpmic1_lp_cfg *cfg, int enable) 787eb5d5313SEtienne Carriere { 788eb5d5313SEtienne Carriere assert(enable == 0 || enable == 1); 789eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, enable, 790eb5d5313SEtienne Carriere LDO_BUCK_ENABLE_MASK); 791eb5d5313SEtienne Carriere } 792eb5d5313SEtienne Carriere 793c7cf2933SEtienne Carriere int stpmic1_lp_set_mode(const char *name, uint8_t hplp) 794c7cf2933SEtienne Carriere { 795c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 796c7cf2933SEtienne Carriere 797c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, 798c7cf2933SEtienne Carriere hplp << LDO_BUCK_HPLP_SHIFT, 799c7cf2933SEtienne Carriere LDO_BUCK_HPLP_ENABLE_MASK); 800c7cf2933SEtienne Carriere } 801c7cf2933SEtienne Carriere 802eb5d5313SEtienne Carriere int stpmic1_lp_mode_unpg(struct stpmic1_lp_cfg *cfg, unsigned int mode) 803eb5d5313SEtienne Carriere { 804eb5d5313SEtienne Carriere assert(mode == 0 || mode == 1); 805eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, 806eb5d5313SEtienne Carriere mode << LDO_BUCK_HPLP_SHIFT, 807eb5d5313SEtienne Carriere LDO_BUCK_HPLP_ENABLE_MASK); 808eb5d5313SEtienne Carriere } 809eb5d5313SEtienne Carriere 810c7cf2933SEtienne Carriere int stpmic1_lp_set_voltage(const char *name, uint16_t millivolts) 811c7cf2933SEtienne Carriere { 812c7cf2933SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 813c7cf2933SEtienne Carriere const struct regul_struct *regul = get_regulator_data(name); 814c7cf2933SEtienne Carriere uint8_t mask = 0; 815c7cf2933SEtienne Carriere 816c7cf2933SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 817c7cf2933SEtienne Carriere if (!strcmp(name, "buck")) 818c7cf2933SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 819c7cf2933SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 820c7cf2933SEtienne Carriere mask = LDO_VOLTAGE_MASK; 821c7cf2933SEtienne Carriere else 822c7cf2933SEtienne Carriere return 0; 823c7cf2933SEtienne Carriere 824c7cf2933SEtienne Carriere return stpmic1_register_update(regul->low_power_reg, voltage_index << 2, 825c7cf2933SEtienne Carriere mask); 826c7cf2933SEtienne Carriere } 827c7cf2933SEtienne Carriere 828eb5d5313SEtienne Carriere /* Returns 1 if no configuration are expected applied at runtime, 0 otherwise */ 829eb5d5313SEtienne Carriere int stpmic1_lp_voltage_cfg(const char *name, uint16_t millivolts, 830eb5d5313SEtienne Carriere struct stpmic1_lp_cfg *cfg) 831eb5d5313SEtienne Carriere 832eb5d5313SEtienne Carriere { 833eb5d5313SEtienne Carriere uint8_t voltage_index = voltage_to_index(name, millivolts); 834eb5d5313SEtienne Carriere uint8_t mask = 0; 835eb5d5313SEtienne Carriere 836eb5d5313SEtienne Carriere /* Voltage can be set for buck<N> or ldo<N> (except ldo4) regulators */ 837eb5d5313SEtienne Carriere if (!strcmp(name, "buck")) 838eb5d5313SEtienne Carriere mask = BUCK_VOLTAGE_MASK; 839eb5d5313SEtienne Carriere else if (!strcmp(name, "ldo") && strcmp(name, "ldo4")) 840eb5d5313SEtienne Carriere mask = LDO_VOLTAGE_MASK; 841eb5d5313SEtienne Carriere else 842eb5d5313SEtienne Carriere return 1; 843eb5d5313SEtienne Carriere 844eb5d5313SEtienne Carriere assert(cfg->lp_reg == get_regulator_data(name)->low_power_reg); 845eb5d5313SEtienne Carriere cfg->value = voltage_index << 2; 846eb5d5313SEtienne Carriere cfg->mask = mask; 847eb5d5313SEtienne Carriere 848eb5d5313SEtienne Carriere return 0; 849eb5d5313SEtienne Carriere } 850eb5d5313SEtienne Carriere 851eb5d5313SEtienne Carriere int stpmic1_lp_voltage_unpg(struct stpmic1_lp_cfg *cfg) 852eb5d5313SEtienne Carriere { 853eb5d5313SEtienne Carriere return stpmic1_register_update(cfg->lp_reg, cfg->value, cfg->mask); 854eb5d5313SEtienne Carriere } 855eb5d5313SEtienne Carriere 856c7cf2933SEtienne Carriere int stpmic1_register_read(uint8_t register_id, uint8_t *value) 857c7cf2933SEtienne Carriere { 858c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 859c7cf2933SEtienne Carriere 860eb5d5313SEtienne Carriere return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr, 861eb5d5313SEtienne Carriere register_id, value, 862eb5d5313SEtienne Carriere false /* !write */); 863c7cf2933SEtienne Carriere } 864c7cf2933SEtienne Carriere 865c7cf2933SEtienne Carriere int stpmic1_register_write(uint8_t register_id, uint8_t value) 866c7cf2933SEtienne Carriere { 867c7cf2933SEtienne Carriere struct i2c_handle_s *i2c = pmic_i2c_handle; 868c7cf2933SEtienne Carriere uint8_t val = value; 869c7cf2933SEtienne Carriere 870eb5d5313SEtienne Carriere return stm32_i2c_read_write_membyte(i2c, pmic_i2c_addr, 871eb5d5313SEtienne Carriere register_id, &val, 872eb5d5313SEtienne Carriere true /* write */); 873c7cf2933SEtienne Carriere } 874c7cf2933SEtienne Carriere 875c7cf2933SEtienne Carriere int stpmic1_register_update(uint8_t register_id, uint8_t value, uint8_t mask) 876c7cf2933SEtienne Carriere { 877c7cf2933SEtienne Carriere int status = 0; 878c7cf2933SEtienne Carriere uint8_t val = 0; 879c7cf2933SEtienne Carriere 880c7cf2933SEtienne Carriere status = stpmic1_register_read(register_id, &val); 881c7cf2933SEtienne Carriere if (status) 882c7cf2933SEtienne Carriere return status; 883c7cf2933SEtienne Carriere 884c7cf2933SEtienne Carriere val = (val & ~mask) | (value & mask); 885c7cf2933SEtienne Carriere 886c7cf2933SEtienne Carriere return stpmic1_register_write(register_id, val); 887c7cf2933SEtienne Carriere } 888c7cf2933SEtienne Carriere 889c7cf2933SEtienne Carriere void stpmic1_bind_i2c(struct i2c_handle_s *i2c_handle, uint16_t i2c_addr) 890c7cf2933SEtienne Carriere { 891c7cf2933SEtienne Carriere pmic_i2c_handle = i2c_handle; 892c7cf2933SEtienne Carriere pmic_i2c_addr = i2c_addr; 893c7cf2933SEtienne Carriere } 894c7cf2933SEtienne Carriere 895c7cf2933SEtienne Carriere void stpmic1_dump_regulators(void) 896c7cf2933SEtienne Carriere { 897c7cf2933SEtienne Carriere size_t i = 0; 898c7cf2933SEtienne Carriere char __maybe_unused const *name = NULL; 899c7cf2933SEtienne Carriere 900c7cf2933SEtienne Carriere for (i = 0; i < ARRAY_SIZE(regulators_table); i++) { 901c7cf2933SEtienne Carriere if (!regulators_table[i].control_reg) 902c7cf2933SEtienne Carriere continue; 903c7cf2933SEtienne Carriere 904c7cf2933SEtienne Carriere name = regulators_table[i].dt_node_name; 905c7cf2933SEtienne Carriere DMSG("PMIC regul %s: %sable, %dmV", 906c7cf2933SEtienne Carriere name, stpmic1_is_regulator_enabled(name) ? "en" : "dis", 907c7cf2933SEtienne Carriere stpmic1_regulator_voltage_get(name)); 908c7cf2933SEtienne Carriere } 909c7cf2933SEtienne Carriere } 910c7cf2933SEtienne Carriere 911c7cf2933SEtienne Carriere int stpmic1_get_version(unsigned long *version) 912c7cf2933SEtienne Carriere { 913c7cf2933SEtienne Carriere uint8_t read_val = 0; 914c7cf2933SEtienne Carriere 915c7cf2933SEtienne Carriere if (stpmic1_register_read(VERSION_STATUS_REG, &read_val)) 916c7cf2933SEtienne Carriere return -1; 917c7cf2933SEtienne Carriere 918c7cf2933SEtienne Carriere *version = read_val; 919c7cf2933SEtienne Carriere return 0; 920c7cf2933SEtienne Carriere } 921