1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2018-2025, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/rtc.h> 9 #include <drivers/stm32_rif.h> 10 #include <drivers/stm32_rtc.h> 11 #include <io.h> 12 #include <kernel/dt.h> 13 #include <kernel/dt_driver.h> 14 #include <kernel/panic.h> 15 #include <kernel/spinlock.h> 16 #include <libfdt.h> 17 #include <mm/core_memprot.h> 18 19 /* 20 * Registers 21 */ 22 #define RTC_TR U(0x00) 23 #define RTC_DR U(0x04) 24 #define RTC_SSR U(0x08) 25 #define RTC_ICSR U(0x0C) 26 #define RTC_PRER U(0x10) 27 #define RTC_WUTR U(0x14) 28 #define RTC_CR U(0x18) 29 #define RTC_PRIVCFGR U(0x1C) 30 /* RTC_SMCR is linked to RTC3v1_2 */ 31 #define RTC_SMCR U(0x20) 32 /* RTC_SECCFGR is linked to RTC3v3_2 and above */ 33 #define RTC_SECCFGR U(0x20) 34 #define RTC_WPR U(0x24) 35 #define RTC_CALR U(0x28) 36 #define RTC_SHIFTR U(0x2C) 37 #define RTC_TSTR U(0x30) 38 #define RTC_TSDR U(0x34) 39 #define RTC_TSSSR U(0x38) 40 #define RTC_ALRMAR U(0x40) 41 #define RTC_ALRMASSR U(0x44) 42 #define RTC_ALRMBR U(0x48) 43 #define RTC_ALRMBSSR U(0x4C) 44 #define RTC_SR U(0x50) 45 #define RTC_SCR U(0x5C) 46 #define RTC_OR U(0x60) 47 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x)) 48 49 #define RTC_TR_SU_MASK GENMASK_32(3, 0) 50 #define RTC_TR_ST_MASK GENMASK_32(6, 4) 51 #define RTC_TR_ST_SHIFT U(4) 52 #define RTC_TR_MNU_MASK GENMASK_32(11, 8) 53 #define RTC_TR_MNU_SHIFT U(8) 54 #define RTC_TR_MNT_MASK GENMASK_32(14, 12) 55 #define RTC_TR_MNT_SHIFT U(12) 56 #define RTC_TR_HU_MASK GENMASK_32(19, 16) 57 #define RTC_TR_HU_SHIFT U(16) 58 #define RTC_TR_HT_MASK GENMASK_32(21, 20) 59 #define RTC_TR_HT_SHIFT U(20) 60 #define RTC_TR_PM BIT(22) 61 62 #define RTC_DR_DU_MASK GENMASK_32(3, 0) 63 #define RTC_DR_DT_MASK GENMASK_32(5, 4) 64 #define RTC_DR_DT_SHIFT U(4) 65 #define RTC_DR_MU_MASK GENMASK_32(11, 8) 66 #define RTC_DR_MU_SHIFT U(8) 67 #define RTC_DR_MT_MASK BIT(12) 68 #define RTC_DR_MT_SHIFT U(12) 69 #define RTC_DR_WDU_MASK GENMASK_32(15, 13) 70 #define RTC_DR_WDU_SHIFT U(13) 71 #define RTC_DR_YU_MASK GENMASK_32(19, 16) 72 #define RTC_DR_YU_SHIFT U(16) 73 #define RTC_DR_YT_MASK GENMASK_32(23, 20) 74 #define RTC_DR_YT_SHIFT U(20) 75 76 #define RTC_SSR_SS_MASK GENMASK_32(15, 0) 77 78 #define RTC_ICSR_RSF BIT(5) 79 #define RTC_ICSR_INITF BIT(6) 80 #define RTC_ICSR_INIT BIT(7) 81 82 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0) 83 84 #define RTC_CR_BYPSHAD BIT(5) 85 #define RTC_CR_BYPSHAD_SHIFT U(5) 86 #define RTC_CR_TAMPTS BIT(25) 87 88 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0) 89 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 90 #define RTC_PRIVCFGR_SHIFT U(9) 91 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 92 #define RTC_PRIVCFGR_FULL_PRIV BIT(15) 93 94 #define RTC_SMCR_TS_DPROT BIT(3) 95 96 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0) 97 #define RTC_SECCFGR_TS_SEC BIT(3) 98 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 99 #define RTC_SECCFGR_SHIFT U(9) 100 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 101 #define RTC_SECCFGR_FULL_SEC BIT(15) 102 103 #define RTC_WPR_KEY1 U(0xCA) 104 #define RTC_WPR_KEY2 U(0x53) 105 #define RTC_WPR_KEY_LOCK U(0xFF) 106 107 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8) 108 #define RTC_TSDR_MU_SHIFT U(8) 109 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4) 110 #define RTC_TSDR_DT_SHIFT U(4) 111 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0) 112 #define RTC_TSDR_DU_SHIFT U(0) 113 114 #define RTC_SR_TSF BIT(3) 115 #define RTC_SR_TSOVF BIT(4) 116 117 #define RTC_SCR_CTSF BIT(3) 118 #define RTC_SCR_CTSOVF BIT(4) 119 120 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 121 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4) 122 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 123 RTC_CIDCFGR_SCID_MASK) 124 125 /* 126 * RIF miscellaneous 127 */ 128 #define RTC_NB_RIF_RESOURCES U(6) 129 130 #define RTC_RIF_FULL_PRIVILEGED U(0x3F) 131 #define RTC_RIF_FULL_SECURED U(0x3F) 132 133 #define RTC_NB_MAX_CID_SUPPORTED U(7) 134 135 /* 136 * Driver miscellaneous 137 */ 138 #define RTC_RES_TIMESTAMP U(3) 139 #define RTC_RES_CALIBRATION U(4) 140 #define RTC_RES_INITIALIZATION U(5) 141 142 #define RTC_FLAGS_READ_TWICE BIT(0) 143 144 #define TIMEOUT_US_RTC_SHADOW U(10000) 145 #define TIMEOUT_US_RTC_GENERIC U(100000) 146 147 #define YEAR_REF ULL(2000) 148 #define YEAR_MAX (YEAR_REF + ULL(99)) 149 150 struct rtc_compat { 151 bool has_seccfgr; 152 bool has_rif_support; 153 }; 154 155 /* 156 * struct rtc_device - RTC device data 157 * @base: RTC IOMEM base address 158 * @compat: RTC compatible data 159 * @pclk: RTC bus clock 160 * @rtc_ck: RTC kernel clock 161 * @conf_data: RTC RIF configuration data, when supported 162 * @nb_res: Number of protectible RTC resources 163 * @ts_lock: Lock used for time stamping events handling 164 * @flags: RTC driver flags 165 * @is_secured: True if the RTC is fully secured 166 */ 167 struct rtc_device { 168 struct io_pa_va base; 169 const struct rtc_compat *compat; 170 struct clk *pclk; 171 struct clk *rtc_ck; 172 struct rif_conf_data *conf_data; 173 unsigned int nb_res; 174 unsigned int ts_lock; 175 uint8_t flags; 176 bool is_secured; 177 }; 178 179 /* Expect a single RTC instance */ 180 static struct rtc_device rtc_dev; 181 182 static vaddr_t get_base(void) 183 { 184 assert(rtc_dev.base.pa); 185 186 return io_pa_or_va(&rtc_dev.base, 1); 187 } 188 189 static void stm32_rtc_write_unprotect(void) 190 { 191 vaddr_t rtc_base = get_base(); 192 193 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1); 194 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2); 195 } 196 197 static void stm32_rtc_write_protect(void) 198 { 199 vaddr_t rtc_base = get_base(); 200 201 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK); 202 } 203 204 static bool stm32_rtc_get_bypshad(void) 205 { 206 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD; 207 } 208 209 /* Get the subsecond value. */ 210 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr) 211 { 212 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) & 213 RTC_PRER_PREDIV_S_MASK; 214 215 return prediv_s - ssr; 216 } 217 218 /* 219 * Get the subsecond scale. 220 * 221 * Number of subseconds in a second is linked to RTC PREDIV_S value. 222 * The higher PREDIV_S is, the more subsecond is precise. 223 */ 224 static uint32_t stm32_rtc_get_subsecond_scale(void) 225 { 226 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1; 227 } 228 229 static bool cid1_has_access(unsigned int resource) 230 { 231 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); 232 233 return !(cidcfgr & _CIDCFGR_CFEN) || 234 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; 235 } 236 237 static TEE_Result check_rif_config(void) 238 { 239 if (!cid1_has_access(RTC_RES_TIMESTAMP) || 240 !cid1_has_access(RTC_RES_CALIBRATION) || 241 !cid1_has_access(RTC_RES_INITIALIZATION)) 242 return TEE_ERROR_ACCESS_DENIED; 243 244 return TEE_SUCCESS; 245 } 246 247 static void apply_rif_config(bool is_tdcid) 248 { 249 vaddr_t base = get_base(); 250 unsigned int shifted_values = 0; 251 uint32_t seccfgr = 0; 252 uint32_t privcfgr = 0; 253 uint32_t access_mask_reg = 0; 254 unsigned int i = 0; 255 256 if (!rtc_dev.conf_data) 257 return; 258 259 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */ 260 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 261 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) { 262 if (i <= RTC_RES_TIMESTAMP) 263 access_mask_reg |= BIT(i); 264 else 265 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT; 266 } 267 } 268 269 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 270 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 271 continue; 272 273 /* 274 * When TDCID, OP-TEE should be the one to set the CID filtering 275 * configuration. Clearing previous configuration prevents 276 * undesired events during the only legitimate configuration. 277 */ 278 if (is_tdcid) 279 io_clrbits32(base + RTC_CIDCFGR(i), 280 RTC_CIDCFGR_CONF_MASK); 281 } 282 283 /* Security RIF configuration */ 284 seccfgr = rtc_dev.conf_data->sec_conf[0]; 285 286 /* Check if all resources must be secured */ 287 if (seccfgr == RTC_RIF_FULL_SECURED) { 288 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC); 289 rtc_dev.is_secured = true; 290 291 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC)) 292 panic("Bad RTC seccfgr configuration"); 293 } 294 295 /* Shift some values to align with the register */ 296 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, 297 RTC_SECCFGR_SHIFT); 298 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; 299 300 io_clrsetbits32(base + RTC_SECCFGR, 301 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); 302 303 /* Privilege RIF configuration */ 304 privcfgr = rtc_dev.conf_data->priv_conf[0]; 305 306 /* Check if all resources must be privileged */ 307 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) { 308 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV); 309 310 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV)) 311 panic("Bad RTC privcfgr configuration"); 312 } 313 314 /* Shift some values to align with the register */ 315 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT, 316 RTC_PRIVCFGR_SHIFT); 317 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values; 318 319 io_clrsetbits32(base + RTC_PRIVCFGR, 320 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr); 321 322 if (!is_tdcid) 323 return; 324 325 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 326 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 327 continue; 328 /* 329 * When at least one resource has CID filtering enabled, 330 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are 331 * cleared. 332 */ 333 io_clrsetbits32(base + RTC_CIDCFGR(i), 334 RTC_CIDCFGR_CONF_MASK, 335 rtc_dev.conf_data->cid_confs[i]); 336 } 337 } 338 339 static TEE_Result parse_dt(const void *fdt, int node) 340 { 341 TEE_Result res = TEE_ERROR_GENERIC; 342 const fdt32_t *cuint = NULL; 343 size_t reg_size = 0; 344 unsigned int i = 0; 345 int lenp = 0; 346 347 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size)) 348 panic(); 349 350 io_pa_or_va(&rtc_dev.base, reg_size); 351 assert(rtc_dev.base.va); 352 353 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk); 354 if (res) 355 return res; 356 357 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck); 358 if (res) 359 return res; 360 361 if (!rtc_dev.compat->has_rif_support) 362 return TEE_SUCCESS; 363 364 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 365 if (!cuint) { 366 DMSG("No RIF configuration available"); 367 return TEE_SUCCESS; 368 } 369 370 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data)); 371 if (!rtc_dev.conf_data) 372 panic(); 373 374 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 375 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES); 376 377 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES, 378 sizeof(uint32_t)); 379 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 380 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 381 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t)); 382 if (!rtc_dev.conf_data->cid_confs || !rtc_dev.conf_data->sec_conf || 383 !rtc_dev.conf_data->priv_conf || !rtc_dev.conf_data->access_mask) 384 panic("Not enough memory capacity for RTC RIF config"); 385 386 for (i = 0; i < rtc_dev.nb_res; i++) 387 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), rtc_dev.conf_data, 388 RTC_NB_RIF_RESOURCES); 389 390 return TEE_SUCCESS; 391 } 392 393 static TEE_Result stm32_rtc_enter_init_mode(void) 394 { 395 vaddr_t base = get_base(); 396 uint32_t icsr = io_read32(base + RTC_ICSR); 397 uint32_t value = 0; 398 399 if (!(icsr & RTC_ICSR_INITF)) { 400 icsr |= RTC_ICSR_INIT; 401 io_write32(base + RTC_ICSR, icsr); 402 403 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 404 value & RTC_ICSR_INITF, 405 10, TIMEOUT_US_RTC_GENERIC)) 406 return TEE_ERROR_BUSY; 407 } 408 409 return TEE_SUCCESS; 410 } 411 412 static void stm32_rtc_exit_init_mode(void) 413 { 414 io_clrbits32(get_base() + RTC_ICSR, RTC_ICSR_INIT); 415 dsb(); 416 } 417 418 static TEE_Result stm32_rtc_wait_sync(void) 419 { 420 vaddr_t base = get_base(); 421 uint32_t value = 0; 422 423 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 424 425 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 426 value & RTC_ICSR_RSF, 10, 427 TIMEOUT_US_RTC_GENERIC)) 428 return TEE_ERROR_BUSY; 429 430 return TEE_SUCCESS; 431 } 432 433 static void stm32_rtc_to_tm(uint32_t ssr, uint32_t tr, uint32_t dr, 434 struct optee_rtc_time *tm) 435 { 436 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 + 437 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); 438 439 if (tr & RTC_TR_PM) 440 tm->tm_hour += 12; 441 442 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) / 443 stm32_rtc_get_subsecond_scale(); 444 445 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 + 446 (tr & RTC_TR_SU_MASK); 447 448 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 + 449 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); 450 451 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7; 452 453 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 + 454 (dr & RTC_DR_DU_MASK); 455 456 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 + 457 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1; 458 459 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 + 460 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF; 461 } 462 463 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused, 464 struct optee_rtc_time *tm) 465 { 466 vaddr_t base = get_base(); 467 uint32_t ssr = 0; 468 uint32_t dr = 0; 469 uint32_t tr = 0; 470 471 if (!stm32_rtc_get_bypshad()) { 472 uint32_t icsr = 0; 473 474 /* Wait calendar registers are ready */ 475 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 476 477 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr, 478 icsr & RTC_ICSR_RSF, 0, 479 TIMEOUT_US_RTC_SHADOW)) 480 panic(); 481 } 482 483 /* 484 * In our RTC we start : 485 * - year at 0 486 * - month at 1 487 * - day at 1 488 * - weekday at Monday = 1 489 * Change month value so it becomes 0=January, 1 = February, ... 490 * Change week day value so it becomes 0=Sunday, 1 = Monday, ... 491 */ 492 493 ssr = io_read32(base + RTC_SSR); 494 tr = io_read32(base + RTC_TR); 495 dr = io_read32(base + RTC_DR); 496 497 stm32_rtc_to_tm(ssr, tr, dr, tm); 498 499 return TEE_SUCCESS; 500 } 501 502 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm) 503 { 504 TEE_Result res = TEE_ERROR_GENERIC; 505 vaddr_t rtc_base = get_base(); 506 uint32_t tr = 0; 507 uint32_t dr = 0; 508 509 /* 510 * In our RTC we start : 511 * - year at 0 512 * - month at 1 513 * - day at 1 514 * - weekday at Monday = 1 515 * Change month value so it becomes 1=January, 2 = February, ... 516 * Change week day value so it becomes 7=Sunday, 1 = Monday, ... 517 */ 518 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) | 519 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) | 520 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) | 521 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) | 522 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) | 523 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK); 524 525 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) | 526 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) | 527 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) & 528 RTC_DR_MU_MASK) | 529 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) & 530 RTC_DR_MT_MASK) | 531 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) & 532 RTC_DR_WDU_MASK) | 533 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10, 534 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) | 535 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10, 536 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK); 537 538 stm32_rtc_write_unprotect(); 539 540 res = stm32_rtc_enter_init_mode(); 541 if (res) 542 goto end; 543 544 io_write32(rtc_base + RTC_TR, tr); 545 io_write32(rtc_base + RTC_DR, dr); 546 547 stm32_rtc_exit_init_mode(); 548 549 res = stm32_rtc_wait_sync(); 550 end: 551 stm32_rtc_write_protect(); 552 553 return res; 554 } 555 556 TEE_Result stm32_rtc_get_timestamp(struct optee_rtc_time *tm) 557 { 558 vaddr_t base = get_base(); 559 uint32_t exceptions = 0; 560 uint32_t value = 0; 561 uint32_t ssr = 0; 562 uint32_t dr = 0; 563 uint32_t tr = 0; 564 565 exceptions = cpu_spin_lock_xsave(&rtc_dev.ts_lock); 566 567 if (IO_READ32_POLL_TIMEOUT(base + RTC_SR, value, 568 value & RTC_SR_TSF, 569 10, TIMEOUT_US_RTC_GENERIC)) { 570 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 571 return TEE_ERROR_NO_DATA; 572 } 573 574 ssr = io_read32(base + RTC_TSSSR); 575 tr = io_read32(base + RTC_TSTR); 576 dr = io_read32(base + RTC_TSDR); 577 578 io_setbits32(base + RTC_SCR, RTC_SCR_CTSF); 579 580 /* Tamper event overflow detection */ 581 if (io_read32(base + RTC_SR) & RTC_SR_TSOVF) { 582 io_setbits32(base + RTC_SCR, RTC_SCR_CTSOVF); 583 DMSG("A timestamp event occurred while handling current event"); 584 } 585 586 cpu_spin_unlock_xrestore(&rtc_dev.ts_lock, exceptions); 587 588 stm32_rtc_to_tm(ssr, tr, dr, tm); 589 590 /* No year timestamp available */ 591 tm->tm_year = 0; 592 593 return TEE_SUCCESS; 594 } 595 596 TEE_Result stm32_rtc_set_tamper_timestamp(void) 597 { 598 vaddr_t base = get_base(); 599 600 stm32_rtc_write_unprotect(); 601 602 /* Secure Timestamp bit */ 603 if (!rtc_dev.compat->has_seccfgr) { 604 /* Inverted logic */ 605 io_clrbits32(base + RTC_SMCR, RTC_SMCR_TS_DPROT); 606 } else { 607 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_TS_SEC); 608 } 609 610 /* Enable tamper timestamper */ 611 io_setbits32(base + RTC_CR, RTC_CR_TAMPTS); 612 613 stm32_rtc_write_protect(); 614 615 return TEE_SUCCESS; 616 } 617 618 TEE_Result stm32_rtc_is_timestamp_enabled(bool *ret) 619 { 620 *ret = io_read32(get_base() + RTC_CR) & RTC_CR_TAMPTS; 621 622 return TEE_SUCCESS; 623 } 624 625 TEE_Result stm32_rtc_driver_is_initialized(void) 626 { 627 if (rtc_dev.pclk) 628 return TEE_SUCCESS; 629 630 return TEE_ERROR_DEFER_DRIVER_INIT; 631 } 632 633 static const struct rtc_ops stm32_rtc_ops = { 634 .get_time = stm32_rtc_get_time, 635 .set_time = stm32_rtc_set_time, 636 }; 637 638 static struct rtc stm32_rtc = { 639 .ops = &stm32_rtc_ops, 640 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0), 641 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999), 642 }; 643 644 static TEE_Result stm32_rtc_probe(const void *fdt, int node, 645 const void *compat_data) 646 { 647 TEE_Result res = TEE_ERROR_GENERIC; 648 bool is_tdcid = false; 649 650 rtc_dev.compat = compat_data; 651 652 if (rtc_dev.compat->has_rif_support) { 653 res = stm32_rifsc_check_tdcid(&is_tdcid); 654 if (res) 655 return res; 656 } 657 658 res = parse_dt(fdt, node); 659 if (res) { 660 memset(&rtc_dev, 0, sizeof(rtc_dev)); 661 return res; 662 } 663 664 /* Unbalanced clock enable to ensure RTC core clock is always on */ 665 res = clk_enable(rtc_dev.rtc_ck); 666 if (res) 667 panic("Couldn't enable RTC clock"); 668 669 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7)) 670 rtc_dev.flags |= RTC_FLAGS_READ_TWICE; 671 672 if (rtc_dev.compat->has_rif_support) { 673 res = clk_enable(rtc_dev.pclk); 674 if (res) 675 panic("Could not enable RTC bus clock"); 676 677 apply_rif_config(is_tdcid); 678 679 /* 680 * Verify if applied RIF config will not disable 681 * other functionalities of this driver. 682 */ 683 res = check_rif_config(); 684 if (res) 685 panic("Incompatible RTC RIF configuration"); 686 687 clk_disable(rtc_dev.pclk); 688 } 689 690 rtc_register(&stm32_rtc); 691 692 return res; 693 } 694 695 static const struct rtc_compat mp25_compat = { 696 .has_seccfgr = true, 697 .has_rif_support = true, 698 }; 699 700 static const struct rtc_compat mp15_compat = { 701 .has_seccfgr = false, 702 .has_rif_support = false, 703 }; 704 705 static const struct rtc_compat mp13_compat = { 706 .has_seccfgr = true, 707 .has_rif_support = false, 708 }; 709 710 static const struct dt_device_match stm32_rtc_match_table[] = { 711 { 712 .compatible = "st,stm32mp25-rtc", 713 .compat_data = &mp25_compat, 714 }, 715 { 716 .compatible = "st,stm32mp1-rtc", 717 .compat_data = &mp15_compat, 718 }, 719 { 720 .compatible = "st,stm32mp13-rtc", 721 .compat_data = &mp13_compat, 722 }, 723 { } 724 }; 725 726 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = { 727 .name = "stm32-rtc", 728 .match_table = stm32_rtc_match_table, 729 .probe = stm32_rtc_probe, 730 }; 731