1 // SPDX-License-Identifier: BSD-2-Clause 2 /* 3 * Copyright (C) 2018-2024, STMicroelectronics 4 */ 5 #include <assert.h> 6 #include <drivers/clk.h> 7 #include <drivers/clk_dt.h> 8 #include <drivers/rtc.h> 9 #include <drivers/stm32_rif.h> 10 #include <io.h> 11 #include <kernel/dt.h> 12 #include <kernel/dt_driver.h> 13 #include <kernel/panic.h> 14 #include <libfdt.h> 15 #include <mm/core_memprot.h> 16 17 /* 18 * Registers 19 */ 20 #define RTC_TR U(0x00) 21 #define RTC_DR U(0x04) 22 #define RTC_SSR U(0x08) 23 #define RTC_ICSR U(0x0C) 24 #define RTC_PRER U(0x10) 25 #define RTC_WUTR U(0x14) 26 #define RTC_CR U(0x18) 27 #define RTC_PRIVCFGR U(0x1C) 28 /* RTC_SMCR is linked to RTC3v1_2 */ 29 #define RTC_SMCR U(0x20) 30 /* RTC_SECCFGR is linked to RTC3v3_2 and above */ 31 #define RTC_SECCFGR U(0x20) 32 #define RTC_WPR U(0x24) 33 #define RTC_CALR U(0x28) 34 #define RTC_SHIFTR U(0x2C) 35 #define RTC_TSTR U(0x30) 36 #define RTC_TSDR U(0x34) 37 #define RTC_TSSSR U(0x38) 38 #define RTC_ALRMAR U(0x40) 39 #define RTC_ALRMASSR U(0x44) 40 #define RTC_ALRMBR U(0x48) 41 #define RTC_ALRMBSSR U(0x4C) 42 #define RTC_SR U(0x50) 43 #define RTC_SCR U(0x5C) 44 #define RTC_OR U(0x60) 45 #define RTC_CIDCFGR(x) (U(0x80) + U(0x4) * (x)) 46 47 #define RTC_TR_SU_MASK GENMASK_32(3, 0) 48 #define RTC_TR_ST_MASK GENMASK_32(6, 4) 49 #define RTC_TR_ST_SHIFT U(4) 50 #define RTC_TR_MNU_MASK GENMASK_32(11, 8) 51 #define RTC_TR_MNU_SHIFT U(8) 52 #define RTC_TR_MNT_MASK GENMASK_32(14, 12) 53 #define RTC_TR_MNT_SHIFT U(12) 54 #define RTC_TR_HU_MASK GENMASK_32(19, 16) 55 #define RTC_TR_HU_SHIFT U(16) 56 #define RTC_TR_HT_MASK GENMASK_32(21, 20) 57 #define RTC_TR_HT_SHIFT U(20) 58 #define RTC_TR_PM BIT(22) 59 60 #define RTC_DR_DU_MASK GENMASK_32(3, 0) 61 #define RTC_DR_DT_MASK GENMASK_32(5, 4) 62 #define RTC_DR_DT_SHIFT U(4) 63 #define RTC_DR_MU_MASK GENMASK_32(11, 8) 64 #define RTC_DR_MU_SHIFT U(8) 65 #define RTC_DR_MT_MASK BIT(12) 66 #define RTC_DR_MT_SHIFT U(12) 67 #define RTC_DR_WDU_MASK GENMASK_32(15, 13) 68 #define RTC_DR_WDU_SHIFT U(13) 69 #define RTC_DR_YU_MASK GENMASK_32(19, 16) 70 #define RTC_DR_YU_SHIFT U(16) 71 #define RTC_DR_YT_MASK GENMASK_32(23, 20) 72 #define RTC_DR_YT_SHIFT U(20) 73 74 #define RTC_SSR_SS_MASK GENMASK_32(15, 0) 75 76 #define RTC_ICSR_RSF BIT(5) 77 #define RTC_ICSR_INITF BIT(6) 78 #define RTC_ICSR_INIT BIT(7) 79 80 #define RTC_PRER_PREDIV_S_MASK GENMASK_32(14, 0) 81 82 #define RTC_CR_BYPSHAD BIT(5) 83 #define RTC_CR_BYPSHAD_SHIFT U(5) 84 #define RTC_CR_TAMPTS BIT(25) 85 86 #define RTC_PRIVCFGR_VALUES GENMASK_32(3, 0) 87 #define RTC_PRIVCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 88 #define RTC_PRIVCFGR_SHIFT U(9) 89 #define RTC_PRIVCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 90 #define RTC_PRIVCFGR_FULL_PRIV BIT(15) 91 92 #define RTC_SMCR_TS_DPROT BIT(3) 93 94 #define RTC_SECCFGR_VALUES GENMASK_32(3, 0) 95 #define RTC_SECCFGR_TS_SEC BIT(3) 96 #define RTC_SECCFGR_VALUES_TO_SHIFT GENMASK_32(5, 4) 97 #define RTC_SECCFGR_SHIFT U(9) 98 #define RTC_SECCFGR_MASK (GENMASK_32(14, 13) | GENMASK_32(3, 0)) 99 #define RTC_SECCFGR_FULL_SEC BIT(15) 100 101 #define RTC_WPR_KEY1 U(0xCA) 102 #define RTC_WPR_KEY2 U(0x53) 103 #define RTC_WPR_KEY_LOCK U(0xFF) 104 105 #define RTC_TSDR_MU_MASK GENMASK_32(11, 8) 106 #define RTC_TSDR_MU_SHIFT U(8) 107 #define RTC_TSDR_DT_MASK GENMASK_32(5, 4) 108 #define RTC_TSDR_DT_SHIFT U(4) 109 #define RTC_TSDR_DU_MASK GENMASK_32(3, 0) 110 #define RTC_TSDR_DU_SHIFT U(0) 111 112 #define RTC_SR_TSF BIT(3) 113 #define RTC_SR_TSOVF BIT(4) 114 115 #define RTC_SCR_CTSF BIT(3) 116 #define RTC_SCR_CTSOVF BIT(4) 117 118 #define RTC_CIDCFGR_SCID_MASK GENMASK_32(6, 4) 119 #define RTC_CIDCFGR_SCID_MASK_SHIFT U(4) 120 #define RTC_CIDCFGR_CONF_MASK (_CIDCFGR_CFEN | \ 121 RTC_CIDCFGR_SCID_MASK) 122 123 /* 124 * RIF miscellaneous 125 */ 126 #define RTC_NB_RIF_RESOURCES U(6) 127 128 #define RTC_RIF_FULL_PRIVILEGED U(0x3F) 129 #define RTC_RIF_FULL_SECURED U(0x3F) 130 131 #define RTC_NB_MAX_CID_SUPPORTED U(7) 132 133 /* 134 * Driver miscellaneous 135 */ 136 #define RTC_RES_TIMESTAMP U(3) 137 #define RTC_RES_CALIBRATION U(4) 138 #define RTC_RES_INITIALIZATION U(5) 139 140 #define RTC_FLAGS_READ_TWICE BIT(0) 141 142 #define TIMEOUT_US_RTC_SHADOW U(10000) 143 #define TIMEOUT_US_RTC_GENERIC U(100000) 144 145 #define YEAR_REF ULL(2000) 146 #define YEAR_MAX (YEAR_REF + ULL(99)) 147 148 struct rtc_compat { 149 bool has_seccfgr; 150 bool has_rif_support; 151 }; 152 153 /* 154 * struct rtc_device - RTC device data 155 * @base: RTC IOMEM base address 156 * @compat: RTC compatible data 157 * @pclk: RTC bus clock 158 * @rtc_ck: RTC kernel clock 159 * @conf_data: RTC RIF configuration data, when supported 160 * @nb_res: Number of protectible RTC resources 161 * @flags: RTC driver flags 162 * @is_secured: True if the RTC is fully secured 163 */ 164 struct rtc_device { 165 struct io_pa_va base; 166 const struct rtc_compat *compat; 167 struct clk *pclk; 168 struct clk *rtc_ck; 169 struct rif_conf_data *conf_data; 170 unsigned int nb_res; 171 uint8_t flags; 172 bool is_secured; 173 }; 174 175 /* Expect a single RTC instance */ 176 static struct rtc_device rtc_dev; 177 178 static vaddr_t get_base(void) 179 { 180 assert(rtc_dev.base.pa); 181 182 return io_pa_or_va(&rtc_dev.base, 1); 183 } 184 185 static void stm32_rtc_write_unprotect(void) 186 { 187 vaddr_t rtc_base = get_base(); 188 189 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY1); 190 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY2); 191 } 192 193 static void stm32_rtc_write_protect(void) 194 { 195 vaddr_t rtc_base = get_base(); 196 197 io_write32(rtc_base + RTC_WPR, RTC_WPR_KEY_LOCK); 198 } 199 200 static bool stm32_rtc_get_bypshad(void) 201 { 202 return io_read32(get_base() + RTC_CR) & RTC_CR_BYPSHAD; 203 } 204 205 /* Get the subsecond value. */ 206 static uint32_t stm32_rtc_get_subsecond(uint32_t ssr) 207 { 208 uint32_t prediv_s = io_read32(get_base() + RTC_PRER) & 209 RTC_PRER_PREDIV_S_MASK; 210 211 return prediv_s - ssr; 212 } 213 214 /* 215 * Get the subsecond scale. 216 * 217 * Number of subseconds in a second is linked to RTC PREDIV_S value. 218 * The higher PREDIV_S is, the more subsecond is precise. 219 */ 220 static uint32_t stm32_rtc_get_subsecond_scale(void) 221 { 222 return (io_read32(get_base() + RTC_PRER) & RTC_PRER_PREDIV_S_MASK) + 1; 223 } 224 225 static bool cid1_has_access(unsigned int resource) 226 { 227 uint32_t cidcfgr = io_read32(get_base() + RTC_CIDCFGR(resource)); 228 229 return !(cidcfgr & _CIDCFGR_CFEN) || 230 get_field_u32(cidcfgr, RTC_CIDCFGR_SCID_MASK) == RIF_CID1; 231 } 232 233 static TEE_Result check_rif_config(void) 234 { 235 if (!cid1_has_access(RTC_RES_TIMESTAMP) || 236 !cid1_has_access(RTC_RES_CALIBRATION) || 237 !cid1_has_access(RTC_RES_INITIALIZATION)) 238 return TEE_ERROR_ACCESS_DENIED; 239 240 return TEE_SUCCESS; 241 } 242 243 static void apply_rif_config(bool is_tdcid) 244 { 245 vaddr_t base = get_base(); 246 unsigned int shifted_values = 0; 247 uint32_t seccfgr = 0; 248 uint32_t privcfgr = 0; 249 uint32_t access_mask_reg = 0; 250 unsigned int i = 0; 251 252 if (!rtc_dev.conf_data) 253 return; 254 255 /* Build access mask for RTC_SECCFGR and RTC_PRIVCFGR */ 256 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 257 if (rtc_dev.conf_data->access_mask[0] & BIT(i)) { 258 if (i <= RTC_RES_TIMESTAMP) 259 access_mask_reg |= BIT(i); 260 else 261 access_mask_reg |= BIT(i) << RTC_SECCFGR_SHIFT; 262 } 263 } 264 265 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 266 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 267 continue; 268 269 /* 270 * When TDCID, OP-TEE should be the one to set the CID filtering 271 * configuration. Clearing previous configuration prevents 272 * undesired events during the only legitimate configuration. 273 */ 274 if (is_tdcid) 275 io_clrbits32(base + RTC_CIDCFGR(i), 276 RTC_CIDCFGR_CONF_MASK); 277 } 278 279 /* Security RIF configuration */ 280 seccfgr = rtc_dev.conf_data->sec_conf[0]; 281 282 /* Check if all resources must be secured */ 283 if (seccfgr == RTC_RIF_FULL_SECURED) { 284 io_setbits32(base + RTC_SECCFGR, RTC_SECCFGR_FULL_SEC); 285 rtc_dev.is_secured = true; 286 287 if (!(io_read32(base + RTC_SECCFGR) & RTC_SECCFGR_FULL_SEC)) 288 panic("Bad RTC seccfgr configuration"); 289 } 290 291 /* Shift some values to align with the register */ 292 shifted_values = SHIFT_U32(seccfgr & RTC_SECCFGR_VALUES_TO_SHIFT, 293 RTC_SECCFGR_SHIFT); 294 seccfgr = (seccfgr & RTC_SECCFGR_VALUES) + shifted_values; 295 296 io_clrsetbits32(base + RTC_SECCFGR, 297 RTC_SECCFGR_MASK & access_mask_reg, seccfgr); 298 299 /* Privilege RIF configuration */ 300 privcfgr = rtc_dev.conf_data->priv_conf[0]; 301 302 /* Check if all resources must be privileged */ 303 if (privcfgr == RTC_RIF_FULL_PRIVILEGED) { 304 io_setbits32(base + RTC_PRIVCFGR, RTC_PRIVCFGR_FULL_PRIV); 305 306 if (!(io_read32(base + RTC_PRIVCFGR) & RTC_PRIVCFGR_FULL_PRIV)) 307 panic("Bad RTC privcfgr configuration"); 308 } 309 310 /* Shift some values to align with the register */ 311 shifted_values = SHIFT_U32(privcfgr & RTC_PRIVCFGR_VALUES_TO_SHIFT, 312 RTC_PRIVCFGR_SHIFT); 313 privcfgr = (privcfgr & RTC_PRIVCFGR_VALUES) + shifted_values; 314 315 io_clrsetbits32(base + RTC_PRIVCFGR, 316 RTC_PRIVCFGR_MASK & access_mask_reg, privcfgr); 317 318 if (!is_tdcid) 319 return; 320 321 for (i = 0; i < RTC_NB_RIF_RESOURCES; i++) { 322 if (!(BIT(i) & rtc_dev.conf_data->access_mask[0])) 323 continue; 324 /* 325 * When at least one resource has CID filtering enabled, 326 * the RTC_PRIVCFGR_FULL_PRIV and RTC_SECCFGR_FULL_SEC bits are 327 * cleared. 328 */ 329 io_clrsetbits32(base + RTC_CIDCFGR(i), 330 RTC_CIDCFGR_CONF_MASK, 331 rtc_dev.conf_data->cid_confs[i]); 332 } 333 } 334 335 static TEE_Result parse_dt(const void *fdt, int node) 336 { 337 TEE_Result res = TEE_ERROR_GENERIC; 338 const fdt32_t *cuint = NULL; 339 size_t reg_size = 0; 340 unsigned int i = 0; 341 int lenp = 0; 342 343 if (fdt_reg_info(fdt, node, &rtc_dev.base.pa, ®_size)) 344 panic(); 345 346 io_pa_or_va(&rtc_dev.base, reg_size); 347 assert(rtc_dev.base.va); 348 349 res = clk_dt_get_by_name(fdt, node, "pclk", &rtc_dev.pclk); 350 if (res) 351 return res; 352 353 res = clk_dt_get_by_name(fdt, node, "rtc_ck", &rtc_dev.rtc_ck); 354 if (res) 355 return res; 356 357 if (!rtc_dev.compat->has_rif_support) 358 return TEE_SUCCESS; 359 360 cuint = fdt_getprop(fdt, node, "st,protreg", &lenp); 361 if (!cuint) { 362 DMSG("No RIF configuration available"); 363 return TEE_SUCCESS; 364 } 365 366 rtc_dev.conf_data = calloc(1, sizeof(*rtc_dev.conf_data)); 367 if (!rtc_dev.conf_data) 368 panic(); 369 370 rtc_dev.nb_res = (unsigned int)(lenp / sizeof(uint32_t)); 371 assert(rtc_dev.nb_res <= RTC_NB_RIF_RESOURCES); 372 373 rtc_dev.conf_data->cid_confs = calloc(RTC_NB_RIF_RESOURCES, 374 sizeof(uint32_t)); 375 rtc_dev.conf_data->sec_conf = calloc(1, sizeof(uint32_t)); 376 rtc_dev.conf_data->priv_conf = calloc(1, sizeof(uint32_t)); 377 rtc_dev.conf_data->access_mask = calloc(1, sizeof(uint32_t)); 378 if (!rtc_dev.conf_data->cid_confs || !rtc_dev.conf_data->sec_conf || 379 !rtc_dev.conf_data->priv_conf || !rtc_dev.conf_data->access_mask) 380 panic("Not enough memory capacity for RTC RIF config"); 381 382 for (i = 0; i < rtc_dev.nb_res; i++) 383 stm32_rif_parse_cfg(fdt32_to_cpu(cuint[i]), rtc_dev.conf_data, 384 RTC_NB_RIF_RESOURCES); 385 386 return TEE_SUCCESS; 387 } 388 389 static TEE_Result stm32_rtc_enter_init_mode(void) 390 { 391 vaddr_t base = get_base(); 392 uint32_t icsr = io_read32(base + RTC_ICSR); 393 uint32_t value = 0; 394 395 if (!(icsr & RTC_ICSR_INITF)) { 396 icsr |= RTC_ICSR_INIT; 397 io_write32(base + RTC_ICSR, icsr); 398 399 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 400 value & RTC_ICSR_INITF, 401 10, TIMEOUT_US_RTC_GENERIC)) 402 return TEE_ERROR_BUSY; 403 } 404 405 return TEE_SUCCESS; 406 } 407 408 static void stm32_rtc_exit_init_mode(void) 409 { 410 io_clrbits32(get_base() + RTC_ICSR, RTC_ICSR_INIT); 411 dsb(); 412 } 413 414 static TEE_Result stm32_rtc_wait_sync(void) 415 { 416 vaddr_t base = get_base(); 417 uint32_t value = 0; 418 419 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 420 421 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, value, 422 value & RTC_ICSR_RSF, 10, 423 TIMEOUT_US_RTC_GENERIC)) 424 return TEE_ERROR_BUSY; 425 426 return TEE_SUCCESS; 427 } 428 429 static TEE_Result stm32_rtc_get_time(struct rtc *rtc __unused, 430 struct optee_rtc_time *tm) 431 { 432 vaddr_t base = get_base(); 433 uint32_t ssr = 0; 434 uint32_t dr = 0; 435 uint32_t tr = 0; 436 437 if (!stm32_rtc_get_bypshad()) { 438 uint32_t icsr = 0; 439 440 /* Wait calendar registers are ready */ 441 io_clrbits32(base + RTC_ICSR, RTC_ICSR_RSF); 442 443 if (IO_READ32_POLL_TIMEOUT(base + RTC_ICSR, icsr, 444 icsr & RTC_ICSR_RSF, 0, 445 TIMEOUT_US_RTC_SHADOW)) 446 panic(); 447 } 448 449 /* 450 * In our RTC we start : 451 * - year at 0 452 * - month at 1 453 * - day at 1 454 * - weekday at Monday = 1 455 * Change month value so it becomes 0=January, 1 = February, ... 456 * Change week day value so it becomes 0=Sunday, 1 = Monday, ... 457 */ 458 459 ssr = io_read32(base + RTC_SSR); 460 tr = io_read32(base + RTC_TR); 461 dr = io_read32(base + RTC_DR); 462 463 tm->tm_hour = ((tr & RTC_TR_HT_MASK) >> RTC_TR_HT_SHIFT) * 10 + 464 ((tr & RTC_TR_HU_MASK) >> RTC_TR_HU_SHIFT); 465 466 if (tr & RTC_TR_PM) 467 tm->tm_hour += 12; 468 469 tm->tm_ms = (stm32_rtc_get_subsecond(ssr) * MS_PER_SEC) / 470 stm32_rtc_get_subsecond_scale(); 471 472 tm->tm_sec = ((tr & RTC_TR_ST_MASK) >> RTC_TR_ST_SHIFT) * 10 + 473 (tr & RTC_TR_SU_MASK); 474 475 tm->tm_min = ((tr & RTC_TR_MNT_MASK) >> RTC_TR_MNT_SHIFT) * 10 + 476 ((tr & RTC_TR_MNU_MASK) >> RTC_TR_MNU_SHIFT); 477 478 tm->tm_wday = ((dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT) % 7; 479 480 tm->tm_mday = ((dr & RTC_DR_DT_MASK) >> RTC_DR_DT_SHIFT) * 10 + 481 (dr & RTC_DR_DU_MASK); 482 483 tm->tm_mon = ((dr & RTC_DR_MT_MASK) >> RTC_DR_MT_SHIFT) * 10 + 484 ((dr & RTC_DR_MU_MASK) >> RTC_DR_MU_SHIFT) - 1; 485 486 tm->tm_year = ((dr & RTC_DR_YT_MASK) >> RTC_DR_YT_SHIFT) * 10 + 487 ((dr & RTC_DR_YU_MASK) >> RTC_DR_YU_SHIFT) + YEAR_REF; 488 489 return TEE_SUCCESS; 490 } 491 492 static TEE_Result stm32_rtc_set_time(struct rtc *rtc, struct optee_rtc_time *tm) 493 { 494 TEE_Result res = TEE_ERROR_GENERIC; 495 vaddr_t rtc_base = get_base(); 496 uint32_t tr = 0; 497 uint32_t dr = 0; 498 499 /* 500 * In our RTC we start : 501 * - year at 0 502 * - month at 1 503 * - day at 1 504 * - weekday at Monday = 1 505 * Change month value so it becomes 1=January, 2 = February, ... 506 * Change week day value so it becomes 7=Sunday, 1 = Monday, ... 507 */ 508 tr = ((tm->tm_sec % 10) & RTC_TR_SU_MASK) | 509 (SHIFT_U32(tm->tm_sec / 10, RTC_TR_ST_SHIFT) & RTC_TR_ST_MASK) | 510 (SHIFT_U32(tm->tm_min % 10, RTC_TR_MNU_SHIFT) & RTC_TR_MNU_MASK) | 511 (SHIFT_U32(tm->tm_min / 10, RTC_TR_MNT_SHIFT) & RTC_TR_MNT_MASK) | 512 (SHIFT_U32(tm->tm_hour % 10, RTC_TR_HU_SHIFT) & RTC_TR_HU_MASK) | 513 (SHIFT_U32(tm->tm_hour / 10, RTC_TR_HT_SHIFT) & RTC_TR_HT_MASK); 514 515 dr = ((tm->tm_mday % 10) & RTC_DR_DU_MASK) | 516 (SHIFT_U32(tm->tm_mday / 10, RTC_DR_DT_SHIFT) & RTC_DR_DT_MASK) | 517 (SHIFT_U32((tm->tm_mon + 1) % 10, RTC_DR_MU_SHIFT) & 518 RTC_DR_MU_MASK) | 519 (SHIFT_U32((tm->tm_mon + 1) / 10, RTC_DR_MT_SHIFT) & 520 RTC_DR_MT_MASK) | 521 (SHIFT_U32(tm->tm_wday ? tm->tm_wday : 7, RTC_DR_WDU_SHIFT) & 522 RTC_DR_WDU_MASK) | 523 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) % 10, 524 RTC_DR_YU_SHIFT) & RTC_DR_YU_MASK) | 525 (SHIFT_U32((tm->tm_year - rtc->range_min.tm_year) / 10, 526 RTC_DR_YT_SHIFT) & RTC_DR_YT_MASK); 527 528 stm32_rtc_write_unprotect(); 529 530 res = stm32_rtc_enter_init_mode(); 531 if (res) 532 goto end; 533 534 io_write32(rtc_base + RTC_TR, tr); 535 io_write32(rtc_base + RTC_DR, dr); 536 537 stm32_rtc_exit_init_mode(); 538 539 res = stm32_rtc_wait_sync(); 540 end: 541 stm32_rtc_write_protect(); 542 543 return res; 544 } 545 546 static const struct rtc_ops stm32_rtc_ops = { 547 .get_time = stm32_rtc_get_time, 548 .set_time = stm32_rtc_set_time, 549 }; 550 551 static struct rtc stm32_rtc = { 552 .ops = &stm32_rtc_ops, 553 .range_min = RTC_TIME(YEAR_REF, 0, 1, 0, 0, 0, 0, 0), 554 .range_max = RTC_TIME(YEAR_MAX, 11, 31, 4, 23, 59, 59, 999), 555 }; 556 557 static TEE_Result stm32_rtc_probe(const void *fdt, int node, 558 const void *compat_data) 559 { 560 TEE_Result res = TEE_ERROR_GENERIC; 561 bool is_tdcid = false; 562 563 rtc_dev.compat = compat_data; 564 565 if (rtc_dev.compat->has_rif_support) { 566 res = stm32_rifsc_check_tdcid(&is_tdcid); 567 if (res) 568 return res; 569 } 570 571 res = parse_dt(fdt, node); 572 if (res) { 573 memset(&rtc_dev, 0, sizeof(rtc_dev)); 574 return res; 575 } 576 577 /* Unbalanced clock enable to ensure RTC core clock is always on */ 578 res = clk_enable(rtc_dev.rtc_ck); 579 if (res) 580 panic("Couldn't enable RTC clock"); 581 582 if (clk_get_rate(rtc_dev.pclk) < (clk_get_rate(rtc_dev.rtc_ck) * 7)) 583 rtc_dev.flags |= RTC_FLAGS_READ_TWICE; 584 585 if (rtc_dev.compat->has_rif_support) { 586 res = clk_enable(rtc_dev.pclk); 587 if (res) 588 panic("Could not enable RTC bus clock"); 589 590 apply_rif_config(is_tdcid); 591 592 /* 593 * Verify if applied RIF config will not disable 594 * other functionalities of this driver. 595 */ 596 res = check_rif_config(); 597 if (res) 598 panic("Incompatible RTC RIF configuration"); 599 600 clk_disable(rtc_dev.pclk); 601 } 602 603 rtc_register(&stm32_rtc); 604 605 return res; 606 } 607 608 static const struct rtc_compat mp25_compat = { 609 .has_seccfgr = true, 610 .has_rif_support = true, 611 }; 612 613 static const struct rtc_compat mp15_compat = { 614 .has_seccfgr = false, 615 .has_rif_support = false, 616 }; 617 618 static const struct rtc_compat mp13_compat = { 619 .has_seccfgr = true, 620 .has_rif_support = false, 621 }; 622 623 static const struct dt_device_match stm32_rtc_match_table[] = { 624 { 625 .compatible = "st,stm32mp25-rtc", 626 .compat_data = &mp25_compat, 627 }, 628 { 629 .compatible = "st,stm32mp1-rtc", 630 .compat_data = &mp15_compat, 631 }, 632 { 633 .compatible = "st,stm32mp13-rtc", 634 .compat_data = &mp13_compat, 635 }, 636 { } 637 }; 638 639 DEFINE_DT_DRIVER(stm32_rtc_dt_driver) = { 640 .name = "stm32-rtc", 641 .match_table = stm32_rtc_match_table, 642 .probe = stm32_rtc_probe, 643 }; 644