1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <drivers/stm32_rng.h> 8 #include <io.h> 9 #include <kernel/delay.h> 10 #include <kernel/dt.h> 11 #include <kernel/boot.h> 12 #include <kernel/panic.h> 13 #include <libfdt.h> 14 #include <mm/core_memprot.h> 15 #include <stdbool.h> 16 #include <stm32_util.h> 17 #include <string.h> 18 19 #define DT_RNG_COMPAT "st,stm32-rng" 20 #define RNG_CR 0x00U 21 #define RNG_SR 0x04U 22 #define RNG_DR 0x08U 23 24 #define RNG_CR_RNGEN BIT(2) 25 #define RNG_CR_IE BIT(3) 26 #define RNG_CR_CED BIT(5) 27 28 #define RNG_SR_DRDY BIT(0) 29 #define RNG_SR_CECS BIT(1) 30 #define RNG_SR_SECS BIT(2) 31 #define RNG_SR_CEIS BIT(5) 32 #define RNG_SR_SEIS BIT(6) 33 34 #define RNG_TIMEOUT_US 10000 35 36 struct stm32_rng_instance { 37 struct io_pa_va base; 38 unsigned long clock; 39 unsigned int lock; 40 unsigned int refcount; 41 }; 42 43 static struct stm32_rng_instance *stm32_rng; 44 45 /* 46 * Extracts from the STM32 RNG specification: 47 * 48 * When a noise source (or seed) error occurs, the RNG stops generating 49 * random numbers and sets to “1” both SEIS and SECS bits to indicate 50 * that a seed error occurred. (...) 51 52 * The following sequence shall be used to fully recover from a seed 53 * error after the RNG initialization: 54 * 1. Clear the SEIS bit by writing it to “0”. 55 * 2. Read out 12 words from the RNG_DR register, and discard each of 56 * them in order to clean the pipeline. 57 * 3. Confirm that SEIS is still cleared. Random number generation is 58 * back to normal. 59 */ 60 static void conceal_seed_error(vaddr_t rng_base) 61 { 62 if (io_read32(rng_base + RNG_SR) & (RNG_SR_SECS | RNG_SR_SEIS)) { 63 size_t i = 0; 64 65 io_mask32(rng_base + RNG_SR, 0, RNG_SR_SEIS); 66 67 for (i = 12; i != 0; i--) 68 (void)io_read32(rng_base + RNG_DR); 69 70 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) 71 panic("RNG noise"); 72 } 73 } 74 75 #define RNG_FIFO_BYTE_DEPTH 16u 76 77 TEE_Result stm32_rng_read_raw(vaddr_t rng_base, uint8_t *out, size_t *size) 78 { 79 bool enabled = false; 80 TEE_Result rc = TEE_ERROR_SECURITY; 81 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); 82 uint64_t timeout_ref = timeout_init_us(RNG_TIMEOUT_US); 83 84 if (!(io_read32(rng_base + RNG_CR) & RNG_CR_RNGEN)) { 85 /* Enable RNG if not, clock error is disabled */ 86 io_write32(rng_base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED); 87 enabled = true; 88 } 89 90 /* Wait RNG has produced well seeded random samples */ 91 while (!timeout_elapsed(timeout_ref)) { 92 conceal_seed_error(rng_base); 93 94 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) 95 break; 96 } 97 98 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) { 99 uint8_t *buf = out; 100 size_t req_size = MIN(RNG_FIFO_BYTE_DEPTH, *size); 101 size_t len = req_size; 102 103 /* RNG is ready: read up to 4 32bit words */ 104 while (len) { 105 uint32_t data32 = io_read32(rng_base + RNG_DR); 106 size_t sz = MIN(len, sizeof(uint32_t)); 107 108 memcpy(buf, &data32, sz); 109 buf += sz; 110 len -= sz; 111 } 112 rc = TEE_SUCCESS; 113 *size = req_size; 114 } 115 116 if (enabled) 117 io_write32(rng_base + RNG_CR, 0); 118 119 thread_unmask_exceptions(exceptions); 120 121 return rc; 122 } 123 124 static void gate_rng(bool enable, struct stm32_rng_instance *dev) 125 { 126 vaddr_t rng_cr = io_pa_or_va(&dev->base) + RNG_CR; 127 uint32_t exceptions = may_spin_lock(&dev->lock); 128 129 if (enable) { 130 /* incr_refcnt return non zero if resource shall be enabled */ 131 if (incr_refcnt(&dev->refcount)) { 132 stm32_clock_enable(dev->clock); 133 io_write32(rng_cr, 0); 134 io_write32(rng_cr, RNG_CR_RNGEN | RNG_CR_CED); 135 } 136 } else { 137 /* decr_refcnt return non zero if resource shall be disabled */ 138 if (decr_refcnt(&dev->refcount)) { 139 io_write32(rng_cr, 0); 140 stm32_clock_disable(dev->clock); 141 } 142 } 143 144 may_spin_unlock(&dev->lock, exceptions); 145 } 146 147 TEE_Result stm32_rng_read(uint8_t *out, size_t size) 148 { 149 TEE_Result rc = 0; 150 uint32_t exceptions = 0; 151 vaddr_t rng_base = io_pa_or_va(&stm32_rng->base); 152 uint8_t *out_ptr = out; 153 size_t out_size = 0; 154 155 if (!stm32_rng) { 156 DMSG("No RNG"); 157 return TEE_ERROR_NOT_SUPPORTED; 158 } 159 160 gate_rng(true, stm32_rng); 161 162 while (out_size < size) { 163 /* Read by chunks of the size the RNG FIFO depth */ 164 size_t sz = size - out_size; 165 166 exceptions = may_spin_lock(&stm32_rng->lock); 167 168 rc = stm32_rng_read_raw(rng_base, out_ptr, &sz); 169 170 may_spin_unlock(&stm32_rng->lock, exceptions); 171 172 if (rc) 173 goto bail; 174 175 out_size += sz; 176 out_ptr += sz; 177 } 178 179 bail: 180 gate_rng(false, stm32_rng); 181 if (rc) 182 memset(out, 0, size); 183 184 return rc; 185 } 186 187 #ifdef CFG_EMBED_DTB 188 static TEE_Result stm32_rng_init(void) 189 { 190 void *fdt = NULL; 191 int node = -1; 192 struct dt_node_info dt_info; 193 enum teecore_memtypes mtype = MEM_AREA_END; 194 195 memset(&dt_info, 0, sizeof(dt_info)); 196 197 fdt = get_embedded_dt(); 198 if (!fdt) 199 panic(); 200 201 while (true) { 202 node = fdt_node_offset_by_compatible(fdt, node, DT_RNG_COMPAT); 203 if (node < 0) 204 break; 205 206 _fdt_fill_device_info(fdt, &dt_info, node); 207 208 if (!(dt_info.status & DT_STATUS_OK_SEC)) 209 continue; 210 211 if (stm32_rng) 212 panic(); 213 214 stm32_rng = calloc(1, sizeof(*stm32_rng)); 215 if (!stm32_rng) 216 panic(); 217 218 assert(dt_info.clock != DT_INFO_INVALID_CLOCK && 219 dt_info.reg != DT_INFO_INVALID_REG); 220 221 if (dt_info.status & DT_STATUS_OK_NSEC) { 222 stm32mp_register_non_secure_periph_iomem(dt_info.reg); 223 mtype = MEM_AREA_IO_NSEC; 224 } else { 225 stm32mp_register_secure_periph_iomem(dt_info.reg); 226 mtype = MEM_AREA_IO_SEC; 227 } 228 229 stm32_rng->base.pa = dt_info.reg; 230 stm32_rng->base.va = (vaddr_t)phys_to_virt(dt_info.reg, mtype); 231 232 stm32_rng->clock = (unsigned long)dt_info.clock; 233 234 DMSG("RNG init"); 235 } 236 237 return TEE_SUCCESS; 238 } 239 240 driver_init(stm32_rng_init); 241 #endif /*CFG_EMBED_DTB*/ 242