1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2018-2019, STMicroelectronics 4 */ 5 6 #include <assert.h> 7 #include <drivers/stm32_rng.h> 8 #include <io.h> 9 #include <kernel/delay.h> 10 #include <kernel/dt.h> 11 #include <kernel/boot.h> 12 #include <kernel/panic.h> 13 #include <kernel/thread.h> 14 #include <libfdt.h> 15 #include <mm/core_memprot.h> 16 #include <stdbool.h> 17 #include <stm32_util.h> 18 #include <string.h> 19 20 #define DT_RNG_COMPAT "st,stm32-rng" 21 #define RNG_CR 0x00U 22 #define RNG_SR 0x04U 23 #define RNG_DR 0x08U 24 25 #define RNG_CR_RNGEN BIT(2) 26 #define RNG_CR_IE BIT(3) 27 #define RNG_CR_CED BIT(5) 28 29 #define RNG_SR_DRDY BIT(0) 30 #define RNG_SR_CECS BIT(1) 31 #define RNG_SR_SECS BIT(2) 32 #define RNG_SR_CEIS BIT(5) 33 #define RNG_SR_SEIS BIT(6) 34 35 #define RNG_TIMEOUT_US 10000 36 37 struct stm32_rng_instance { 38 struct io_pa_va base; 39 unsigned long clock; 40 unsigned int lock; 41 unsigned int refcount; 42 }; 43 44 static struct stm32_rng_instance *stm32_rng; 45 46 /* 47 * Extracts from the STM32 RNG specification: 48 * 49 * When a noise source (or seed) error occurs, the RNG stops generating 50 * random numbers and sets to “1” both SEIS and SECS bits to indicate 51 * that a seed error occurred. (...) 52 53 * The following sequence shall be used to fully recover from a seed 54 * error after the RNG initialization: 55 * 1. Clear the SEIS bit by writing it to “0”. 56 * 2. Read out 12 words from the RNG_DR register, and discard each of 57 * them in order to clean the pipeline. 58 * 3. Confirm that SEIS is still cleared. Random number generation is 59 * back to normal. 60 */ 61 static void conceal_seed_error(vaddr_t rng_base) 62 { 63 if (io_read32(rng_base + RNG_SR) & (RNG_SR_SECS | RNG_SR_SEIS)) { 64 size_t i = 0; 65 66 io_mask32(rng_base + RNG_SR, 0, RNG_SR_SEIS); 67 68 for (i = 12; i != 0; i--) 69 (void)io_read32(rng_base + RNG_DR); 70 71 if (io_read32(rng_base + RNG_SR) & RNG_SR_SEIS) 72 panic("RNG noise"); 73 } 74 } 75 76 #define RNG_FIFO_BYTE_DEPTH 16u 77 78 TEE_Result stm32_rng_read_raw(vaddr_t rng_base, uint8_t *out, size_t *size) 79 { 80 bool enabled = false; 81 TEE_Result rc = TEE_ERROR_SECURITY; 82 uint32_t exceptions = thread_mask_exceptions(THREAD_EXCP_ALL); 83 uint64_t timeout_ref = timeout_init_us(RNG_TIMEOUT_US); 84 85 if (!(io_read32(rng_base + RNG_CR) & RNG_CR_RNGEN)) { 86 /* Enable RNG if not, clock error is disabled */ 87 io_write32(rng_base + RNG_CR, RNG_CR_RNGEN | RNG_CR_CED); 88 enabled = true; 89 } 90 91 /* Wait RNG has produced well seeded random samples */ 92 while (!timeout_elapsed(timeout_ref)) { 93 conceal_seed_error(rng_base); 94 95 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) 96 break; 97 } 98 99 if (io_read32(rng_base + RNG_SR) & RNG_SR_DRDY) { 100 uint8_t *buf = out; 101 size_t req_size = MIN(RNG_FIFO_BYTE_DEPTH, *size); 102 size_t len = req_size; 103 104 /* RNG is ready: read up to 4 32bit words */ 105 while (len) { 106 uint32_t data32 = io_read32(rng_base + RNG_DR); 107 size_t sz = MIN(len, sizeof(uint32_t)); 108 109 memcpy(buf, &data32, sz); 110 buf += sz; 111 len -= sz; 112 } 113 rc = TEE_SUCCESS; 114 *size = req_size; 115 } 116 117 if (enabled) 118 io_write32(rng_base + RNG_CR, 0); 119 120 thread_unmask_exceptions(exceptions); 121 122 return rc; 123 } 124 125 static void gate_rng(bool enable, struct stm32_rng_instance *dev) 126 { 127 vaddr_t rng_cr = io_pa_or_va(&dev->base) + RNG_CR; 128 uint32_t exceptions = may_spin_lock(&dev->lock); 129 130 if (enable) { 131 /* incr_refcnt return non zero if resource shall be enabled */ 132 if (incr_refcnt(&dev->refcount)) { 133 stm32_clock_enable(dev->clock); 134 io_write32(rng_cr, 0); 135 io_write32(rng_cr, RNG_CR_RNGEN | RNG_CR_CED); 136 } 137 } else { 138 /* decr_refcnt return non zero if resource shall be disabled */ 139 if (decr_refcnt(&dev->refcount)) { 140 io_write32(rng_cr, 0); 141 stm32_clock_disable(dev->clock); 142 } 143 } 144 145 may_spin_unlock(&dev->lock, exceptions); 146 } 147 148 TEE_Result stm32_rng_read(uint8_t *out, size_t size) 149 { 150 TEE_Result rc = 0; 151 uint32_t exceptions = 0; 152 vaddr_t rng_base = io_pa_or_va(&stm32_rng->base); 153 uint8_t *out_ptr = out; 154 size_t out_size = 0; 155 156 if (!stm32_rng) { 157 DMSG("No RNG"); 158 return TEE_ERROR_NOT_SUPPORTED; 159 } 160 161 gate_rng(true, stm32_rng); 162 163 while (out_size < size) { 164 /* Read by chunks of the size the RNG FIFO depth */ 165 size_t sz = size - out_size; 166 167 exceptions = may_spin_lock(&stm32_rng->lock); 168 169 rc = stm32_rng_read_raw(rng_base, out_ptr, &sz); 170 171 may_spin_unlock(&stm32_rng->lock, exceptions); 172 173 if (rc) 174 goto bail; 175 176 out_size += sz; 177 out_ptr += sz; 178 } 179 180 bail: 181 gate_rng(false, stm32_rng); 182 if (rc) 183 memset(out, 0, size); 184 185 return rc; 186 } 187 188 #ifdef CFG_EMBED_DTB 189 static TEE_Result stm32_rng_init(void) 190 { 191 void *fdt = NULL; 192 int node = -1; 193 struct dt_node_info dt_info; 194 enum teecore_memtypes mtype = MEM_AREA_END; 195 196 memset(&dt_info, 0, sizeof(dt_info)); 197 198 fdt = get_embedded_dt(); 199 if (!fdt) 200 panic(); 201 202 while (true) { 203 node = fdt_node_offset_by_compatible(fdt, node, DT_RNG_COMPAT); 204 if (node < 0) 205 break; 206 207 _fdt_fill_device_info(fdt, &dt_info, node); 208 209 if (!(dt_info.status & DT_STATUS_OK_SEC)) 210 continue; 211 212 if (stm32_rng) 213 panic(); 214 215 stm32_rng = calloc(1, sizeof(*stm32_rng)); 216 if (!stm32_rng) 217 panic(); 218 219 assert(dt_info.clock != DT_INFO_INVALID_CLOCK && 220 dt_info.reg != DT_INFO_INVALID_REG); 221 222 if (dt_info.status & DT_STATUS_OK_NSEC) { 223 stm32mp_register_non_secure_periph_iomem(dt_info.reg); 224 mtype = MEM_AREA_IO_NSEC; 225 } else { 226 stm32mp_register_secure_periph_iomem(dt_info.reg); 227 mtype = MEM_AREA_IO_SEC; 228 } 229 230 stm32_rng->base.pa = dt_info.reg; 231 stm32_rng->base.va = (vaddr_t)phys_to_virt(dt_info.reg, mtype); 232 233 stm32_rng->clock = (unsigned long)dt_info.clock; 234 235 DMSG("RNG init"); 236 } 237 238 return TEE_SUCCESS; 239 } 240 241 driver_init(stm32_rng_init); 242 #endif /*CFG_EMBED_DTB*/ 243