xref: /optee_os/core/drivers/stm32_iwdg.c (revision f6ee86ec9430b4c912b7b91158d2b0cd88f6a174) 
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3  * Copyright (c) 2017-2025, STMicroelectronics - All Rights Reserved
4  */
5 
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/rstctrl.h>
10 #include <drivers/wdt.h>
11 #include <io.h>
12 #include <keep.h>
13 #include <kernel/boot.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/dt_driver.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/panic.h>
20 #include <kernel/pm.h>
21 #include <kernel/spinlock.h>
22 #include <kernel/tee_time.h>
23 #include <libfdt.h>
24 #include <mm/core_memprot.h>
25 #include <sm/sm.h>
26 #include <stdint.h>
27 #include <stm32_util.h>
28 #include <string.h>
29 #include <trace.h>
30 
31 /* IWDG Compatibility */
32 #define IWDG_TIMEOUT_US		U(10000)
33 #define IWDG_CNT_MASK		GENMASK_32(11, 0)
34 #define IWDG_ONF_MIN_VER	U(0x31)
35 #define IWDG_ICR_MIN_VER	U(0x40)
36 
37 /* IWDG registers offsets */
38 #define IWDG_KR_OFFSET		U(0x00)
39 #define IWDG_PR_OFFSET		U(0x04)
40 #define IWDG_RLR_OFFSET		U(0x08)
41 #define IWDG_SR_OFFSET		U(0x0C)
42 #define IWDG_EWCR_OFFSET	U(0x14)
43 #define IWDG_ICR_OFFSET		U(0x18)
44 #define IWDG_VERR_OFFSET	U(0x3F4)
45 
46 #define IWDG_KR_WPROT_KEY	U(0x0000)
47 #define IWDG_KR_ACCESS_KEY	U(0x5555)
48 #define IWDG_KR_RELOAD_KEY	U(0xAAAA)
49 #define IWDG_KR_START_KEY	U(0xCCCC)
50 
51 /* Use a fixed prescaler divider of 256 */
52 #define IWDG_PRESCALER_256	U(256)
53 #define IWDG_PR_DIV_256		U(0x06)
54 #define IWDG_PR_DIV_MASK	GENMASK_32(3, 0)
55 
56 #define IWDG_SR_PVU		BIT(0)
57 #define IWDG_SR_RVU		BIT(1)
58 #define IWDG_SR_WVU		BIT(2)
59 #define IWDG_SR_EWU		BIT(3)
60 #define IWDG_SR_UPDATE_MASK	(IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \
61 				 IWDG_SR_EWU)
62 #define IWDG_SR_ONF		BIT(8)
63 #define IWDG_SR_EWIF		BIT(14)
64 #define IWDG_SR_EWIF_V40	BIT(15)
65 
66 #define IWDG_EWCR_EWIE		BIT(15)
67 #define IWDG_EWCR_EWIC		BIT(14)
68 
69 #define IWDG_ICR_EWIC		BIT(15)
70 
71 #define IWDG_VERR_REV_MASK	GENMASK_32(7, 0)
72 
73 /* Define default early timeout delay to 5 sec before timeout */
74 #define IWDG_ETIMEOUT_SEC	U(5)
75 
76 /*
77  * Values for struct stm32_iwdg_device::flags
78  * IWDG_FLAGS_ENABLED			Watchdog has been enabled
79  */
80 #define IWDG_FLAGS_ENABLED			BIT(0)
81 
82 /*
83  * IWDG watch instance data
84  * @base - IWDG interface IOMEM base address
85  * @clk_pclk - Bus clock
86  * @clk_lsi - IWDG source clock
87  * @itr_chip - Interrupt chip device
88  * @itr_num - Interrupt number for the IWDG instance
89  * @itr_handler - Interrupt handler
90  * @reset - Reset controller device used to control the ability of the watchdog
91  *          to reset the system
92  * @flags - Property flags for the IWDG instance
93  * @timeout - Watchdog elaspure timeout
94  * @saved_nb_int - Saved number of interrupts before panic
95  * @nb_int - Remaining number of interrupts before panic
96  * @hw_version - Watchdog HW version
97  * @last_refresh - Time of last watchdog refresh
98  * @wdt_chip - Wathcdog chip instance
99  * @max_hw_timeout - Maximum hardware timeout
100  */
101 struct stm32_iwdg_device {
102 	struct io_pa_va base;
103 	struct clk *clk_pclk;
104 	struct clk *clk_lsi;
105 	struct itr_chip *itr_chip;
106 	size_t itr_num;
107 	struct itr_handler *itr_handler;
108 	struct rstctrl *reset;
109 	uint32_t flags;
110 	unsigned long timeout;
111 	unsigned long early_timeout;
112 	unsigned long saved_nb_int;
113 	unsigned long nb_int;
114 	unsigned int hw_version;
115 	TEE_Time last_refresh;
116 	struct wdt_chip wdt_chip;
117 	unsigned long max_hw_timeout;
118 };
119 
120 static uint32_t sr_ewif_mask(struct stm32_iwdg_device *iwdg)
121 {
122 	if (iwdg->hw_version >= IWDG_ICR_MIN_VER)
123 		return IWDG_SR_EWIF_V40;
124 	else
125 		return IWDG_SR_EWIF;
126 }
127 
128 static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
129 {
130 	return io_pa_or_va(&iwdg->base, 1);
131 }
132 
133 static void iwdg_wdt_set_enabled(struct stm32_iwdg_device *iwdg)
134 {
135 	iwdg->flags |= IWDG_FLAGS_ENABLED;
136 }
137 
138 static bool iwdg_wdt_is_enabled(struct stm32_iwdg_device *iwdg)
139 {
140 	return iwdg->flags & IWDG_FLAGS_ENABLED;
141 }
142 
143 /* Return counter value to related to input timeout in seconds, or 0 on error */
144 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg,
145 				 unsigned long to_sec)
146 {
147 	uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi);
148 	uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1;
149 
150 	/* Be safe and expect any counter to be above 2 */
151 	if (cnt > IWDG_CNT_MASK || cnt < 3)
152 		return 0;
153 
154 	return cnt;
155 }
156 
157 /* Wait IWDG programming completes */
158 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg)
159 {
160 	uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US);
161 	vaddr_t iwdg_base = get_base(iwdg);
162 
163 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
164 		if (timeout_elapsed(timeout_ref))
165 			break;
166 
167 	if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
168 		return TEE_ERROR_GENERIC;
169 
170 	return TEE_SUCCESS;
171 }
172 
173 static void stm32_iwdg_it_ack(struct stm32_iwdg_device *iwdg)
174 {
175 	vaddr_t iwdg_base = get_base(iwdg);
176 
177 	if (iwdg->hw_version >= IWDG_ICR_MIN_VER)
178 		io_setbits32(iwdg_base + IWDG_ICR_OFFSET, IWDG_ICR_EWIC);
179 	else
180 		io_setbits32(iwdg_base + IWDG_EWCR_OFFSET, IWDG_EWCR_EWIC);
181 }
182 
183 static enum itr_return stm32_iwdg_it_handler(struct itr_handler *h)
184 {
185 	unsigned int __maybe_unused cpu = get_core_pos();
186 	struct stm32_iwdg_device *iwdg = h->data;
187 	vaddr_t iwdg_base = get_base(iwdg);
188 
189 	DMSG("CPU %u IT Watchdog %#"PRIxPA, cpu, iwdg->base.pa);
190 
191 	/* Check for spurious interrupt */
192 	if (!(io_read32(iwdg_base + IWDG_SR_OFFSET) & sr_ewif_mask(iwdg)))
193 		return ITRR_NONE;
194 
195 	/*
196 	 * Writing IWDG_EWCR_EWIT triggers a watchdog refresh.
197 	 * To prevent the watchdog refresh, write-protect all the registers;
198 	 * this makes read-only all IWDG_EWCR fields except IWDG_EWCR_EWIC.
199 	 */
200 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_WPROT_KEY);
201 
202 	/* Disable early interrupt */
203 	stm32_iwdg_it_ack(iwdg);
204 
205 	if (iwdg->nb_int > 0) {
206 		iwdg->nb_int--;
207 		io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
208 	} else {
209 		panic("Watchdog");
210 	}
211 
212 	return ITRR_HANDLED;
213 }
214 DECLARE_KEEP_PAGER(stm32_iwdg_it_handler);
215 
216 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
217 {
218 	TEE_Result res = TEE_ERROR_GENERIC;
219 	vaddr_t iwdg_base = get_base(iwdg);
220 	uint32_t rlr_value = 0;
221 	uint32_t ewie_value = 0;
222 
223 	assert(iwdg_wdt_is_enabled(iwdg));
224 
225 	rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout);
226 	if (!rlr_value)
227 		return TEE_ERROR_GENERIC;
228 
229 	if (iwdg->itr_handler) {
230 		ewie_value = iwdg_timeout_cnt(iwdg, iwdg->early_timeout);
231 		interrupt_enable(iwdg->itr_chip, iwdg->itr_num);
232 	}
233 
234 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
235 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
236 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
237 	if (ewie_value &&
238 	    !(io_read32(iwdg_base + IWDG_EWCR_OFFSET) & IWDG_EWCR_EWIE))
239 		io_write32(iwdg_base + IWDG_EWCR_OFFSET,
240 			   ewie_value | IWDG_EWCR_EWIE);
241 
242 	res = iwdg_wait_sync(iwdg);
243 
244 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
245 
246 	return res;
247 }
248 
249 static void iwdg_start(struct stm32_iwdg_device *iwdg)
250 {
251 	TEE_Result res = TEE_ERROR_GENERIC;
252 
253 	res = tee_time_get_sys_time(&iwdg->last_refresh);
254 	if (res)
255 		panic();
256 
257 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
258 
259 	iwdg_wdt_set_enabled(iwdg);
260 }
261 
262 static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
263 {
264 	TEE_Result res = TEE_ERROR_GENERIC;
265 
266 	res = tee_time_get_sys_time(&iwdg->last_refresh);
267 	if (res)
268 		panic();
269 
270 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
271 }
272 
273 /* Operators for watchdog OP-TEE interface */
274 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip)
275 {
276 	return container_of(chip, struct stm32_iwdg_device, wdt_chip);
277 }
278 
279 static TEE_Result iwdg_wdt_init(struct wdt_chip *chip,
280 				unsigned long *min_timeout,
281 				unsigned long *max_timeout)
282 {
283 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
284 	unsigned long rate = clk_get_rate(iwdg->clk_lsi);
285 
286 	if (!rate)
287 		return TEE_ERROR_GENERIC;
288 
289 	/* Be safe and expect any counter to be above 2 */
290 	*min_timeout = 3 * IWDG_PRESCALER_256 / rate;
291 	*max_timeout = INT32_MAX;
292 
293 	return TEE_SUCCESS;
294 }
295 
296 static void iwdg_wdt_start(struct wdt_chip *chip)
297 {
298 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
299 
300 	iwdg_start(iwdg);
301 	if (iwdg->reset && iwdg->itr_handler)
302 		stm32_iwdg_it_ack(iwdg);
303 
304 	if (configure_timeout(iwdg))
305 		panic();
306 
307 	if (iwdg->reset)
308 		if (rstctrl_assert(iwdg->reset))
309 			panic();
310 }
311 
312 static void iwdg_wdt_stop(struct wdt_chip *chip)
313 {
314 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
315 
316 	if (iwdg->reset) {
317 		if (rstctrl_deassert(iwdg->reset))
318 			panic();
319 		if (iwdg->itr_handler)
320 			interrupt_disable(iwdg->itr_chip, iwdg->itr_num);
321 	}
322 }
323 
324 static void iwdg_wdt_refresh(struct wdt_chip *chip)
325 {
326 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
327 
328 	iwdg->nb_int = iwdg->saved_nb_int;
329 	iwdg_refresh(iwdg);
330 }
331 
332 static void stm32_iwdg_handle_timeouts(struct stm32_iwdg_device *iwdg,
333 				       unsigned long timeout_sec)
334 {
335 	unsigned long interval = 0;
336 	unsigned long rate = 0;
337 	unsigned long n = 0;
338 	long w = 0;
339 
340 	rate = clk_get_rate(iwdg->clk_lsi);
341 	iwdg->max_hw_timeout = (IWDG_CNT_MASK + 1) * IWDG_PRESCALER_256 / rate;
342 
343 	if (timeout_sec > iwdg->max_hw_timeout) {
344 		IMSG("Timeout exceeds hardware capability, approximate it");
345 		interval = iwdg->max_hw_timeout - IWDG_ETIMEOUT_SEC;
346 		n = (timeout_sec - IWDG_ETIMEOUT_SEC) / interval;
347 		w = ((timeout_sec - IWDG_ETIMEOUT_SEC) / (n + 1)) +
348 		IWDG_ETIMEOUT_SEC;
349 		iwdg->timeout = w;
350 		iwdg->early_timeout = IWDG_ETIMEOUT_SEC;
351 	} else {
352 		iwdg->timeout = timeout_sec;
353 		if (iwdg->timeout >= 2 * IWDG_ETIMEOUT_SEC)
354 			iwdg->early_timeout = IWDG_ETIMEOUT_SEC;
355 		else
356 			iwdg->early_timeout = iwdg->timeout / 4;
357 	}
358 
359 	if (!iwdg->early_timeout)
360 		iwdg->early_timeout = 1;
361 
362 	iwdg->saved_nb_int = n;
363 	iwdg->nb_int = n;
364 }
365 
366 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip,
367 				       unsigned long timeout)
368 {
369 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
370 
371 	if (iwdg_wdt_is_enabled(iwdg)) {
372 		TEE_Result res = TEE_ERROR_GENERIC;
373 
374 		stm32_iwdg_handle_timeouts(iwdg, timeout);
375 
376 		res = configure_timeout(iwdg);
377 		if (res)
378 			return res;
379 	}
380 
381 	return TEE_SUCCESS;
382 }
383 
384 static TEE_Result iwdg_wdt_get_timeleft(struct wdt_chip *chip, bool *is_started,
385 					unsigned long *timeleft)
386 {
387 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
388 	TEE_Result res = TEE_ERROR_GENERIC;
389 	TEE_Time time = { };
390 	TEE_Time now = { };
391 
392 	*is_started = iwdg_wdt_is_enabled(iwdg);
393 
394 	if (!*is_started)
395 		return TEE_SUCCESS;
396 
397 	res = tee_time_get_sys_time(&now);
398 	if (res)
399 		panic();
400 
401 	time.seconds =
402 		(iwdg->timeout - iwdg->early_timeout) * iwdg->saved_nb_int
403 		+ iwdg->early_timeout;
404 	TEE_TIME_ADD(iwdg->last_refresh, time, time);
405 	if (TEE_TIME_LE(time, now)) {
406 		*timeleft = 0;
407 	} else {
408 		TEE_TIME_SUB(time, now, time);
409 		*timeleft = time.seconds;
410 	}
411 
412 	return TEE_SUCCESS;
413 }
414 
415 static const struct wdt_ops stm32_iwdg_ops = {
416 	.init = iwdg_wdt_init,
417 	.start = iwdg_wdt_start,
418 	.stop = iwdg_wdt_stop,
419 	.ping = iwdg_wdt_refresh,
420 	.set_timeout = iwdg_wdt_set_timeout,
421 	.get_timeleft = iwdg_wdt_get_timeleft,
422 };
423 DECLARE_KEEP_PAGER(stm32_iwdg_ops);
424 
425 /* Driver initialization */
426 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
427 				       const void *fdt, int node)
428 {
429 	TEE_Result res = TEE_ERROR_GENERIC;
430 	struct dt_node_info dt_info = { };
431 	const fdt32_t *cuint = NULL;
432 
433 	fdt_fill_device_info(fdt, &dt_info, node);
434 
435 	if (dt_info.reg == DT_INFO_INVALID_REG ||
436 	    dt_info.reg_size == DT_INFO_INVALID_REG_SIZE)
437 		panic();
438 
439 	res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clk_pclk);
440 	if (res)
441 		return res;
442 
443 	res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi);
444 	if (res)
445 		return res;
446 
447 	res = interrupt_dt_get(fdt, node, &iwdg->itr_chip, &iwdg->itr_num);
448 	if (res && res != TEE_ERROR_ITEM_NOT_FOUND)
449 		return res;
450 	if (!res) {
451 		res = interrupt_create_handler(iwdg->itr_chip, iwdg->itr_num,
452 					       stm32_iwdg_it_handler, iwdg, 0,
453 					       &iwdg->itr_handler);
454 		if (res)
455 			return res;
456 	}
457 
458 	res = rstctrl_dt_get_by_index(fdt, node, 0, &iwdg->reset);
459 	if (res && res != TEE_ERROR_ITEM_NOT_FOUND)
460 		goto err_itr;
461 
462 	/* Get IOMEM address */
463 	iwdg->base.pa = dt_info.reg;
464 	io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
465 	assert(iwdg->base.va);
466 
467 	/* Get and check timeout value */
468 	cuint = fdt_getprop(fdt, node, "timeout-sec", NULL);
469 	if (!cuint) {
470 		res = TEE_ERROR_BAD_PARAMETERS;
471 		goto err_itr;
472 	}
473 
474 	iwdg->timeout = (int)fdt32_to_cpu(*cuint);
475 	if (!iwdg->timeout) {
476 		res = TEE_ERROR_BAD_PARAMETERS;
477 		goto err_itr;
478 	}
479 
480 	return TEE_SUCCESS;
481 
482 err_itr:
483 	interrupt_remove_free_handler(iwdg->itr_handler);
484 
485 	return res;
486 }
487 
488 static void iwdg_wdt_get_version_and_status(struct stm32_iwdg_device *iwdg)
489 {
490 	vaddr_t iwdg_base = get_base(iwdg);
491 	uint32_t rlr_value = 0;
492 
493 	iwdg->hw_version = io_read32(iwdg_base + IWDG_VERR_OFFSET) &
494 			   IWDG_VERR_REV_MASK;
495 
496 	/* Test if watchdog is already running */
497 	if (iwdg->hw_version >= IWDG_ONF_MIN_VER) {
498 		if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_ONF)
499 			iwdg_wdt_set_enabled(iwdg);
500 	} else {
501 		/*
502 		 * Workaround for old versions without IWDG_SR_ONF bit:
503 		 * - write in IWDG_RLR_OFFSET
504 		 * - wait for sync
505 		 * - if sync succeeds, then iwdg is running
506 		 */
507 		io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
508 
509 		rlr_value = io_read32(iwdg_base + IWDG_RLR_OFFSET);
510 		io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
511 
512 		if (!iwdg_wait_sync(iwdg))
513 			iwdg_wdt_set_enabled(iwdg);
514 
515 		io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_WPROT_KEY);
516 	}
517 
518 	DMSG("Watchdog is %sabled", iwdg_wdt_is_enabled(iwdg) ? "en" : "dis");
519 }
520 
521 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
522 				   const void *fdt, int node)
523 {
524 	TEE_Result res = TEE_SUCCESS;
525 
526 	res = stm32_iwdg_parse_fdt(iwdg, fdt, node);
527 	if (res)
528 		return res;
529 
530 	/* Enable watchdog source and bus clocks once for all */
531 	if (clk_enable(iwdg->clk_lsi))
532 		panic();
533 
534 	if (clk_enable(iwdg->clk_pclk))
535 		panic();
536 
537 	iwdg_wdt_get_version_and_status(iwdg);
538 
539 	res = iwdg_wdt_set_timeout(&iwdg->wdt_chip, iwdg->timeout);
540 	if (res)
541 		panic();
542 
543 	if (iwdg_wdt_is_enabled(iwdg))
544 		iwdg_wdt_refresh(&iwdg->wdt_chip);
545 
546 	return TEE_SUCCESS;
547 }
548 
549 static TEE_Result stm32_iwdg_pm(enum pm_op op, unsigned int pm_hint __unused,
550 				const struct pm_callback_handle *pm_handle)
551 {
552 	struct stm32_iwdg_device *iwdg = PM_CALLBACK_GET_HANDLE(pm_handle);
553 
554 	if (op == PM_OP_RESUME) {
555 		clk_enable(iwdg->clk_lsi);
556 		clk_enable(iwdg->clk_pclk);
557 	} else {
558 		clk_disable(iwdg->clk_lsi);
559 		clk_disable(iwdg->clk_pclk);
560 	}
561 
562 	return TEE_SUCCESS;
563 }
564 DECLARE_KEEP_PAGER(stm32_iwdg_pm);
565 
566 static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
567 				   const void *compat_data __unused)
568 {
569 	struct stm32_iwdg_device *iwdg = NULL;
570 	TEE_Result res = TEE_SUCCESS;
571 
572 	iwdg = calloc(1, sizeof(*iwdg));
573 	if (!iwdg)
574 		return TEE_ERROR_OUT_OF_MEMORY;
575 
576 	res = stm32_iwdg_setup(iwdg, fdt, node);
577 	if (res)
578 		goto out_free;
579 
580 	iwdg->wdt_chip.ops = &stm32_iwdg_ops;
581 
582 	register_pm_core_service_cb(stm32_iwdg_pm, iwdg, "stm32-iwdg");
583 
584 	res = watchdog_register(&iwdg->wdt_chip);
585 	if (res)
586 		goto out_pm;
587 
588 	return TEE_SUCCESS;
589 
590 out_pm:
591 	unregister_pm_core_service_cb(stm32_iwdg_pm, iwdg);
592 out_free:
593 	free(iwdg);
594 
595 	return res;
596 }
597 
598 static const struct dt_device_match stm32_iwdg_match_table[] = {
599 	{ .compatible = "st,stm32mp1-iwdg" },
600 	{ }
601 };
602 
603 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = {
604 	.name = "stm32-iwdg",
605 	.match_table = stm32_iwdg_match_table,
606 	.probe = stm32_iwdg_probe,
607 };
608