xref: /optee_os/core/drivers/stm32_iwdg.c (revision af3fb62410645ac9636d27c3d1db72c0c9fca913) 
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3  * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4  */
5 
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_iwdg.h>
10 #include <drivers/wdt.h>
11 #include <io.h>
12 #include <keep.h>
13 #include <kernel/boot.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/dt_driver.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/panic.h>
20 #include <kernel/pm.h>
21 #include <kernel/spinlock.h>
22 #include <libfdt.h>
23 #include <mm/core_memprot.h>
24 #include <sm/sm.h>
25 #include <stm32_util.h>
26 #include <string.h>
27 #include <trace.h>
28 
29 /* IWDG Compatibility */
30 #define IWDG_TIMEOUT_US		U(1000)
31 #define IWDG_CNT_MASK		GENMASK_32(11, 0)
32 
33 /* IWDG registers offsets */
34 #define IWDG_KR_OFFSET		U(0x00)
35 #define IWDG_PR_OFFSET		U(0x04)
36 #define IWDG_RLR_OFFSET		U(0x08)
37 #define IWDG_SR_OFFSET		U(0x0C)
38 #define IWDG_EWCR_OFFSET	U(0x14)
39 
40 #define IWDG_KR_ACCESS_KEY	U(0x5555)
41 #define IWDG_KR_RELOAD_KEY	U(0xAAAA)
42 #define IWDG_KR_START_KEY	U(0xCCCC)
43 
44 /* Use a fixed prescaler divider of 256 */
45 #define IWDG_PRESCALER_256	U(256)
46 #define IWDG_PR_DIV_256		U(0x06)
47 #define IWDG_PR_DIV_MASK	GENMASK_32(3, 0)
48 
49 #define IWDG_SR_PVU		BIT(0)
50 #define IWDG_SR_RVU		BIT(1)
51 #define IWDG_SR_WVU		BIT(2)
52 #define IWDG_SR_EWU		BIT(3)
53 #define IWDG_SR_UPDATE_MASK	(IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \
54 				 IWDG_SR_EWU)
55 
56 #define IWDG_EWCR_EWIE		BIT(15)
57 #define IWDG_EWCR_EWIC		BIT(14)
58 
59 /*
60  * Values for struct stm32_iwdg_device::flags
61  * IWDG_FLAGS_HW_ENABLED                Watchdog is enabled by BootROM
62  * IWDG_FLAGS_DISABLE_ON_STOP           Watchdog is freezed in SoC STOP mode
63  * IWDG_FLAGS_DISABLE_ON_STANDBY        Watchdog is freezed in SoC STANDBY mode
64  * IWDG_FLAGS_NON_SECURE                Instance is assigned to non-secure world
65  * IWDG_FLAGS_ENABLED			Watchdog has been enabled
66  */
67 #define IWDG_FLAGS_HW_ENABLED			BIT(0)
68 #define IWDG_FLAGS_DISABLE_ON_STOP		BIT(1)
69 #define IWDG_FLAGS_DISABLE_ON_STANDBY		BIT(2)
70 #define IWDG_FLAGS_NON_SECURE			BIT(3)
71 #define IWDG_FLAGS_ENABLED			BIT(4)
72 
73 /*
74  * IWDG watch instance data
75  * @base - IWDG interface IOMEM base address
76  * @clk_pclk - Bus clock
77  * @clk_lsi - IWDG source clock
78  * @flags - Property flags for the IWDG instance
79  * @timeout - Watchdog elaspure timeout
80  * @wdt_chip - Wathcdog chip instance
81  * @link - Link in registered watchdog instance list
82  */
83 struct stm32_iwdg_device {
84 	struct io_pa_va base;
85 	struct clk *clk_pclk;
86 	struct clk *clk_lsi;
87 	uint32_t flags;
88 	unsigned long timeout;
89 	struct wdt_chip wdt_chip;
90 	SLIST_ENTRY(stm32_iwdg_device) link;
91 };
92 
93 static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list =
94 	SLIST_HEAD_INITIALIZER(iwdg_dev_list_head);
95 
96 static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
97 {
98 	return io_pa_or_va(&iwdg->base, 1);
99 }
100 
101 static bool is_assigned_to_nsec(struct stm32_iwdg_device *iwdg)
102 {
103 	return iwdg->flags & IWDG_FLAGS_NON_SECURE;
104 }
105 
106 static void iwdg_wdt_set_enabled(struct stm32_iwdg_device *iwdg)
107 {
108 	iwdg->flags |= IWDG_FLAGS_ENABLED;
109 }
110 
111 static bool iwdg_wdt_is_enabled(struct stm32_iwdg_device *iwdg)
112 {
113 	return iwdg->flags & IWDG_FLAGS_ENABLED;
114 }
115 
116 /* Return counter value to related to input timeout in seconds, or 0 on error */
117 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg,
118 				 unsigned long to_sec)
119 {
120 	uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi);
121 	uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1;
122 
123 	/* Be safe and expect any counter to be above 2 */
124 	if (cnt > IWDG_CNT_MASK || cnt < 3)
125 		return 0;
126 
127 	return cnt;
128 }
129 
130 /* Wait IWDG programming completes */
131 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg)
132 {
133 	uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US);
134 	vaddr_t iwdg_base = get_base(iwdg);
135 
136 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
137 		if (timeout_elapsed(timeout_ref))
138 			break;
139 
140 	if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
141 		return TEE_ERROR_GENERIC;
142 
143 	return TEE_SUCCESS;
144 }
145 
146 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
147 {
148 	TEE_Result res = TEE_ERROR_GENERIC;
149 	vaddr_t iwdg_base = get_base(iwdg);
150 	uint32_t rlr_value = 0;
151 
152 	assert(iwdg_wdt_is_enabled(iwdg));
153 
154 	rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout);
155 	if (!rlr_value)
156 		return TEE_ERROR_GENERIC;
157 
158 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
159 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
160 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
161 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
162 
163 	res = iwdg_wait_sync(iwdg);
164 
165 	return res;
166 }
167 
168 static void iwdg_start(struct stm32_iwdg_device *iwdg)
169 {
170 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
171 
172 	iwdg_wdt_set_enabled(iwdg);
173 }
174 
175 static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
176 {
177 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
178 }
179 
180 /* Operators for watchdog OP-TEE interface */
181 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip)
182 {
183 	return container_of(chip, struct stm32_iwdg_device, wdt_chip);
184 }
185 
186 static TEE_Result iwdg_wdt_init(struct wdt_chip *chip,
187 				unsigned long *min_timeout,
188 				unsigned long *max_timeout)
189 {
190 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
191 	unsigned long rate = clk_get_rate(iwdg->clk_lsi);
192 
193 	if (!rate)
194 		return TEE_ERROR_GENERIC;
195 
196 	/* Be safe and expect any counter to be above 2 */
197 	*min_timeout = 3 * IWDG_PRESCALER_256 / rate;
198 	*max_timeout = (IWDG_CNT_MASK + 1) * IWDG_PRESCALER_256 / rate;
199 
200 	return TEE_SUCCESS;
201 }
202 
203 static void iwdg_wdt_start(struct wdt_chip *chip)
204 {
205 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
206 
207 	iwdg_start(iwdg);
208 
209 	if (configure_timeout(iwdg))
210 		panic();
211 }
212 
213 static void iwdg_wdt_refresh(struct wdt_chip *chip)
214 {
215 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
216 
217 	iwdg_refresh(iwdg);
218 }
219 
220 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip,
221 				       unsigned long timeout)
222 {
223 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
224 
225 	if (!iwdg_timeout_cnt(iwdg, timeout))
226 		return TEE_ERROR_BAD_PARAMETERS;
227 
228 	iwdg->timeout = timeout;
229 
230 	if (iwdg_wdt_is_enabled(iwdg)) {
231 		TEE_Result res = TEE_ERROR_GENERIC;
232 
233 		res = configure_timeout(iwdg);
234 		if (res)
235 			return res;
236 	}
237 
238 	return TEE_SUCCESS;
239 }
240 
241 static const struct wdt_ops stm32_iwdg_ops = {
242 	.init = iwdg_wdt_init,
243 	.start = iwdg_wdt_start,
244 	.ping = iwdg_wdt_refresh,
245 	.set_timeout = iwdg_wdt_set_timeout,
246 };
247 DECLARE_KEEP_PAGER(stm32_iwdg_ops);
248 
249 /* Driver initialization */
250 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
251 				       const void *fdt, int node)
252 {
253 	TEE_Result res = TEE_ERROR_GENERIC;
254 	struct dt_node_info dt_info = { };
255 	const fdt32_t *cuint = NULL;
256 
257 	fdt_fill_device_info(fdt, &dt_info, node);
258 
259 	if (dt_info.reg == DT_INFO_INVALID_REG ||
260 	    dt_info.reg_size == DT_INFO_INVALID_REG_SIZE)
261 		panic();
262 
263 	res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clk_pclk);
264 	if (res)
265 		return res;
266 
267 	res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi);
268 	if (res)
269 		return res;
270 
271 	if (dt_info.status == DT_STATUS_OK_NSEC)
272 		iwdg->flags |= IWDG_FLAGS_NON_SECURE;
273 
274 	/* Get IOMEM address */
275 	iwdg->base.pa = dt_info.reg;
276 
277 	if (iwdg->flags & IWDG_FLAGS_NON_SECURE)
278 		io_pa_or_va_nsec(&iwdg->base, dt_info.reg_size);
279 	else
280 		io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
281 
282 	assert(iwdg->base.va);
283 
284 	/* Get and check timeout value */
285 	cuint = fdt_getprop(fdt, node, "timeout-sec", NULL);
286 	if (!cuint)
287 		return TEE_ERROR_BAD_PARAMETERS;
288 
289 	iwdg->timeout = (int)fdt32_to_cpu(*cuint);
290 	if (!iwdg->timeout)
291 		return TEE_ERROR_BAD_PARAMETERS;
292 
293 	if (!iwdg_timeout_cnt(iwdg, iwdg->timeout)) {
294 		EMSG("Timeout %lu not applicable", iwdg->timeout);
295 		return TEE_ERROR_BAD_PARAMETERS;
296 	}
297 
298 	/* DT can specify low power cases */
299 	if (!fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL))
300 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
301 
302 	if (!fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL))
303 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
304 
305 	return TEE_SUCCESS;
306 }
307 
308 /* Platform should override this function to provide IWDG fuses configuration */
309 TEE_Result __weak stm32_get_iwdg_otp_config(paddr_t pbase __unused,
310 					    struct stm32_iwdg_otp_data *otp_d)
311 {
312 	otp_d->hw_enabled = false;
313 	otp_d->disable_on_stop = false;
314 	otp_d->disable_on_standby = false;
315 
316 	return TEE_SUCCESS;
317 }
318 
319 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
320 				   const void *fdt, int node)
321 {
322 	struct stm32_iwdg_otp_data otp_data = { };
323 	TEE_Result res = TEE_SUCCESS;
324 
325 	res = stm32_iwdg_parse_fdt(iwdg, fdt, node);
326 	if (res)
327 		return res;
328 
329 	res = stm32_get_iwdg_otp_config(iwdg->base.pa, &otp_data);
330 	if (res)
331 		return res;
332 
333 	if (otp_data.hw_enabled)
334 		iwdg->flags |= IWDG_FLAGS_HW_ENABLED;
335 	if (otp_data.disable_on_stop)
336 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
337 	if (otp_data.disable_on_standby)
338 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
339 
340 	/* Enable watchdog source and bus clocks once for all */
341 	clk_enable(iwdg->clk_lsi);
342 	clk_enable(iwdg->clk_pclk);
343 
344 	if (otp_data.hw_enabled) {
345 		iwdg->flags |= IWDG_FLAGS_ENABLED;
346 
347 		/* Configure timeout if watchdog is already enabled */
348 		res = configure_timeout(iwdg);
349 		if (res)
350 			return res;
351 
352 		iwdg_refresh(iwdg);
353 	}
354 
355 	return TEE_SUCCESS;
356 }
357 
358 static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg)
359 {
360 	TEE_Result res = TEE_ERROR_GENERIC;
361 
362 	if (is_assigned_to_nsec(iwdg)) {
363 		stm32mp_register_non_secure_periph_iomem(iwdg->base.pa);
364 	} else {
365 		stm32mp_register_secure_periph_iomem(iwdg->base.pa);
366 
367 		/* Expose watchdog runtime service only to secure IWDG */
368 		iwdg->wdt_chip.ops = &stm32_iwdg_ops;
369 
370 		res = watchdog_register(&iwdg->wdt_chip);
371 		if (res)
372 			return res;
373 	}
374 
375 	SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link);
376 
377 	return TEE_SUCCESS;
378 }
379 
380 static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
381 				   const void *compat_data __unused)
382 {
383 	struct stm32_iwdg_device *iwdg = NULL;
384 	TEE_Result res = TEE_SUCCESS;
385 
386 	iwdg = calloc(1, sizeof(*iwdg));
387 	if (!iwdg)
388 		return TEE_ERROR_OUT_OF_MEMORY;
389 
390 	res = stm32_iwdg_setup(iwdg, fdt, node);
391 	if (res)
392 		goto err;
393 
394 	res = stm32_iwdg_register(iwdg);
395 	if (res)
396 		goto err;
397 
398 	return TEE_SUCCESS;
399 
400 err:
401 	free(iwdg);
402 	return res;
403 }
404 
405 static const struct dt_device_match stm32_iwdg_match_table[] = {
406 	{ .compatible = "st,stm32mp1-iwdg" },
407 	{ }
408 };
409 
410 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = {
411 	.name = "stm32-iwdg",
412 	.match_table = stm32_iwdg_match_table,
413 	.probe = stm32_iwdg_probe,
414 };
415