1 // SPDX-License-Identifier: BSD-3-Clause 2 /* 3 * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved 4 */ 5 6 #include <assert.h> 7 #include <drivers/clk.h> 8 #include <drivers/clk_dt.h> 9 #include <drivers/stm32_iwdg.h> 10 #include <drivers/wdt.h> 11 #include <io.h> 12 #include <keep.h> 13 #include <kernel/boot.h> 14 #include <kernel/delay.h> 15 #include <kernel/dt.h> 16 #include <kernel/dt_driver.h> 17 #include <kernel/interrupt.h> 18 #include <kernel/misc.h> 19 #include <kernel/panic.h> 20 #include <kernel/pm.h> 21 #include <kernel/spinlock.h> 22 #include <libfdt.h> 23 #include <mm/core_memprot.h> 24 #include <sm/sm.h> 25 #include <stm32_util.h> 26 #include <string.h> 27 #include <trace.h> 28 29 /* IWDG Compatibility */ 30 #define IWDG_TIMEOUT_US U(1000) 31 #define IWDG_CNT_MASK GENMASK_32(11, 0) 32 33 /* IWDG registers offsets */ 34 #define IWDG_KR_OFFSET U(0x00) 35 #define IWDG_PR_OFFSET U(0x04) 36 #define IWDG_RLR_OFFSET U(0x08) 37 #define IWDG_SR_OFFSET U(0x0C) 38 #define IWDG_EWCR_OFFSET U(0x14) 39 40 #define IWDG_KR_ACCESS_KEY U(0x5555) 41 #define IWDG_KR_RELOAD_KEY U(0xAAAA) 42 #define IWDG_KR_START_KEY U(0xCCCC) 43 44 /* Use a fixed prescaler divider of 256 */ 45 #define IWDG_PRESCALER_256 U(256) 46 #define IWDG_PR_DIV_256 U(0x06) 47 #define IWDG_PR_DIV_MASK GENMASK_32(3, 0) 48 49 #define IWDG_SR_PVU BIT(0) 50 #define IWDG_SR_RVU BIT(1) 51 #define IWDG_SR_WVU BIT(2) 52 #define IWDG_SR_EWU BIT(3) 53 #define IWDG_SR_UPDATE_MASK (IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \ 54 IWDG_SR_EWU) 55 56 #define IWDG_EWCR_EWIE BIT(15) 57 #define IWDG_EWCR_EWIC BIT(14) 58 59 /* 60 * Values for struct stm32_iwdg_device::flags 61 * IWDG_FLAGS_HW_ENABLED Watchdog is enabled by BootROM 62 * IWDG_FLAGS_DISABLE_ON_STOP Watchdog is freezed in SoC STOP mode 63 * IWDG_FLAGS_DISABLE_ON_STANDBY Watchdog is freezed in SoC STANDBY mode 64 * IWDG_FLAGS_ENABLED Watchdog has been enabled 65 */ 66 #define IWDG_FLAGS_HW_ENABLED BIT(0) 67 #define IWDG_FLAGS_DISABLE_ON_STOP BIT(1) 68 #define IWDG_FLAGS_DISABLE_ON_STANDBY BIT(2) 69 #define IWDG_FLAGS_ENABLED BIT(3) 70 71 /* 72 * IWDG watch instance data 73 * @base - IWDG interface IOMEM base address 74 * @clk_pclk - Bus clock 75 * @clk_lsi - IWDG source clock 76 * @flags - Property flags for the IWDG instance 77 * @timeout - Watchdog elaspure timeout 78 * @wdt_chip - Wathcdog chip instance 79 * @link - Link in registered watchdog instance list 80 */ 81 struct stm32_iwdg_device { 82 struct io_pa_va base; 83 struct clk *clk_pclk; 84 struct clk *clk_lsi; 85 uint32_t flags; 86 unsigned long timeout; 87 struct wdt_chip wdt_chip; 88 SLIST_ENTRY(stm32_iwdg_device) link; 89 }; 90 91 static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list = 92 SLIST_HEAD_INITIALIZER(iwdg_dev_list_head); 93 94 static vaddr_t get_base(struct stm32_iwdg_device *iwdg) 95 { 96 return io_pa_or_va(&iwdg->base, 1); 97 } 98 99 static void iwdg_wdt_set_enabled(struct stm32_iwdg_device *iwdg) 100 { 101 iwdg->flags |= IWDG_FLAGS_ENABLED; 102 } 103 104 static bool iwdg_wdt_is_enabled(struct stm32_iwdg_device *iwdg) 105 { 106 return iwdg->flags & IWDG_FLAGS_ENABLED; 107 } 108 109 /* Return counter value to related to input timeout in seconds, or 0 on error */ 110 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg, 111 unsigned long to_sec) 112 { 113 uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi); 114 uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1; 115 116 /* Be safe and expect any counter to be above 2 */ 117 if (cnt > IWDG_CNT_MASK || cnt < 3) 118 return 0; 119 120 return cnt; 121 } 122 123 /* Wait IWDG programming completes */ 124 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg) 125 { 126 uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US); 127 vaddr_t iwdg_base = get_base(iwdg); 128 129 while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK) 130 if (timeout_elapsed(timeout_ref)) 131 break; 132 133 if (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK) 134 return TEE_ERROR_GENERIC; 135 136 return TEE_SUCCESS; 137 } 138 139 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg) 140 { 141 TEE_Result res = TEE_ERROR_GENERIC; 142 vaddr_t iwdg_base = get_base(iwdg); 143 uint32_t rlr_value = 0; 144 145 assert(iwdg_wdt_is_enabled(iwdg)); 146 147 rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout); 148 if (!rlr_value) 149 return TEE_ERROR_GENERIC; 150 151 io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY); 152 io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256); 153 io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value); 154 io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY); 155 156 res = iwdg_wait_sync(iwdg); 157 158 return res; 159 } 160 161 static void iwdg_start(struct stm32_iwdg_device *iwdg) 162 { 163 io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY); 164 165 iwdg_wdt_set_enabled(iwdg); 166 } 167 168 static void iwdg_refresh(struct stm32_iwdg_device *iwdg) 169 { 170 io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY); 171 } 172 173 /* Operators for watchdog OP-TEE interface */ 174 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip) 175 { 176 return container_of(chip, struct stm32_iwdg_device, wdt_chip); 177 } 178 179 static TEE_Result iwdg_wdt_init(struct wdt_chip *chip, 180 unsigned long *min_timeout, 181 unsigned long *max_timeout) 182 { 183 struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip); 184 unsigned long rate = clk_get_rate(iwdg->clk_lsi); 185 186 if (!rate) 187 return TEE_ERROR_GENERIC; 188 189 /* Be safe and expect any counter to be above 2 */ 190 *min_timeout = 3 * IWDG_PRESCALER_256 / rate; 191 *max_timeout = (IWDG_CNT_MASK + 1) * IWDG_PRESCALER_256 / rate; 192 193 return TEE_SUCCESS; 194 } 195 196 static void iwdg_wdt_start(struct wdt_chip *chip) 197 { 198 struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip); 199 200 iwdg_start(iwdg); 201 202 if (configure_timeout(iwdg)) 203 panic(); 204 } 205 206 static void iwdg_wdt_refresh(struct wdt_chip *chip) 207 { 208 struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip); 209 210 iwdg_refresh(iwdg); 211 } 212 213 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip, 214 unsigned long timeout) 215 { 216 struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip); 217 218 if (!iwdg_timeout_cnt(iwdg, timeout)) 219 return TEE_ERROR_BAD_PARAMETERS; 220 221 iwdg->timeout = timeout; 222 223 if (iwdg_wdt_is_enabled(iwdg)) { 224 TEE_Result res = TEE_ERROR_GENERIC; 225 226 res = configure_timeout(iwdg); 227 if (res) 228 return res; 229 } 230 231 return TEE_SUCCESS; 232 } 233 234 static const struct wdt_ops stm32_iwdg_ops = { 235 .init = iwdg_wdt_init, 236 .start = iwdg_wdt_start, 237 .ping = iwdg_wdt_refresh, 238 .set_timeout = iwdg_wdt_set_timeout, 239 }; 240 DECLARE_KEEP_PAGER(stm32_iwdg_ops); 241 242 /* Driver initialization */ 243 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg, 244 const void *fdt, int node) 245 { 246 TEE_Result res = TEE_ERROR_GENERIC; 247 struct dt_node_info dt_info = { }; 248 const fdt32_t *cuint = NULL; 249 250 fdt_fill_device_info(fdt, &dt_info, node); 251 252 if (dt_info.reg == DT_INFO_INVALID_REG || 253 dt_info.reg_size == DT_INFO_INVALID_REG_SIZE) 254 panic(); 255 256 res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clk_pclk); 257 if (res) 258 return res; 259 260 res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi); 261 if (res) 262 return res; 263 264 /* Get IOMEM address */ 265 iwdg->base.pa = dt_info.reg; 266 io_pa_or_va_secure(&iwdg->base, dt_info.reg_size); 267 assert(iwdg->base.va); 268 269 /* Get and check timeout value */ 270 cuint = fdt_getprop(fdt, node, "timeout-sec", NULL); 271 if (!cuint) 272 return TEE_ERROR_BAD_PARAMETERS; 273 274 iwdg->timeout = (int)fdt32_to_cpu(*cuint); 275 if (!iwdg->timeout) 276 return TEE_ERROR_BAD_PARAMETERS; 277 278 if (!iwdg_timeout_cnt(iwdg, iwdg->timeout)) { 279 EMSG("Timeout %lu not applicable", iwdg->timeout); 280 return TEE_ERROR_BAD_PARAMETERS; 281 } 282 283 /* DT can specify low power cases */ 284 if (!fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL)) 285 iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP; 286 287 if (!fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL)) 288 iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY; 289 290 return TEE_SUCCESS; 291 } 292 293 /* Platform should override this function to provide IWDG fuses configuration */ 294 TEE_Result __weak stm32_get_iwdg_otp_config(paddr_t pbase __unused, 295 struct stm32_iwdg_otp_data *otp_d) 296 { 297 otp_d->hw_enabled = false; 298 otp_d->disable_on_stop = false; 299 otp_d->disable_on_standby = false; 300 301 return TEE_SUCCESS; 302 } 303 304 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg, 305 const void *fdt, int node) 306 { 307 struct stm32_iwdg_otp_data otp_data = { }; 308 TEE_Result res = TEE_SUCCESS; 309 310 res = stm32_iwdg_parse_fdt(iwdg, fdt, node); 311 if (res) 312 return res; 313 314 res = stm32_get_iwdg_otp_config(iwdg->base.pa, &otp_data); 315 if (res) 316 return res; 317 318 if (otp_data.hw_enabled) 319 iwdg->flags |= IWDG_FLAGS_HW_ENABLED; 320 if (otp_data.disable_on_stop) 321 iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP; 322 if (otp_data.disable_on_standby) 323 iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY; 324 325 /* Enable watchdog source and bus clocks once for all */ 326 clk_enable(iwdg->clk_lsi); 327 clk_enable(iwdg->clk_pclk); 328 329 if (otp_data.hw_enabled) { 330 iwdg->flags |= IWDG_FLAGS_ENABLED; 331 332 /* Configure timeout if watchdog is already enabled */ 333 res = configure_timeout(iwdg); 334 if (res) 335 return res; 336 337 iwdg_refresh(iwdg); 338 } 339 340 return TEE_SUCCESS; 341 } 342 343 static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg) 344 { 345 TEE_Result res = TEE_ERROR_GENERIC; 346 347 iwdg->wdt_chip.ops = &stm32_iwdg_ops; 348 349 res = watchdog_register(&iwdg->wdt_chip); 350 if (res) 351 return res; 352 353 SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link); 354 355 return TEE_SUCCESS; 356 } 357 358 static TEE_Result stm32_iwdg_probe(const void *fdt, int node, 359 const void *compat_data __unused) 360 { 361 struct stm32_iwdg_device *iwdg = NULL; 362 TEE_Result res = TEE_SUCCESS; 363 364 iwdg = calloc(1, sizeof(*iwdg)); 365 if (!iwdg) 366 return TEE_ERROR_OUT_OF_MEMORY; 367 368 res = stm32_iwdg_setup(iwdg, fdt, node); 369 if (res) 370 goto err; 371 372 res = stm32_iwdg_register(iwdg); 373 if (res) 374 goto err; 375 376 return TEE_SUCCESS; 377 378 err: 379 free(iwdg); 380 return res; 381 } 382 383 static const struct dt_device_match stm32_iwdg_match_table[] = { 384 { .compatible = "st,stm32mp1-iwdg" }, 385 { } 386 }; 387 388 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = { 389 .name = "stm32-iwdg", 390 .match_table = stm32_iwdg_match_table, 391 .probe = stm32_iwdg_probe, 392 }; 393