xref: /optee_os/core/drivers/stm32_iwdg.c (revision 32b3180828fa15a49ccc86ecb4be9d274c140c89) 
1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3  * Copyright (c) 2017-2022, STMicroelectronics - All Rights Reserved
4  */
5 
6 #include <assert.h>
7 #include <drivers/clk.h>
8 #include <drivers/clk_dt.h>
9 #include <drivers/stm32_iwdg.h>
10 #include <drivers/wdt.h>
11 #include <io.h>
12 #include <keep.h>
13 #include <kernel/boot.h>
14 #include <kernel/delay.h>
15 #include <kernel/dt.h>
16 #include <kernel/dt_driver.h>
17 #include <kernel/interrupt.h>
18 #include <kernel/misc.h>
19 #include <kernel/panic.h>
20 #include <kernel/pm.h>
21 #include <kernel/spinlock.h>
22 #include <libfdt.h>
23 #include <mm/core_memprot.h>
24 #include <sm/sm.h>
25 #include <stm32_util.h>
26 #include <string.h>
27 #include <trace.h>
28 
29 /* IWDG Compatibility */
30 #define IWDG_TIMEOUT_US		U(1000)
31 #define IWDG_CNT_MASK		GENMASK_32(11, 0)
32 
33 /* IWDG registers offsets */
34 #define IWDG_KR_OFFSET		U(0x00)
35 #define IWDG_PR_OFFSET		U(0x04)
36 #define IWDG_RLR_OFFSET		U(0x08)
37 #define IWDG_SR_OFFSET		U(0x0C)
38 #define IWDG_EWCR_OFFSET	U(0x14)
39 
40 #define IWDG_KR_ACCESS_KEY	U(0x5555)
41 #define IWDG_KR_RELOAD_KEY	U(0xAAAA)
42 #define IWDG_KR_START_KEY	U(0xCCCC)
43 
44 /* Use a fixed prescaler divider of 256 */
45 #define IWDG_PRESCALER_256	U(256)
46 #define IWDG_PR_DIV_256		U(0x06)
47 #define IWDG_PR_DIV_MASK	GENMASK_32(3, 0)
48 
49 #define IWDG_SR_PVU		BIT(0)
50 #define IWDG_SR_RVU		BIT(1)
51 #define IWDG_SR_WVU		BIT(2)
52 #define IWDG_SR_EWU		BIT(3)
53 #define IWDG_SR_UPDATE_MASK	(IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU | \
54 				 IWDG_SR_EWU)
55 
56 #define IWDG_EWCR_EWIE		BIT(15)
57 #define IWDG_EWCR_EWIC		BIT(14)
58 
59 /*
60  * Values for struct stm32_iwdg_device::flags
61  * IWDG_FLAGS_HW_ENABLED                Watchdog is enabled by BootROM
62  * IWDG_FLAGS_DISABLE_ON_STOP           Watchdog is freezed in SoC STOP mode
63  * IWDG_FLAGS_DISABLE_ON_STANDBY        Watchdog is freezed in SoC STANDBY mode
64  * IWDG_FLAGS_NON_SECURE                Instance is assigned to non-secure world
65  * IWDG_FLAGS_ENABLED			Watchdog has been enabled
66  */
67 #define IWDG_FLAGS_HW_ENABLED			BIT(0)
68 #define IWDG_FLAGS_DISABLE_ON_STOP		BIT(1)
69 #define IWDG_FLAGS_DISABLE_ON_STANDBY		BIT(2)
70 #define IWDG_FLAGS_NON_SECURE			BIT(3)
71 #define IWDG_FLAGS_ENABLED			BIT(4)
72 
73 /*
74  * IWDG watch instance data
75  * @base - IWDG interface IOMEM base address
76  * @clock - Bus clock
77  * @clk_lsi - IWDG source clock
78  * @flags - Property flags for the IWDG instance
79  * @timeout - Watchdog elaspure timeout
80  * @wdt_chip - Wathcdog chip instance
81  * @link - Link in registered watchdog instance list
82  */
83 struct stm32_iwdg_device {
84 	struct io_pa_va base;
85 	struct clk *clock;
86 	struct clk *clk_lsi;
87 	uint32_t flags;
88 	unsigned long timeout;
89 	struct wdt_chip wdt_chip;
90 	SLIST_ENTRY(stm32_iwdg_device) link;
91 };
92 
93 static unsigned int iwdg_lock = SPINLOCK_UNLOCK;
94 
95 static SLIST_HEAD(iwdg_dev_list_head, stm32_iwdg_device) iwdg_dev_list =
96 	SLIST_HEAD_INITIALIZER(iwdg_dev_list_head);
97 
98 static vaddr_t get_base(struct stm32_iwdg_device *iwdg)
99 {
100 	return io_pa_or_va(&iwdg->base, 1);
101 }
102 
103 static bool is_assigned_to_nsec(struct stm32_iwdg_device *iwdg)
104 {
105 	return iwdg->flags & IWDG_FLAGS_NON_SECURE;
106 }
107 
108 static bool is_enable(struct stm32_iwdg_device *iwdg)
109 {
110 	return iwdg->flags & IWDG_FLAGS_ENABLED;
111 }
112 
113 /* Return counter value to related to input timeout in seconds, or 0 on error */
114 static uint32_t iwdg_timeout_cnt(struct stm32_iwdg_device *iwdg,
115 				 unsigned long to_sec)
116 {
117 	uint64_t reload = (uint64_t)to_sec * clk_get_rate(iwdg->clk_lsi);
118 	uint64_t cnt = (reload / IWDG_PRESCALER_256) - 1;
119 
120 	/* Be safe and expect any counter to be above 2 */
121 	if (cnt > IWDG_CNT_MASK || cnt < 3)
122 		return 0;
123 
124 	return cnt;
125 }
126 
127 /* Wait IWDG programming completes */
128 static TEE_Result iwdg_wait_sync(struct stm32_iwdg_device *iwdg)
129 {
130 	uint64_t timeout_ref = timeout_init_us(IWDG_TIMEOUT_US);
131 	vaddr_t iwdg_base = get_base(iwdg);
132 
133 	while (io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK)
134 		if (timeout_elapsed(timeout_ref))
135 			break;
136 
137 	if (!(io_read32(iwdg_base + IWDG_SR_OFFSET) & IWDG_SR_UPDATE_MASK))
138 		return TEE_ERROR_GENERIC;
139 
140 	return TEE_SUCCESS;
141 }
142 
143 static TEE_Result configure_timeout(struct stm32_iwdg_device *iwdg)
144 {
145 	TEE_Result res = TEE_ERROR_GENERIC;
146 	vaddr_t iwdg_base = get_base(iwdg);
147 	uint32_t rlr_value = 0;
148 
149 	assert(is_enable(iwdg));
150 
151 	rlr_value = iwdg_timeout_cnt(iwdg, iwdg->timeout);
152 	if (!rlr_value)
153 		return TEE_ERROR_GENERIC;
154 
155 	clk_enable(iwdg->clock);
156 
157 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_ACCESS_KEY);
158 	io_write32(iwdg_base + IWDG_PR_OFFSET, IWDG_PR_DIV_256);
159 	io_write32(iwdg_base + IWDG_RLR_OFFSET, rlr_value);
160 	io_write32(iwdg_base + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
161 
162 	res = iwdg_wait_sync(iwdg);
163 
164 	clk_disable(iwdg->clock);
165 
166 	return res;
167 }
168 
169 static void iwdg_start(struct stm32_iwdg_device *iwdg)
170 {
171 	clk_enable(iwdg->clock);
172 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_START_KEY);
173 	clk_disable(iwdg->clock);
174 
175 	iwdg->flags |= IWDG_FLAGS_ENABLED;
176 }
177 
178 static void iwdg_refresh(struct stm32_iwdg_device *iwdg)
179 {
180 	clk_enable(iwdg->clock);
181 	io_write32(get_base(iwdg) + IWDG_KR_OFFSET, IWDG_KR_RELOAD_KEY);
182 	clk_disable(iwdg->clock);
183 }
184 
185 /* Operators for watchdog OP-TEE interface */
186 static struct stm32_iwdg_device *wdt_chip_to_iwdg(struct wdt_chip *chip)
187 {
188 	return container_of(chip, struct stm32_iwdg_device, wdt_chip);
189 }
190 
191 static void iwdg_wdt_start(struct wdt_chip *chip)
192 {
193 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
194 
195 	iwdg_start(iwdg);
196 
197 	if (configure_timeout(iwdg))
198 		panic();
199 }
200 
201 static void iwdg_wdt_refresh(struct wdt_chip *chip)
202 {
203 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
204 
205 	iwdg_refresh(iwdg);
206 }
207 
208 static TEE_Result iwdg_wdt_set_timeout(struct wdt_chip *chip,
209 				       unsigned long timeout)
210 {
211 	struct stm32_iwdg_device *iwdg = wdt_chip_to_iwdg(chip);
212 
213 	if (!iwdg_timeout_cnt(iwdg, timeout))
214 		return TEE_ERROR_BAD_PARAMETERS;
215 
216 	iwdg->timeout = timeout;
217 
218 	if (is_enable(iwdg)) {
219 		TEE_Result res = TEE_ERROR_GENERIC;
220 
221 		res = configure_timeout(iwdg);
222 		if (res)
223 			return res;
224 	}
225 
226 	return TEE_SUCCESS;
227 }
228 
229 static const struct wdt_ops stm32_iwdg_ops = {
230 	.start = iwdg_wdt_start,
231 	.ping = iwdg_wdt_refresh,
232 	.set_timeout = iwdg_wdt_set_timeout,
233 };
234 DECLARE_KEEP_PAGER(stm32_iwdg_ops);
235 
236 /* Refresh all registered watchdogs */
237 void stm32_iwdg_refresh(void)
238 {
239 	struct stm32_iwdg_device *iwdg = NULL;
240 	uint32_t exceptions = cpu_spin_lock_xsave(&iwdg_lock);
241 
242 	SLIST_FOREACH(iwdg, &iwdg_dev_list, link)
243 		iwdg_refresh(iwdg);
244 
245 	cpu_spin_unlock_xrestore(&iwdg_lock, exceptions);
246 }
247 
248 /* Driver initialization */
249 static TEE_Result stm32_iwdg_parse_fdt(struct stm32_iwdg_device *iwdg,
250 				       const void *fdt, int node)
251 {
252 	TEE_Result res = TEE_ERROR_GENERIC;
253 	struct dt_node_info dt_info = { };
254 	const fdt32_t *cuint = NULL;
255 
256 	fdt_fill_device_info(fdt, &dt_info, node);
257 
258 	if (dt_info.reg == DT_INFO_INVALID_REG ||
259 	    dt_info.reg_size == DT_INFO_INVALID_REG_SIZE)
260 		panic();
261 
262 	res = clk_dt_get_by_name(fdt, node, "pclk", &iwdg->clock);
263 	if (res)
264 		return res;
265 
266 	res = clk_dt_get_by_name(fdt, node, "lsi", &iwdg->clk_lsi);
267 	if (res)
268 		return res;
269 
270 	if (dt_info.status == DT_STATUS_OK_NSEC)
271 		iwdg->flags |= IWDG_FLAGS_NON_SECURE;
272 
273 	/* Get IOMEM address */
274 	iwdg->base.pa = dt_info.reg;
275 
276 	if (iwdg->flags & IWDG_FLAGS_NON_SECURE)
277 		io_pa_or_va_nsec(&iwdg->base, dt_info.reg_size);
278 	else
279 		io_pa_or_va_secure(&iwdg->base, dt_info.reg_size);
280 
281 	assert(iwdg->base.va);
282 
283 	/* Get and check timeout value */
284 	cuint = fdt_getprop(fdt, node, "timeout-sec", NULL);
285 	if (!cuint)
286 		return TEE_ERROR_BAD_PARAMETERS;
287 
288 	iwdg->timeout = (int)fdt32_to_cpu(*cuint);
289 	if (!iwdg->timeout)
290 		return TEE_ERROR_BAD_PARAMETERS;
291 
292 	if (!iwdg_timeout_cnt(iwdg, iwdg->timeout)) {
293 		EMSG("Timeout %lu not applicable", iwdg->timeout);
294 		return TEE_ERROR_BAD_PARAMETERS;
295 	}
296 
297 	/* DT can specify low power cases */
298 	if (!fdt_getprop(fdt, node, "stm32,enable-on-stop", NULL))
299 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
300 
301 	if (!fdt_getprop(fdt, node, "stm32,enable-on-standby", NULL))
302 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
303 
304 	return TEE_SUCCESS;
305 }
306 
307 /* Platform should override this function to provide IWDG fuses configuration */
308 TEE_Result __weak stm32_get_iwdg_otp_config(paddr_t pbase __unused,
309 					    struct stm32_iwdg_otp_data *otp_d)
310 {
311 	otp_d->hw_enabled = false;
312 	otp_d->disable_on_stop = false;
313 	otp_d->disable_on_standby = false;
314 
315 	return TEE_SUCCESS;
316 }
317 
318 static TEE_Result stm32_iwdg_setup(struct stm32_iwdg_device *iwdg,
319 				   const void *fdt, int node)
320 {
321 	struct stm32_iwdg_otp_data otp_data = { };
322 	TEE_Result res = TEE_SUCCESS;
323 
324 	res = stm32_iwdg_parse_fdt(iwdg, fdt, node);
325 	if (res)
326 		return res;
327 
328 	res = stm32_get_iwdg_otp_config(iwdg->base.pa, &otp_data);
329 	if (res)
330 		return res;
331 
332 	if (otp_data.hw_enabled)
333 		iwdg->flags |= IWDG_FLAGS_HW_ENABLED;
334 	if (otp_data.disable_on_stop)
335 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STOP;
336 	if (otp_data.disable_on_standby)
337 		iwdg->flags |= IWDG_FLAGS_DISABLE_ON_STANDBY;
338 
339 	/* Enable watchdog source clock once for all */
340 	clk_enable(iwdg->clk_lsi);
341 
342 	if (otp_data.hw_enabled) {
343 		iwdg->flags |= IWDG_FLAGS_ENABLED;
344 
345 		/* Configure timeout if watchdog is already enabled */
346 		res = configure_timeout(iwdg);
347 		if (res)
348 			return res;
349 
350 		iwdg_refresh(iwdg);
351 	}
352 
353 	return TEE_SUCCESS;
354 }
355 
356 static TEE_Result stm32_iwdg_register(struct stm32_iwdg_device *iwdg)
357 {
358 	TEE_Result res = TEE_ERROR_GENERIC;
359 
360 	if (is_assigned_to_nsec(iwdg)) {
361 		stm32mp_register_non_secure_periph_iomem(iwdg->base.pa);
362 	} else {
363 		stm32mp_register_secure_periph_iomem(iwdg->base.pa);
364 
365 		/* Expose watchdog runtime service only to secure IWDG */
366 		iwdg->wdt_chip.ops = &stm32_iwdg_ops;
367 
368 		res = watchdog_register(&iwdg->wdt_chip);
369 		if (res)
370 			return res;
371 	}
372 
373 	SLIST_INSERT_HEAD(&iwdg_dev_list, iwdg, link);
374 
375 	return TEE_SUCCESS;
376 }
377 
378 static TEE_Result stm32_iwdg_probe(const void *fdt, int node,
379 				   const void *compat_data __unused)
380 {
381 	struct stm32_iwdg_device *iwdg = NULL;
382 	TEE_Result res = TEE_SUCCESS;
383 
384 	iwdg = calloc(1, sizeof(*iwdg));
385 	if (!iwdg)
386 		return TEE_ERROR_OUT_OF_MEMORY;
387 
388 	res = stm32_iwdg_setup(iwdg, fdt, node);
389 	if (res)
390 		goto err;
391 
392 	res = stm32_iwdg_register(iwdg);
393 	if (res)
394 		goto err;
395 
396 	return TEE_SUCCESS;
397 
398 err:
399 	free(iwdg);
400 	return res;
401 }
402 
403 static const struct dt_device_match stm32_iwdg_match_table[] = {
404 	{ .compatible = "st,stm32mp1-iwdg" },
405 	{ }
406 };
407 
408 DEFINE_DT_DRIVER(stm32_iwdg_dt_driver) = {
409 	.name = "stm32-iwdg",
410 	.match_table = stm32_iwdg_match_table,
411 	.probe = stm32_iwdg_probe,
412 };
413