1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2024, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/clk.h> 14 #include <drivers/clk_dt.h> 15 #include <drivers/pinctrl.h> 16 #include <drivers/stm32_gpio.h> 17 #include <drivers/stm32_i2c.h> 18 #include <io.h> 19 #include <kernel/boot.h> 20 #include <kernel/delay.h> 21 #include <kernel/dt.h> 22 #include <kernel/dt_driver.h> 23 #include <kernel/mutex_pm_aware.h> 24 #include <kernel/panic.h> 25 #include <libfdt.h> 26 #include <stdbool.h> 27 #include <stdlib.h> 28 #include <stm32_util.h> 29 #include <trace.h> 30 31 /* STM32 I2C registers offsets */ 32 #define I2C_CR1 0x00U 33 #define I2C_CR2 0x04U 34 #define I2C_OAR1 0x08U 35 #define I2C_OAR2 0x0CU 36 #define I2C_TIMINGR 0x10U 37 #define I2C_TIMEOUTR 0x14U 38 #define I2C_ISR 0x18U 39 #define I2C_ICR 0x1CU 40 #define I2C_PECR 0x20U 41 #define I2C_RXDR 0x24U 42 #define I2C_TXDR 0x28U 43 #define I2C_SIZE 0x2CU 44 45 /* Bit definition for I2C_CR1 register */ 46 #define I2C_CR1_PE BIT(0) 47 #define I2C_CR1_TXIE BIT(1) 48 #define I2C_CR1_RXIE BIT(2) 49 #define I2C_CR1_ADDRIE BIT(3) 50 #define I2C_CR1_NACKIE BIT(4) 51 #define I2C_CR1_STOPIE BIT(5) 52 #define I2C_CR1_TCIE BIT(6) 53 #define I2C_CR1_ERRIE BIT(7) 54 #define I2C_CR1_DNF GENMASK_32(11, 8) 55 #define I2C_CR1_ANFOFF BIT(12) 56 #define I2C_CR1_SWRST BIT(13) 57 #define I2C_CR1_TXDMAEN BIT(14) 58 #define I2C_CR1_RXDMAEN BIT(15) 59 #define I2C_CR1_SBC BIT(16) 60 #define I2C_CR1_NOSTRETCH BIT(17) 61 #define I2C_CR1_WUPEN BIT(18) 62 #define I2C_CR1_GCEN BIT(19) 63 #define I2C_CR1_SMBHEN BIT(22) 64 #define I2C_CR1_SMBDEN BIT(21) 65 #define I2C_CR1_ALERTEN BIT(22) 66 #define I2C_CR1_PECEN BIT(23) 67 68 /* Bit definition for I2C_CR2 register */ 69 #define I2C_CR2_SADD GENMASK_32(9, 0) 70 #define I2C_CR2_RD_WRN BIT(10) 71 #define I2C_CR2_RD_WRN_OFFSET 10U 72 #define I2C_CR2_ADD10 BIT(11) 73 #define I2C_CR2_HEAD10R BIT(12) 74 #define I2C_CR2_START BIT(13) 75 #define I2C_CR2_STOP BIT(14) 76 #define I2C_CR2_NACK BIT(15) 77 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 78 #define I2C_CR2_NBYTES_OFFSET 16U 79 #define I2C_CR2_RELOAD BIT(24) 80 #define I2C_CR2_AUTOEND BIT(25) 81 #define I2C_CR2_PECBYTE BIT(26) 82 83 /* Bit definition for I2C_OAR1 register */ 84 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 85 #define I2C_OAR1_OA1MODE BIT(10) 86 #define I2C_OAR1_OA1EN BIT(15) 87 88 /* Bit definition for I2C_OAR2 register */ 89 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 90 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 91 #define I2C_OAR2_OA2NOMASK 0 92 #define I2C_OAR2_OA2MASK01 BIT(8) 93 #define I2C_OAR2_OA2MASK02 BIT(9) 94 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 95 #define I2C_OAR2_OA2MASK04 BIT(10) 96 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 97 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 98 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 99 #define I2C_OAR2_OA2EN BIT(15) 100 101 /* Bit definition for I2C_TIMINGR register */ 102 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 103 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 104 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 105 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 106 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 107 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 108 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 109 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 110 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 111 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 112 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 113 (I2C_TIMINGR_SCLL_MAX - 1)) 114 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 115 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 116 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 117 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 118 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 119 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 120 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 121 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 122 123 /* Bit definition for I2C_TIMEOUTR register */ 124 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 125 #define I2C_TIMEOUTR_TIDLE BIT(12) 126 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 127 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 128 #define I2C_TIMEOUTR_TEXTEN BIT(31) 129 130 /* Bit definition for I2C_ISR register */ 131 #define I2C_ISR_TXE BIT(0) 132 #define I2C_ISR_TXIS BIT(1) 133 #define I2C_ISR_RXNE BIT(2) 134 #define I2C_ISR_ADDR BIT(3) 135 #define I2C_ISR_NACKF BIT(4) 136 #define I2C_ISR_STOPF BIT(5) 137 #define I2C_ISR_TC BIT(6) 138 #define I2C_ISR_TCR BIT(7) 139 #define I2C_ISR_BERR BIT(8) 140 #define I2C_ISR_ARLO BIT(9) 141 #define I2C_ISR_OVR BIT(10) 142 #define I2C_ISR_PECERR BIT(11) 143 #define I2C_ISR_TIMEOUT BIT(12) 144 #define I2C_ISR_ALERT BIT(13) 145 #define I2C_ISR_BUSY BIT(15) 146 #define I2C_ISR_DIR BIT(16) 147 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 148 149 /* Bit definition for I2C_ICR register */ 150 #define I2C_ICR_ADDRCF BIT(3) 151 #define I2C_ICR_NACKCF BIT(4) 152 #define I2C_ICR_STOPCF BIT(5) 153 #define I2C_ICR_BERRCF BIT(8) 154 #define I2C_ICR_ARLOCF BIT(9) 155 #define I2C_ICR_OVRCF BIT(10) 156 #define I2C_ICR_PECCF BIT(11) 157 #define I2C_ICR_TIMOUTCF BIT(12) 158 #define I2C_ICR_ALERTCF BIT(13) 159 160 /* Max data size for a single I2C transfer */ 161 #define MAX_NBYTE_SIZE 255U 162 163 #define I2C_NSEC_PER_SEC 1000000000UL 164 #define I2C_TIMEOUT_BUSY_MS 25 165 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 166 #define I2C_TIMEOUT_RXNE_MS 5 167 168 #define I2C_TIMEOUT_DEFAULT_MS 100 169 170 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 171 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 172 I2C_CR2_RD_WRN) 173 174 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 175 I2C_TIMINGR_SDADEL | \ 176 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 177 178 /* 179 * I2C transfer modes 180 * I2C_RELOAD: Enable Reload mode 181 * I2C_AUTOEND_MODE: Enable automatic end mode 182 * I2C_SOFTEND_MODE: Enable software end mode 183 */ 184 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 185 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 186 #define I2C_SOFTEND_MODE 0x0 187 188 /* 189 * Start/restart/stop I2C transfer requests. 190 * 191 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 192 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 193 * I2C_GENERATE_START_READ: Generate Restart for read request. 194 * I2C_GENERATE_START_WRITE: Generate Restart for write request 195 */ 196 #define I2C_NO_STARTSTOP 0x0 197 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 198 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 199 I2C_CR2_RD_WRN) 200 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 201 202 /* Memory address byte sizes */ 203 #define I2C_MEMADD_SIZE_8BIT 1 204 #define I2C_MEMADD_SIZE_16BIT 2 205 206 /* Effective rate cannot be lower than 80% target rate */ 207 #define RATE_MIN(rate) (((rate) * 80U) / 100U) 208 209 /* 210 * struct i2c_spec_s - Private I2C timing specifications. 211 * @rate: I2C bus speed (Hz) 212 * @fall_max: Max fall time of both SDA and SCL signals (ns) 213 * @rise_max: Max rise time of both SDA and SCL signals (ns) 214 * @hddat_min: Min data hold time (ns) 215 * @vddat_max: Max data valid time (ns) 216 * @sudat_min: Min data setup time (ns) 217 * @l_min: Min low period of the SCL clock (ns) 218 * @h_min: Min high period of the SCL clock (ns) 219 */ 220 struct i2c_spec_s { 221 uint32_t rate; 222 uint32_t fall_max; 223 uint32_t rise_max; 224 uint32_t hddat_min; 225 uint32_t vddat_max; 226 uint32_t sudat_min; 227 uint32_t l_min; 228 uint32_t h_min; 229 }; 230 231 /* 232 * struct i2c_timing_s - Private I2C output parameters. 233 * @scldel: Data setup time 234 * @sdadel: Data hold time 235 * @sclh: SCL high period (master mode) 236 * @sclh: SCL low period (master mode) 237 * @is_saved: True if relating to a configuration candidate 238 */ 239 struct i2c_timing_s { 240 uint8_t scldel; 241 uint8_t sdadel; 242 uint8_t sclh; 243 uint8_t scll; 244 bool is_saved; 245 }; 246 247 /* This table must be sorted in increasing value for field @rate */ 248 static const struct i2c_spec_s i2c_specs[] = { 249 /* Standard - 100KHz */ 250 { 251 .rate = I2C_STANDARD_RATE, 252 .fall_max = 300, 253 .rise_max = 1000, 254 .hddat_min = 0, 255 .vddat_max = 3450, 256 .sudat_min = 250, 257 .l_min = 4700, 258 .h_min = 4000, 259 }, 260 /* Fast - 400KHz */ 261 { 262 .rate = I2C_FAST_RATE, 263 .fall_max = 300, 264 .rise_max = 300, 265 .hddat_min = 0, 266 .vddat_max = 900, 267 .sudat_min = 100, 268 .l_min = 1300, 269 .h_min = 600, 270 }, 271 /* FastPlus - 1MHz */ 272 { 273 .rate = I2C_FAST_PLUS_RATE, 274 .fall_max = 100, 275 .rise_max = 120, 276 .hddat_min = 0, 277 .vddat_max = 450, 278 .sudat_min = 50, 279 .l_min = 500, 280 .h_min = 260, 281 }, 282 }; 283 284 /* 285 * I2C request parameters 286 * @dev_addr: I2C address of the target device 287 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 288 * @mem_addr: Target memory cell accessed in device (memory mode) 289 * @mem_addr_size: Byte size of the memory cell address (memory mode) 290 * @timeout_ms: Timeout in millisenconds for the request 291 */ 292 struct i2c_request { 293 uint32_t dev_addr; 294 enum i2c_mode_e mode; 295 uint32_t mem_addr; 296 uint32_t mem_addr_size; 297 unsigned int timeout_ms; 298 }; 299 300 /* Place holder for STM32MP15 non-secure I2C bus compat data */ 301 static const int non_secure_bus; 302 303 static vaddr_t get_base(struct i2c_handle_s *hi2c) 304 { 305 return io_pa_or_va_secure(&hi2c->base, hi2c->reg_size); 306 } 307 308 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 309 { 310 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 311 hi2c->i2c_state = I2C_STATE_READY; 312 } 313 314 static const struct i2c_spec_s *get_specs(uint32_t rate) 315 { 316 size_t i = 0; 317 318 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++) 319 if (rate <= i2c_specs[i].rate) 320 return i2c_specs + i; 321 322 return NULL; 323 } 324 325 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 326 { 327 vaddr_t base = get_base(hi2c); 328 329 clk_enable(hi2c->clock); 330 331 cfg->cr1 = io_read32(base + I2C_CR1); 332 cfg->cr2 = io_read32(base + I2C_CR2); 333 cfg->oar1 = io_read32(base + I2C_OAR1); 334 cfg->oar2 = io_read32(base + I2C_OAR2); 335 cfg->timingr = io_read32(base + I2C_TIMINGR); 336 337 clk_disable(hi2c->clock); 338 } 339 340 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 341 { 342 vaddr_t base = get_base(hi2c); 343 344 clk_enable(hi2c->clock); 345 346 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 347 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 348 io_write32(base + I2C_OAR1, cfg->oar1); 349 io_write32(base + I2C_CR2, cfg->cr2); 350 io_write32(base + I2C_OAR2, cfg->oar2); 351 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 352 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 353 354 clk_disable(hi2c->clock); 355 } 356 357 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 358 { 359 DMSG("CR1: %#"PRIx32, cfg->cr1); 360 DMSG("CR2: %#"PRIx32, cfg->cr2); 361 DMSG("OAR1: %#"PRIx32, cfg->oar1); 362 DMSG("OAR2: %#"PRIx32, cfg->oar2); 363 DMSG("TIM: %#"PRIx32, cfg->timingr); 364 } 365 366 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 367 { 368 vaddr_t __maybe_unused base = get_base(hi2c); 369 370 clk_enable(hi2c->clock); 371 372 DMSG("CR1: %#"PRIx32, io_read32(base + I2C_CR1)); 373 DMSG("CR2: %#"PRIx32, io_read32(base + I2C_CR2)); 374 DMSG("OAR1: %#"PRIx32, io_read32(base + I2C_OAR1)); 375 DMSG("OAR2: %#"PRIx32, io_read32(base + I2C_OAR2)); 376 DMSG("TIM: %#"PRIx32, io_read32(base + I2C_TIMINGR)); 377 378 clk_disable(hi2c->clock); 379 } 380 381 /* 382 * Compute the I2C device timings 383 * 384 * @init: Ref to the initialization configuration structure 385 * @clock_src: I2C clock source frequency (Hz) 386 * @timing: Pointer to the final computed timing result 387 * Return 0 on success or a negative value 388 */ 389 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 390 unsigned long clock_src, uint32_t *timing) 391 { 392 const struct i2c_spec_s *specs = NULL; 393 uint32_t speed_freq = 0; 394 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 395 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 396 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 397 uint32_t af_delay_min = 0; 398 uint32_t af_delay_max = 0; 399 uint32_t dnf_delay = 0; 400 uint32_t tsync = 0; 401 uint32_t clk_min = 0; 402 uint32_t clk_max = 0; 403 int clk_error_prev = 0; 404 uint16_t p = 0; 405 uint16_t l = 0; 406 uint16_t a = 0; 407 uint16_t h = 0; 408 unsigned int sdadel_min = 0; 409 unsigned int sdadel_max = 0; 410 unsigned int scldel_min = 0; 411 unsigned int delay = 0; 412 int s = -1; 413 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 414 415 specs = get_specs(init->bus_rate); 416 if (!specs) { 417 DMSG("I2C speed out of bound: %"PRId32"Hz", init->bus_rate); 418 return -1; 419 } 420 421 speed_freq = specs->rate; 422 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 423 clk_error_prev = INT_MAX; 424 425 if (init->rise_time > specs->rise_max || 426 init->fall_time > specs->fall_max) { 427 DMSG("I2C rise{%"PRId32">%"PRId32"}/fall{%"PRId32">%"PRId32"}", 428 init->rise_time, specs->rise_max, 429 init->fall_time, specs->fall_max); 430 return -1; 431 } 432 433 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 434 DMSG("DNF out of bound %"PRId8"/%d", 435 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 436 return -1; 437 } 438 439 /* Analog and Digital Filters */ 440 if (init->analog_filter) { 441 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 442 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 443 } 444 dnf_delay = init->digital_filter_coef * i2cclk; 445 446 sdadel_min = specs->hddat_min + init->fall_time; 447 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 448 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 449 sdadel_min = 0; 450 451 sdadel_max = specs->vddat_max - init->rise_time; 452 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 453 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 454 sdadel_max = 0; 455 456 scldel_min = init->rise_time + specs->sudat_min; 457 458 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 459 sdadel_min, sdadel_max, scldel_min); 460 461 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 462 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 463 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 464 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 465 466 if (scldel < scldel_min) 467 continue; 468 469 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 470 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 471 472 if ((sdadel >= sdadel_min) && 473 (sdadel <= sdadel_max) && 474 (p != p_prev)) { 475 solutions[p].scldel = l; 476 solutions[p].sdadel = a; 477 solutions[p].is_saved = true; 478 p_prev = p; 479 break; 480 } 481 } 482 483 if (p_prev == p) 484 break; 485 } 486 } 487 488 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 489 DMSG("I2C no Prescaler solution"); 490 return -1; 491 } 492 493 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 494 clk_max = I2C_NSEC_PER_SEC / RATE_MIN(specs->rate); 495 clk_min = I2C_NSEC_PER_SEC / specs->rate; 496 497 /* 498 * Among prescaler possibilities discovered above figures out SCL Low 499 * and High Period. Provided: 500 * - SCL Low Period has to be higher than Low Period of the SCL Clock 501 * defined by I2C Specification. I2C Clock has to be lower than 502 * (SCL Low Period - Analog/Digital filters) / 4. 503 * - SCL High Period has to be lower than High Period of the SCL Clock 504 * defined by I2C Specification. 505 * - I2C Clock has to be lower than SCL High Period. 506 */ 507 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 508 uint32_t prescaler = (p + 1) * i2cclk; 509 510 if (!solutions[p].is_saved) 511 continue; 512 513 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 514 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 515 516 if (tscl_l < specs->l_min || 517 i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4)) 518 continue; 519 520 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 521 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 522 uint32_t tscl = tscl_l + tscl_h + 523 init->rise_time + 524 init->fall_time; 525 526 if (tscl >= clk_min && tscl <= clk_max && 527 tscl_h >= specs->h_min && i2cclk < tscl_h) { 528 int clk_error = tscl - i2cbus; 529 530 if (clk_error < 0) 531 clk_error = -clk_error; 532 533 if (clk_error < clk_error_prev) { 534 clk_error_prev = clk_error; 535 solutions[p].scll = l; 536 solutions[p].sclh = h; 537 s = p; 538 } 539 } 540 } 541 } 542 } 543 544 if (s < 0) { 545 DMSG("I2C no solution at all"); 546 return -1; 547 } 548 549 /* Finalize timing settings */ 550 *timing = I2C_SET_TIMINGR_PRESC(s) | 551 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 552 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 553 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 554 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 555 556 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%"PRIu8"/%"PRIu8, 557 s, solutions[s].scldel, solutions[s].sdadel); 558 DMSG("I2C TIMINGR (SCLH/SCLL): %"PRIu8"/%"PRIu8, 559 solutions[s].sclh, solutions[s].scll); 560 DMSG("I2C TIMINGR: 0x%"PRIx32, *timing); 561 562 return 0; 563 } 564 565 /* i2c_specs[] must be sorted by increasing rate */ 566 static bool __maybe_unused i2c_specs_is_consistent(void) 567 { 568 size_t i = 0; 569 570 COMPILE_TIME_ASSERT(ARRAY_SIZE(i2c_specs)); 571 572 for (i = 1; i < ARRAY_SIZE(i2c_specs); i++) 573 if (i2c_specs[i - 1].rate >= i2c_specs[i].rate) 574 return false; 575 576 return true; 577 } 578 579 /* 580 * @brief From requested rate, get the closest I2C rate without exceeding it, 581 * within I2C specification values defined in @i2c_specs. 582 * @param rate: The requested rate. 583 * @retval Found rate, else the lowest value supported by platform. 584 */ 585 static uint32_t get_lower_rate(uint32_t rate) 586 { 587 size_t i = 0; 588 589 for (i = ARRAY_SIZE(i2c_specs); i > 0; i--) 590 if (rate > i2c_specs[i - 1].rate) 591 return i2c_specs[i - 1].rate; 592 593 return i2c_specs[0].rate; 594 } 595 596 /* 597 * Setup the I2C device timings 598 * 599 * @hi2c: I2C handle structure 600 * @init: Ref to the initialization configuration structure 601 * @timing: Output TIMINGR register configuration value 602 * @retval 0 if OK, negative value else 603 */ 604 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 605 struct stm32_i2c_init_s *init, 606 uint32_t *timing) 607 { 608 int rc = 0; 609 unsigned long clock_src = 0; 610 611 assert(i2c_specs_is_consistent()); 612 613 clock_src = clk_get_rate(hi2c->clock); 614 if (!clock_src) { 615 DMSG("Null I2C clock rate"); 616 return -1; 617 } 618 619 /* 620 * If the timing has already been computed, and the frequency is the 621 * same as when it was computed, then use the saved timing. 622 */ 623 if (clock_src == hi2c->saved_frequency) { 624 *timing = hi2c->saved_timing; 625 return 0; 626 } 627 628 do { 629 rc = i2c_compute_timing(init, clock_src, timing); 630 if (rc) { 631 DMSG("Failed to compute I2C timings"); 632 if (init->bus_rate > I2C_STANDARD_RATE) { 633 init->bus_rate = get_lower_rate(init->bus_rate); 634 IMSG("Downgrade I2C speed to %"PRIu32"Hz)", 635 init->bus_rate); 636 } else { 637 break; 638 } 639 } 640 } while (rc); 641 642 if (rc) { 643 DMSG("Impossible to compute I2C timings"); 644 return rc; 645 } 646 647 DMSG("I2C Freq(%"PRIu32"Hz), Clk Source(%lu)", 648 init->bus_rate, clock_src); 649 DMSG("I2C Rise(%"PRId32") and Fall(%"PRId32") Time", 650 init->rise_time, init->fall_time); 651 DMSG("I2C Analog Filter(%s), DNF(%"PRIu8")", 652 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 653 654 hi2c->saved_timing = *timing; 655 hi2c->saved_frequency = clock_src; 656 657 return 0; 658 } 659 660 /* 661 * Configure I2C Analog noise filter. 662 * @hi2c: I2C handle structure 663 * @analog_filter_on: True if enabling analog filter, false otherwise 664 */ 665 static void i2c_config_analog_filter(struct i2c_handle_s *hi2c, 666 bool analog_filter_on) 667 { 668 vaddr_t base = get_base(hi2c); 669 670 /* Disable the selected I2C peripheral */ 671 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 672 673 /* Reset I2Cx ANOFF bit */ 674 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 675 676 /* Set analog filter bit if filter is disabled */ 677 if (!analog_filter_on) 678 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 679 680 /* Enable the selected I2C peripheral */ 681 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 682 } 683 684 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 685 struct stm32_i2c_init_s *init, 686 struct pinctrl_state **pinctrl, 687 struct pinctrl_state **pinctrl_sleep) 688 { 689 TEE_Result res = TEE_ERROR_GENERIC; 690 const fdt32_t *cuint = NULL; 691 struct dt_node_info info = { .status = 0 }; 692 int __maybe_unused count = 0; 693 694 /* Default STM32 specific configs caller may need to overwrite */ 695 memset(init, 0, sizeof(*init)); 696 697 fdt_fill_device_info(fdt, &info, node); 698 assert(info.reg != DT_INFO_INVALID_REG && 699 info.reg_size != DT_INFO_INVALID_REG_SIZE); 700 701 init->pbase = info.reg; 702 init->reg_size = info.reg_size; 703 704 res = clk_dt_get_by_index(fdt, node, 0, &init->clock); 705 if (res) 706 return res; 707 708 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 709 if (cuint) 710 init->rise_time = fdt32_to_cpu(*cuint); 711 else 712 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 713 714 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 715 if (cuint) 716 init->fall_time = fdt32_to_cpu(*cuint); 717 else 718 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 719 720 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 721 if (cuint) { 722 init->bus_rate = fdt32_to_cpu(*cuint); 723 724 if (init->bus_rate > I2C_FAST_PLUS_RATE) { 725 DMSG("Invalid bus speed (%"PRIu32" > %i)", 726 init->bus_rate, I2C_FAST_PLUS_RATE); 727 return TEE_ERROR_GENERIC; 728 } 729 } else { 730 init->bus_rate = I2C_STANDARD_RATE; 731 } 732 733 if (pinctrl) { 734 res = pinctrl_get_state_by_name(fdt, node, "default", pinctrl); 735 if (res) 736 return res; 737 } 738 739 if (pinctrl_sleep) { 740 res = pinctrl_get_state_by_name(fdt, node, "sleep", 741 pinctrl_sleep); 742 if (res == TEE_ERROR_ITEM_NOT_FOUND) 743 res = TEE_SUCCESS; 744 if (res) 745 return res; 746 } 747 748 return TEE_SUCCESS; 749 } 750 751 int stm32_i2c_init(struct i2c_handle_s *hi2c, 752 struct stm32_i2c_init_s *init_data) 753 { 754 int rc = 0; 755 uint32_t timing = 0; 756 vaddr_t base = 0; 757 uint32_t val = 0; 758 759 mutex_pm_aware_init(&hi2c->mu); 760 761 rc = i2c_setup_timing(hi2c, init_data, &timing); 762 if (rc) 763 return rc; 764 765 clk_enable(hi2c->clock); 766 767 base = get_base(hi2c); 768 hi2c->i2c_state = I2C_STATE_BUSY; 769 770 /* Disable the selected I2C peripheral */ 771 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 772 773 /* Configure I2Cx: Frequency range */ 774 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 775 776 /* Disable Own Address1 before set the Own Address1 configuration */ 777 io_write32(base + I2C_OAR1, 0); 778 779 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 780 if (init_data->addr_mode_10b_not_7b) 781 io_write32(base + I2C_OAR1, 782 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 783 init_data->own_address1); 784 else 785 io_write32(base + I2C_OAR1, 786 I2C_OAR1_OA1EN | init_data->own_address1); 787 788 /* Configure I2Cx: Addressing Master mode */ 789 io_write32(base + I2C_CR2, 0); 790 if (init_data->addr_mode_10b_not_7b) 791 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 792 793 /* 794 * Enable the AUTOEND by default, and enable NACK 795 * (should be disabled only during Slave process). 796 */ 797 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 798 799 /* Disable Own Address2 before set the Own Address2 configuration */ 800 io_write32(base + I2C_OAR2, 0); 801 802 /* Configure I2Cx: Dual mode and Own Address2 */ 803 if (init_data->dual_address_mode) 804 io_write32(base + I2C_OAR2, 805 I2C_OAR2_OA2EN | init_data->own_address2 | 806 (init_data->own_address2_masks << 8)); 807 808 /* Configure I2Cx: Generalcall and NoStretch mode */ 809 val = 0; 810 if (init_data->general_call_mode) 811 val |= I2C_CR1_GCEN; 812 if (init_data->no_stretch_mode) 813 val |= I2C_CR1_NOSTRETCH; 814 io_write32(base + I2C_CR1, val); 815 816 /* Enable the selected I2C peripheral */ 817 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 818 819 hi2c->i2c_err = I2C_ERROR_NONE; 820 hi2c->i2c_state = I2C_STATE_READY; 821 822 i2c_config_analog_filter(hi2c, init_data->analog_filter); 823 824 clk_disable(hi2c->clock); 825 826 if (hi2c->pinctrl && pinctrl_apply_state(hi2c->pinctrl)) 827 return -1; 828 829 return 0; 830 } 831 832 /* I2C transmit (TX) data register flush sequence */ 833 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 834 { 835 vaddr_t base = get_base(hi2c); 836 837 /* 838 * If a pending TXIS flag is set, 839 * write a dummy data in TXDR to clear it. 840 */ 841 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 842 io_write32(base + I2C_TXDR, 0); 843 844 /* Flush TX register if not empty */ 845 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 846 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 847 } 848 849 /* 850 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 851 * 852 * @hi2c: I2C handle structure 853 * @bit_mask: Bit mask for the target single bit position to consider 854 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 855 * @timeout_ref: Expriation timeout reference 856 * Return 0 on success and a non-zero value on timeout 857 */ 858 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 859 unsigned int awaited_value, uint64_t timeout_ref) 860 { 861 vaddr_t isr = get_base(hi2c) + I2C_ISR; 862 863 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 864 865 /* May timeout while TEE thread is suspended */ 866 while (!timeout_elapsed(timeout_ref)) 867 if (!!(io_read32(isr) & bit_mask) == awaited_value) 868 break; 869 870 if (!!(io_read32(isr) & bit_mask) == awaited_value) 871 return 0; 872 873 notif_i2c_timeout(hi2c); 874 return -1; 875 } 876 877 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 878 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 879 { 880 vaddr_t base = get_base(hi2c); 881 882 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 883 return 0; 884 885 /* 886 * Wait until STOP Flag is reset. Use polling method. 887 * AutoEnd should be initiate after AF. 888 * Timeout may elpased while TEE thread is suspended. 889 */ 890 while (!timeout_elapsed(timeout_ref)) 891 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 892 break; 893 894 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 895 notif_i2c_timeout(hi2c); 896 return -1; 897 } 898 899 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 900 901 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 902 903 i2c_flush_txdr(hi2c); 904 905 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 906 907 hi2c->i2c_err |= I2C_ERROR_ACKF; 908 hi2c->i2c_state = I2C_STATE_READY; 909 910 return -1; 911 } 912 913 /* Wait TXIS bit is 1 in I2C_ISR register */ 914 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 915 { 916 while (!timeout_elapsed(timeout_ref)) { 917 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 918 break; 919 if (i2c_ack_failed(hi2c, timeout_ref)) 920 return -1; 921 } 922 923 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 924 return 0; 925 926 if (i2c_ack_failed(hi2c, timeout_ref)) 927 return -1; 928 929 notif_i2c_timeout(hi2c); 930 return -1; 931 } 932 933 /* Wait STOPF bit is 1 in I2C_ISR register */ 934 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 935 { 936 while (!timeout_elapsed(timeout_ref)) { 937 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 938 break; 939 940 if (i2c_ack_failed(hi2c, timeout_ref)) 941 return -1; 942 } 943 944 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 945 return 0; 946 947 if (i2c_ack_failed(hi2c, timeout_ref)) 948 return -1; 949 950 notif_i2c_timeout(hi2c); 951 return -1; 952 } 953 954 /* 955 * Load I2C_CR2 register for a I2C transfer 956 * 957 * @hi2c: I2C handle structure 958 * @dev_addr: Slave address to be transferred 959 * @size: Number of bytes to be transferred 960 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 961 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 962 * I2C_GENERATE_START_{READ|WRITE} 963 */ 964 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 965 uint32_t size, uint32_t i2c_mode, 966 uint32_t startstop) 967 { 968 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 969 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 970 (I2C_CR2_RD_WRN & 971 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 972 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 973 ((size << I2C_CR2_NBYTES_OFFSET) & 974 I2C_CR2_NBYTES) | 975 i2c_mode | startstop; 976 977 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 978 } 979 980 /* 981 * Master sends target device address followed by internal memory 982 * address for a memory write request. 983 * Function returns 0 on success or a negative value. 984 */ 985 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 986 struct i2c_request *request, 987 uint64_t timeout_ref) 988 { 989 vaddr_t base = get_base(hi2c); 990 991 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 992 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 993 994 if (i2c_wait_txis(hi2c, timeout_ref)) 995 return -1; 996 997 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 998 /* Send memory address */ 999 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1000 } else { 1001 /* Send MSB of memory address */ 1002 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1003 1004 if (i2c_wait_txis(hi2c, timeout_ref)) 1005 return -1; 1006 1007 /* Send LSB of memory address */ 1008 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1009 } 1010 1011 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1012 return -1; 1013 1014 return 0; 1015 } 1016 1017 /* 1018 * Master sends target device address followed by internal memory 1019 * address to prepare a memory read request. 1020 * Function returns 0 on success or a negative value. 1021 */ 1022 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 1023 struct i2c_request *request, 1024 uint64_t timeout_ref) 1025 { 1026 vaddr_t base = get_base(hi2c); 1027 1028 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 1029 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 1030 1031 if (i2c_wait_txis(hi2c, timeout_ref)) 1032 return -1; 1033 1034 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 1035 /* Send memory address */ 1036 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1037 } else { 1038 /* Send MSB of memory address */ 1039 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1040 1041 if (i2c_wait_txis(hi2c, timeout_ref)) 1042 return -1; 1043 1044 /* Send LSB of memory address */ 1045 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1046 } 1047 1048 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1049 return -1; 1050 1051 return 0; 1052 } 1053 1054 /* 1055 * Write an amount of data in blocking mode 1056 * 1057 * @hi2c: Reference to struct i2c_handle_s 1058 * @request: I2C request parameters 1059 * @p_data: Pointer to data buffer 1060 * @size: Amount of data to be sent 1061 * Return 0 on success or a negative value 1062 */ 1063 static int do_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1064 uint8_t *p_data, uint16_t size) 1065 { 1066 uint64_t timeout_ref = 0; 1067 vaddr_t base = get_base(hi2c); 1068 int rc = -1; 1069 uint8_t *p_buff = p_data; 1070 size_t xfer_size = 0; 1071 size_t xfer_count = size; 1072 1073 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1074 return -1; 1075 1076 if (!p_data || !size) 1077 return -1; 1078 1079 mutex_pm_aware_lock(&hi2c->mu); 1080 1081 if (hi2c->i2c_state != I2C_STATE_READY) { 1082 mutex_pm_aware_unlock(&hi2c->mu); 1083 return -1; 1084 } 1085 1086 clk_enable(hi2c->clock); 1087 1088 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1089 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1090 goto bail; 1091 1092 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1093 hi2c->i2c_err = I2C_ERROR_NONE; 1094 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1095 1096 if (request->mode == I2C_MODE_MEM) { 1097 /* In memory mode, send slave address and memory address */ 1098 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1099 goto bail; 1100 1101 if (xfer_count > MAX_NBYTE_SIZE) { 1102 xfer_size = MAX_NBYTE_SIZE; 1103 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1104 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1105 } else { 1106 xfer_size = xfer_count; 1107 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1108 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1109 } 1110 } else { 1111 /* In master mode, send slave address */ 1112 if (xfer_count > MAX_NBYTE_SIZE) { 1113 xfer_size = MAX_NBYTE_SIZE; 1114 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1115 I2C_RELOAD_MODE, 1116 I2C_GENERATE_START_WRITE); 1117 } else { 1118 xfer_size = xfer_count; 1119 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1120 I2C_AUTOEND_MODE, 1121 I2C_GENERATE_START_WRITE); 1122 } 1123 } 1124 1125 do { 1126 if (i2c_wait_txis(hi2c, timeout_ref)) 1127 goto bail; 1128 1129 io_write8(base + I2C_TXDR, *p_buff); 1130 p_buff++; 1131 xfer_count--; 1132 xfer_size--; 1133 1134 if (xfer_count && !xfer_size) { 1135 /* Wait until TCR flag is set */ 1136 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1137 goto bail; 1138 1139 if (xfer_count > MAX_NBYTE_SIZE) { 1140 xfer_size = MAX_NBYTE_SIZE; 1141 i2c_transfer_config(hi2c, request->dev_addr, 1142 xfer_size, 1143 I2C_RELOAD_MODE, 1144 I2C_NO_STARTSTOP); 1145 } else { 1146 xfer_size = xfer_count; 1147 i2c_transfer_config(hi2c, request->dev_addr, 1148 xfer_size, 1149 I2C_AUTOEND_MODE, 1150 I2C_NO_STARTSTOP); 1151 } 1152 } 1153 1154 } while (xfer_count > 0U); 1155 1156 /* 1157 * No need to Check TC flag, with AUTOEND mode the stop 1158 * is automatically generated. 1159 * Wait until STOPF flag is reset. 1160 */ 1161 if (i2c_wait_stop(hi2c, timeout_ref)) 1162 goto bail; 1163 1164 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1165 1166 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1167 1168 hi2c->i2c_state = I2C_STATE_READY; 1169 1170 rc = 0; 1171 1172 bail: 1173 clk_disable(hi2c->clock); 1174 mutex_pm_aware_unlock(&hi2c->mu); 1175 1176 return rc; 1177 } 1178 1179 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1180 uint32_t mem_addr, uint32_t mem_addr_size, 1181 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1182 { 1183 struct i2c_request request = { 1184 .dev_addr = dev_addr, 1185 .mode = I2C_MODE_MEM, 1186 .mem_addr = mem_addr, 1187 .mem_addr_size = mem_addr_size, 1188 .timeout_ms = timeout_ms, 1189 }; 1190 1191 return do_write(hi2c, &request, p_data, size); 1192 } 1193 1194 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1195 uint8_t *p_data, size_t size, 1196 unsigned int timeout_ms) 1197 { 1198 struct i2c_request request = { 1199 .dev_addr = dev_addr, 1200 .mode = I2C_MODE_MASTER, 1201 .timeout_ms = timeout_ms, 1202 }; 1203 1204 return do_write(hi2c, &request, p_data, size); 1205 } 1206 1207 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1208 unsigned int mem_addr, uint8_t *p_data, 1209 bool write) 1210 { 1211 uint64_t timeout_ref = 0; 1212 uintptr_t base = get_base(hi2c); 1213 int rc = -1; 1214 uint8_t *p_buff = p_data; 1215 uint32_t event_mask = 0; 1216 1217 mutex_pm_aware_lock(&hi2c->mu); 1218 1219 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) { 1220 mutex_pm_aware_unlock(&hi2c->mu); 1221 return -1; 1222 } 1223 1224 clk_enable(hi2c->clock); 1225 1226 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1227 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1228 goto bail; 1229 1230 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1231 hi2c->i2c_err = I2C_ERROR_NONE; 1232 1233 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1234 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1235 I2C_GENERATE_START_WRITE); 1236 1237 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1238 if (i2c_wait_txis(hi2c, timeout_ref)) 1239 goto bail; 1240 1241 io_write8(base + I2C_TXDR, mem_addr); 1242 1243 if (write) 1244 event_mask = I2C_ISR_TCR; 1245 else 1246 event_mask = I2C_ISR_TC; 1247 1248 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1249 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1250 goto bail; 1251 1252 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1253 I2C_AUTOEND_MODE, 1254 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1255 1256 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1257 if (write) { 1258 if (i2c_wait_txis(hi2c, timeout_ref)) 1259 goto bail; 1260 1261 io_write8(base + I2C_TXDR, *p_buff); 1262 } else { 1263 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1264 goto bail; 1265 1266 *p_buff = io_read8(base + I2C_RXDR); 1267 } 1268 1269 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1270 if (i2c_wait_stop(hi2c, timeout_ref)) 1271 goto bail; 1272 1273 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1274 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1275 1276 hi2c->i2c_state = I2C_STATE_READY; 1277 1278 rc = 0; 1279 1280 bail: 1281 clk_disable(hi2c->clock); 1282 mutex_pm_aware_unlock(&hi2c->mu); 1283 1284 return rc; 1285 } 1286 1287 /* 1288 * Read an amount of data in blocking mode 1289 * 1290 * @hi2c: Reference to struct i2c_handle_s 1291 * @request: I2C request parameters 1292 * @p_data: Pointer to data buffer 1293 * @size: Amount of data to be sent 1294 * Return 0 on success or a negative value 1295 */ 1296 static int do_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1297 uint8_t *p_data, uint32_t size) 1298 { 1299 vaddr_t base = get_base(hi2c); 1300 uint64_t timeout_ref = 0; 1301 int rc = -1; 1302 uint8_t *p_buff = p_data; 1303 size_t xfer_count = size; 1304 size_t xfer_size = 0; 1305 1306 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1307 return -1; 1308 1309 if (!p_data || !size) 1310 return -1; 1311 1312 mutex_pm_aware_lock(&hi2c->mu); 1313 1314 if (hi2c->i2c_state != I2C_STATE_READY) { 1315 mutex_pm_aware_unlock(&hi2c->mu); 1316 return -1; 1317 } 1318 1319 clk_enable(hi2c->clock); 1320 1321 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1322 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1323 goto bail; 1324 1325 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1326 hi2c->i2c_err = I2C_ERROR_NONE; 1327 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1328 1329 if (request->mode == I2C_MODE_MEM) { 1330 /* Send memory address */ 1331 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1332 goto bail; 1333 } 1334 1335 /* 1336 * Send slave address. 1337 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1338 * and generate RESTART. 1339 */ 1340 if (xfer_count > MAX_NBYTE_SIZE) { 1341 xfer_size = MAX_NBYTE_SIZE; 1342 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1343 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1344 } else { 1345 xfer_size = xfer_count; 1346 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1347 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1348 } 1349 1350 do { 1351 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, 1352 timeout_init_us(I2C_TIMEOUT_RXNE_MS * 1000))) 1353 goto bail; 1354 1355 *p_buff = io_read8(base + I2C_RXDR); 1356 p_buff++; 1357 xfer_size--; 1358 xfer_count--; 1359 1360 if (xfer_count && !xfer_size) { 1361 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1362 goto bail; 1363 1364 if (xfer_count > MAX_NBYTE_SIZE) { 1365 xfer_size = MAX_NBYTE_SIZE; 1366 i2c_transfer_config(hi2c, request->dev_addr, 1367 xfer_size, 1368 I2C_RELOAD_MODE, 1369 I2C_NO_STARTSTOP); 1370 } else { 1371 xfer_size = xfer_count; 1372 i2c_transfer_config(hi2c, request->dev_addr, 1373 xfer_size, 1374 I2C_AUTOEND_MODE, 1375 I2C_NO_STARTSTOP); 1376 } 1377 } 1378 } while (xfer_count > 0U); 1379 1380 /* 1381 * No need to Check TC flag, with AUTOEND mode the stop 1382 * is automatically generated. 1383 * Wait until STOPF flag is reset. 1384 */ 1385 if (i2c_wait_stop(hi2c, timeout_ref)) 1386 goto bail; 1387 1388 /* Clear the NACK generated at the end of the transfer */ 1389 if ((io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_NACKF)) 1390 io_write32(get_base(hi2c) + I2C_ICR, I2C_ICR_NACKCF); 1391 1392 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1393 1394 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1395 1396 hi2c->i2c_state = I2C_STATE_READY; 1397 1398 rc = 0; 1399 1400 bail: 1401 clk_disable(hi2c->clock); 1402 mutex_pm_aware_unlock(&hi2c->mu); 1403 1404 return rc; 1405 } 1406 1407 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1408 uint32_t mem_addr, uint32_t mem_addr_size, 1409 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1410 { 1411 struct i2c_request request = { 1412 .dev_addr = dev_addr, 1413 .mode = I2C_MODE_MEM, 1414 .mem_addr = mem_addr, 1415 .mem_addr_size = mem_addr_size, 1416 .timeout_ms = timeout_ms, 1417 }; 1418 1419 return do_read(hi2c, &request, p_data, size); 1420 } 1421 1422 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1423 uint8_t *p_data, size_t size, 1424 unsigned int timeout_ms) 1425 { 1426 struct i2c_request request = { 1427 .dev_addr = dev_addr, 1428 .mode = I2C_MODE_MASTER, 1429 .timeout_ms = timeout_ms, 1430 }; 1431 1432 return do_read(hi2c, &request, p_data, size); 1433 } 1434 1435 static struct i2c_handle_s *stm32_i2c_dev_to_handle(struct i2c_dev *i2c_dev) 1436 { 1437 struct stm32_i2c_dev *dev = container_of(i2c_dev, struct stm32_i2c_dev, 1438 i2c_dev); 1439 1440 return dev->handle; 1441 } 1442 1443 static TEE_Result stm32_i2c_read_data(struct i2c_dev *i2c_dev, uint8_t *buf, 1444 size_t len) 1445 { 1446 struct i2c_handle_s *i2c_handle = stm32_i2c_dev_to_handle(i2c_dev); 1447 int rc = 0; 1448 1449 rc = stm32_i2c_master_receive(i2c_handle, i2c_dev->addr, buf, len, 1450 I2C_TIMEOUT_DEFAULT_MS); 1451 if (!rc) 1452 return TEE_SUCCESS; 1453 else 1454 return TEE_ERROR_GENERIC; 1455 } 1456 1457 static TEE_Result stm32_i2c_write_data(struct i2c_dev *i2c_dev, 1458 const uint8_t *buf, size_t len) 1459 { 1460 struct i2c_handle_s *i2c_handle = stm32_i2c_dev_to_handle(i2c_dev); 1461 uint8_t *buf2 = (uint8_t *)buf; 1462 int rc = 0; 1463 1464 rc = stm32_i2c_master_transmit(i2c_handle, i2c_dev->addr, buf2, len, 1465 I2C_TIMEOUT_DEFAULT_MS); 1466 if (!rc) 1467 return TEE_SUCCESS; 1468 else 1469 return TEE_ERROR_GENERIC; 1470 } 1471 1472 static const struct i2c_ctrl_ops stm32_i2c_ops = { 1473 .read = stm32_i2c_read_data, 1474 .write = stm32_i2c_write_data, 1475 }; 1476 1477 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1478 unsigned int trials, unsigned int timeout_ms) 1479 { 1480 vaddr_t base = get_base(hi2c); 1481 unsigned int i2c_trials = 0U; 1482 bool rc = false; 1483 1484 mutex_pm_aware_lock(&hi2c->mu); 1485 1486 if (hi2c->i2c_state != I2C_STATE_READY) { 1487 mutex_pm_aware_unlock(&hi2c->mu); 1488 return rc; 1489 } 1490 1491 clk_enable(hi2c->clock); 1492 1493 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1494 goto bail; 1495 1496 hi2c->i2c_state = I2C_STATE_BUSY; 1497 hi2c->i2c_err = I2C_ERROR_NONE; 1498 1499 do { 1500 uint64_t timeout_ref = 0; 1501 vaddr_t isr = base + I2C_ISR; 1502 1503 /* Generate Start */ 1504 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1505 io_write32(base + I2C_CR2, 1506 ((dev_addr & I2C_CR2_SADD) | 1507 I2C_CR2_START | I2C_CR2_AUTOEND) & 1508 ~I2C_CR2_RD_WRN); 1509 else 1510 io_write32(base + I2C_CR2, 1511 ((dev_addr & I2C_CR2_SADD) | 1512 I2C_CR2_START | I2C_CR2_ADD10) & 1513 ~I2C_CR2_RD_WRN); 1514 1515 /* 1516 * No need to Check TC flag, with AUTOEND mode the stop 1517 * is automatically generated. 1518 * Wait until STOPF flag is set or a NACK flag is set. 1519 */ 1520 timeout_ref = timeout_init_us(timeout_ms * 1000); 1521 while (!timeout_elapsed(timeout_ref)) 1522 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1523 break; 1524 1525 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1526 notif_i2c_timeout(hi2c); 1527 goto bail; 1528 } 1529 1530 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1531 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1532 goto bail; 1533 1534 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1535 1536 hi2c->i2c_state = I2C_STATE_READY; 1537 1538 rc = true; 1539 goto bail; 1540 } 1541 1542 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1543 goto bail; 1544 1545 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1546 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1547 1548 if (i2c_trials == trials) { 1549 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1550 1551 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1552 goto bail; 1553 1554 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1555 } 1556 1557 i2c_trials++; 1558 } while (i2c_trials < trials); 1559 1560 notif_i2c_timeout(hi2c); 1561 1562 bail: 1563 clk_disable(hi2c->clock); 1564 mutex_pm_aware_unlock(&hi2c->mu); 1565 1566 return rc; 1567 } 1568 1569 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1570 { 1571 if (hi2c->i2c_state == I2C_STATE_READY) 1572 return; 1573 1574 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1575 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1576 panic(); 1577 1578 if (pinctrl_apply_state(hi2c->pinctrl)) 1579 panic(); 1580 1581 if (hi2c->i2c_state == I2C_STATE_RESET) { 1582 /* There is no valid I2C configuration to be loaded yet */ 1583 return; 1584 } 1585 1586 restore_cfg(hi2c, &hi2c->sec_cfg); 1587 1588 hi2c->i2c_state = I2C_STATE_READY; 1589 } 1590 1591 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1592 { 1593 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1594 return; 1595 1596 if (hi2c->i2c_state != I2C_STATE_READY) 1597 panic(); 1598 1599 save_cfg(hi2c, &hi2c->sec_cfg); 1600 1601 if (hi2c->pinctrl_sleep && pinctrl_apply_state(hi2c->pinctrl_sleep)) 1602 panic(); 1603 1604 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1605 } 1606 1607 static TEE_Result stm32_get_i2c_dev(struct dt_pargs *args, void *data, 1608 struct i2c_dev **out_device) 1609 { 1610 struct stm32_i2c_dev *stm32_i2c_dev = NULL; 1611 paddr_t addr = 0; 1612 1613 addr = fdt_reg_base_address(args->fdt, args->consumer_node); 1614 if (addr == DT_INFO_INVALID_REG) { 1615 DMSG("Can't get device I2C address"); 1616 return TEE_ERROR_GENERIC; 1617 } 1618 1619 stm32_i2c_dev = calloc(1, sizeof(*stm32_i2c_dev)); 1620 if (!stm32_i2c_dev) 1621 return TEE_ERROR_OUT_OF_MEMORY; 1622 1623 stm32_i2c_dev->handle = data; 1624 stm32_i2c_dev->i2c_dev.addr = addr; 1625 stm32_i2c_dev->i2c_ctrl.ops = &stm32_i2c_ops; 1626 stm32_i2c_dev->i2c_dev.ctrl = &stm32_i2c_dev->i2c_ctrl; 1627 1628 *out_device = &stm32_i2c_dev->i2c_dev; 1629 1630 return TEE_SUCCESS; 1631 } 1632 1633 static TEE_Result stm32_i2c_probe(const void *fdt, int node, 1634 const void *compat_data) 1635 { 1636 TEE_Result res = TEE_SUCCESS; 1637 int subnode = 0; 1638 struct i2c_handle_s *i2c_handle_p = NULL; 1639 struct stm32_i2c_init_s init_data = { }; 1640 struct pinctrl_state *pinctrl_active = NULL; 1641 struct pinctrl_state *pinctrl_idle = NULL; 1642 1643 res = stm32_i2c_get_setup_from_fdt((void *)fdt, node, &init_data, 1644 &pinctrl_active, &pinctrl_idle); 1645 if (res) 1646 return res; 1647 1648 i2c_handle_p = calloc(1, sizeof(struct i2c_handle_s)); 1649 if (!i2c_handle_p) 1650 return TEE_ERROR_OUT_OF_MEMORY; 1651 1652 i2c_handle_p->reg_size = init_data.reg_size; 1653 i2c_handle_p->clock = init_data.clock; 1654 i2c_handle_p->base.pa = init_data.pbase; 1655 i2c_handle_p->base.va = io_pa_or_va(&i2c_handle_p->base, 1656 init_data.reg_size); 1657 assert(i2c_handle_p->base.va); 1658 i2c_handle_p->clock = init_data.clock; 1659 i2c_handle_p->i2c_state = I2C_STATE_RESET; 1660 i2c_handle_p->pinctrl = pinctrl_active; 1661 i2c_handle_p->pinctrl_sleep = pinctrl_idle; 1662 1663 if (compat_data != &non_secure_bus) 1664 i2c_handle_p->i2c_secure = true; 1665 1666 init_data.analog_filter = true; 1667 init_data.digital_filter_coef = 0; 1668 1669 if (stm32_i2c_init(i2c_handle_p, &init_data)) 1670 panic("Couldn't initialise I2C"); 1671 1672 res = i2c_register_provider(fdt, node, stm32_get_i2c_dev, i2c_handle_p); 1673 if (res) 1674 panic("Couldn't register I2C provider"); 1675 1676 fdt_for_each_subnode(subnode, fdt, node) { 1677 res = dt_driver_maybe_add_probe_node(fdt, subnode); 1678 if (res) { 1679 EMSG("Failed on node %s with %#"PRIx32, 1680 fdt_get_name(fdt, subnode, NULL), res); 1681 panic(); 1682 } 1683 } 1684 1685 return res; 1686 } 1687 1688 static const struct dt_device_match stm32_i2c_match_table[] = { 1689 { .compatible = "st,stm32mp15-i2c" }, 1690 { .compatible = "st,stm32mp13-i2c" }, 1691 { 1692 .compatible = "st,stm32mp15-i2c-non-secure", 1693 .compat_data = &non_secure_bus, 1694 }, 1695 { } 1696 }; 1697 1698 DEFINE_DT_DRIVER(stm32_i2c_dt_driver) = { 1699 .name = "stm32_i2c", 1700 .match_table = stm32_i2c_match_table, 1701 .probe = stm32_i2c_probe, 1702 .type = DT_DRIVER_I2C 1703 }; 1704