1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/clk.h> 14 #include <drivers/clk_dt.h> 15 #include <drivers/stm32_i2c.h> 16 #include <io.h> 17 #include <kernel/delay.h> 18 #include <kernel/dt.h> 19 #include <kernel/boot.h> 20 #include <kernel/panic.h> 21 #include <libfdt.h> 22 #include <stdbool.h> 23 #include <stdlib.h> 24 #include <stm32_util.h> 25 #include <trace.h> 26 27 /* STM32 I2C registers offsets */ 28 #define I2C_CR1 0x00U 29 #define I2C_CR2 0x04U 30 #define I2C_OAR1 0x08U 31 #define I2C_OAR2 0x0CU 32 #define I2C_TIMINGR 0x10U 33 #define I2C_TIMEOUTR 0x14U 34 #define I2C_ISR 0x18U 35 #define I2C_ICR 0x1CU 36 #define I2C_PECR 0x20U 37 #define I2C_RXDR 0x24U 38 #define I2C_TXDR 0x28U 39 #define I2C_SIZE 0x2CU 40 41 /* Bit definition for I2C_CR1 register */ 42 #define I2C_CR1_PE BIT(0) 43 #define I2C_CR1_TXIE BIT(1) 44 #define I2C_CR1_RXIE BIT(2) 45 #define I2C_CR1_ADDRIE BIT(3) 46 #define I2C_CR1_NACKIE BIT(4) 47 #define I2C_CR1_STOPIE BIT(5) 48 #define I2C_CR1_TCIE BIT(6) 49 #define I2C_CR1_ERRIE BIT(7) 50 #define I2C_CR1_DNF GENMASK_32(11, 8) 51 #define I2C_CR1_ANFOFF BIT(12) 52 #define I2C_CR1_SWRST BIT(13) 53 #define I2C_CR1_TXDMAEN BIT(14) 54 #define I2C_CR1_RXDMAEN BIT(15) 55 #define I2C_CR1_SBC BIT(16) 56 #define I2C_CR1_NOSTRETCH BIT(17) 57 #define I2C_CR1_WUPEN BIT(18) 58 #define I2C_CR1_GCEN BIT(19) 59 #define I2C_CR1_SMBHEN BIT(22) 60 #define I2C_CR1_SMBDEN BIT(21) 61 #define I2C_CR1_ALERTEN BIT(22) 62 #define I2C_CR1_PECEN BIT(23) 63 64 /* Bit definition for I2C_CR2 register */ 65 #define I2C_CR2_SADD GENMASK_32(9, 0) 66 #define I2C_CR2_RD_WRN BIT(10) 67 #define I2C_CR2_RD_WRN_OFFSET 10U 68 #define I2C_CR2_ADD10 BIT(11) 69 #define I2C_CR2_HEAD10R BIT(12) 70 #define I2C_CR2_START BIT(13) 71 #define I2C_CR2_STOP BIT(14) 72 #define I2C_CR2_NACK BIT(15) 73 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 74 #define I2C_CR2_NBYTES_OFFSET 16U 75 #define I2C_CR2_RELOAD BIT(24) 76 #define I2C_CR2_AUTOEND BIT(25) 77 #define I2C_CR2_PECBYTE BIT(26) 78 79 /* Bit definition for I2C_OAR1 register */ 80 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 81 #define I2C_OAR1_OA1MODE BIT(10) 82 #define I2C_OAR1_OA1EN BIT(15) 83 84 /* Bit definition for I2C_OAR2 register */ 85 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 86 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 87 #define I2C_OAR2_OA2NOMASK 0 88 #define I2C_OAR2_OA2MASK01 BIT(8) 89 #define I2C_OAR2_OA2MASK02 BIT(9) 90 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 91 #define I2C_OAR2_OA2MASK04 BIT(10) 92 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 93 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 94 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 95 #define I2C_OAR2_OA2EN BIT(15) 96 97 /* Bit definition for I2C_TIMINGR register */ 98 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 99 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 100 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 101 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 102 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 103 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 104 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 105 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 106 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 107 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 108 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 109 (I2C_TIMINGR_SCLL_MAX - 1)) 110 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 111 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 112 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 113 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 114 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 115 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 116 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 117 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 118 119 /* Bit definition for I2C_TIMEOUTR register */ 120 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 121 #define I2C_TIMEOUTR_TIDLE BIT(12) 122 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 123 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 124 #define I2C_TIMEOUTR_TEXTEN BIT(31) 125 126 /* Bit definition for I2C_ISR register */ 127 #define I2C_ISR_TXE BIT(0) 128 #define I2C_ISR_TXIS BIT(1) 129 #define I2C_ISR_RXNE BIT(2) 130 #define I2C_ISR_ADDR BIT(3) 131 #define I2C_ISR_NACKF BIT(4) 132 #define I2C_ISR_STOPF BIT(5) 133 #define I2C_ISR_TC BIT(6) 134 #define I2C_ISR_TCR BIT(7) 135 #define I2C_ISR_BERR BIT(8) 136 #define I2C_ISR_ARLO BIT(9) 137 #define I2C_ISR_OVR BIT(10) 138 #define I2C_ISR_PECERR BIT(11) 139 #define I2C_ISR_TIMEOUT BIT(12) 140 #define I2C_ISR_ALERT BIT(13) 141 #define I2C_ISR_BUSY BIT(15) 142 #define I2C_ISR_DIR BIT(16) 143 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 144 145 /* Bit definition for I2C_ICR register */ 146 #define I2C_ICR_ADDRCF BIT(3) 147 #define I2C_ICR_NACKCF BIT(4) 148 #define I2C_ICR_STOPCF BIT(5) 149 #define I2C_ICR_BERRCF BIT(8) 150 #define I2C_ICR_ARLOCF BIT(9) 151 #define I2C_ICR_OVRCF BIT(10) 152 #define I2C_ICR_PECCF BIT(11) 153 #define I2C_ICR_TIMOUTCF BIT(12) 154 #define I2C_ICR_ALERTCF BIT(13) 155 156 /* Max data size for a single I2C transfer */ 157 #define MAX_NBYTE_SIZE 255U 158 159 #define I2C_NSEC_PER_SEC 1000000000UL 160 #define I2C_TIMEOUT_BUSY_MS 25 161 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 162 #define I2C_TIMEOUT_RXNE_MS 5 163 164 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 165 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 166 I2C_CR2_RD_WRN) 167 168 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 169 I2C_TIMINGR_SDADEL | \ 170 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 171 172 /* 173 * I2C transfer modes 174 * I2C_RELOAD: Enable Reload mode 175 * I2C_AUTOEND_MODE: Enable automatic end mode 176 * I2C_SOFTEND_MODE: Enable software end mode 177 */ 178 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 179 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 180 #define I2C_SOFTEND_MODE 0x0 181 182 /* 183 * Start/restart/stop I2C transfer requests. 184 * 185 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 186 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 187 * I2C_GENERATE_START_READ: Generate Restart for read request. 188 * I2C_GENERATE_START_WRITE: Generate Restart for write request 189 */ 190 #define I2C_NO_STARTSTOP 0x0 191 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 192 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 193 I2C_CR2_RD_WRN) 194 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 195 196 /* Memory address byte sizes */ 197 #define I2C_MEMADD_SIZE_8BIT 1 198 #define I2C_MEMADD_SIZE_16BIT 2 199 200 /* Effective rate cannot be lower than 80% target rate */ 201 #define RATE_MIN(rate) (((rate) * 80U) / 100U) 202 203 /* 204 * struct i2c_spec_s - Private I2C timing specifications. 205 * @rate: I2C bus speed (Hz) 206 * @fall_max: Max fall time of both SDA and SCL signals (ns) 207 * @rise_max: Max rise time of both SDA and SCL signals (ns) 208 * @hddat_min: Min data hold time (ns) 209 * @vddat_max: Max data valid time (ns) 210 * @sudat_min: Min data setup time (ns) 211 * @l_min: Min low period of the SCL clock (ns) 212 * @h_min: Min high period of the SCL clock (ns) 213 */ 214 struct i2c_spec_s { 215 uint32_t rate; 216 uint32_t fall_max; 217 uint32_t rise_max; 218 uint32_t hddat_min; 219 uint32_t vddat_max; 220 uint32_t sudat_min; 221 uint32_t l_min; 222 uint32_t h_min; 223 }; 224 225 /* 226 * struct i2c_timing_s - Private I2C output parameters. 227 * @scldel: Data setup time 228 * @sdadel: Data hold time 229 * @sclh: SCL high period (master mode) 230 * @sclh: SCL low period (master mode) 231 * @is_saved: True if relating to a configuration candidate 232 */ 233 struct i2c_timing_s { 234 uint8_t scldel; 235 uint8_t sdadel; 236 uint8_t sclh; 237 uint8_t scll; 238 bool is_saved; 239 }; 240 241 /* This table must be sorted in increasing value for field @rate */ 242 static const struct i2c_spec_s i2c_specs[] = { 243 /* Standard - 100KHz */ 244 { 245 .rate = I2C_STANDARD_RATE, 246 .fall_max = 300, 247 .rise_max = 1000, 248 .hddat_min = 0, 249 .vddat_max = 3450, 250 .sudat_min = 250, 251 .l_min = 4700, 252 .h_min = 4000, 253 }, 254 /* Fast - 400KHz */ 255 { 256 .rate = I2C_FAST_RATE, 257 .fall_max = 300, 258 .rise_max = 300, 259 .hddat_min = 0, 260 .vddat_max = 900, 261 .sudat_min = 100, 262 .l_min = 1300, 263 .h_min = 600, 264 }, 265 /* FastPlus - 1MHz */ 266 { 267 .rate = I2C_FAST_PLUS_RATE, 268 .fall_max = 100, 269 .rise_max = 120, 270 .hddat_min = 0, 271 .vddat_max = 450, 272 .sudat_min = 50, 273 .l_min = 500, 274 .h_min = 260, 275 }, 276 }; 277 278 /* 279 * I2C request parameters 280 * @dev_addr: I2C address of the target device 281 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 282 * @mem_addr: Target memory cell accessed in device (memory mode) 283 * @mem_addr_size: Byte size of the memory cell address (memory mode) 284 * @timeout_ms: Timeout in millisenconds for the request 285 */ 286 struct i2c_request { 287 uint32_t dev_addr; 288 enum i2c_mode_e mode; 289 uint32_t mem_addr; 290 uint32_t mem_addr_size; 291 unsigned int timeout_ms; 292 }; 293 294 static vaddr_t get_base(struct i2c_handle_s *hi2c) 295 { 296 return io_pa_or_va_secure(&hi2c->base, hi2c->reg_size); 297 } 298 299 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 300 { 301 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 302 hi2c->i2c_state = I2C_STATE_READY; 303 } 304 305 static const struct i2c_spec_s *get_specs(uint32_t rate) 306 { 307 size_t i = 0; 308 309 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++) 310 if (rate <= i2c_specs[i].rate) 311 return i2c_specs + i; 312 313 return NULL; 314 } 315 316 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 317 { 318 vaddr_t base = get_base(hi2c); 319 320 clk_enable(hi2c->clock); 321 322 cfg->cr1 = io_read32(base + I2C_CR1); 323 cfg->cr2 = io_read32(base + I2C_CR2); 324 cfg->oar1 = io_read32(base + I2C_OAR1); 325 cfg->oar2 = io_read32(base + I2C_OAR2); 326 cfg->timingr = io_read32(base + I2C_TIMINGR); 327 328 clk_disable(hi2c->clock); 329 } 330 331 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 332 { 333 vaddr_t base = get_base(hi2c); 334 335 clk_enable(hi2c->clock); 336 337 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 338 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 339 io_write32(base + I2C_OAR1, cfg->oar1); 340 io_write32(base + I2C_CR2, cfg->cr2); 341 io_write32(base + I2C_OAR2, cfg->oar2); 342 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 343 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 344 345 clk_disable(hi2c->clock); 346 } 347 348 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 349 { 350 DMSG("CR1: %#"PRIx32, cfg->cr1); 351 DMSG("CR2: %#"PRIx32, cfg->cr2); 352 DMSG("OAR1: %#"PRIx32, cfg->oar1); 353 DMSG("OAR2: %#"PRIx32, cfg->oar2); 354 DMSG("TIM: %#"PRIx32, cfg->timingr); 355 } 356 357 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 358 { 359 vaddr_t __maybe_unused base = get_base(hi2c); 360 361 clk_enable(hi2c->clock); 362 363 DMSG("CR1: %#"PRIx32, io_read32(base + I2C_CR1)); 364 DMSG("CR2: %#"PRIx32, io_read32(base + I2C_CR2)); 365 DMSG("OAR1: %#"PRIx32, io_read32(base + I2C_OAR1)); 366 DMSG("OAR2: %#"PRIx32, io_read32(base + I2C_OAR2)); 367 DMSG("TIM: %#"PRIx32, io_read32(base + I2C_TIMINGR)); 368 369 clk_disable(hi2c->clock); 370 } 371 372 /* 373 * Compute the I2C device timings 374 * 375 * @init: Ref to the initialization configuration structure 376 * @clock_src: I2C clock source frequency (Hz) 377 * @timing: Pointer to the final computed timing result 378 * Return 0 on success or a negative value 379 */ 380 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 381 unsigned long clock_src, uint32_t *timing) 382 { 383 const struct i2c_spec_s *specs = NULL; 384 uint32_t speed_freq = 0; 385 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 386 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 387 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 388 uint32_t af_delay_min = 0; 389 uint32_t af_delay_max = 0; 390 uint32_t dnf_delay = 0; 391 uint32_t tsync = 0; 392 uint32_t clk_min = 0; 393 uint32_t clk_max = 0; 394 int clk_error_prev = 0; 395 uint16_t p = 0; 396 uint16_t l = 0; 397 uint16_t a = 0; 398 uint16_t h = 0; 399 unsigned int sdadel_min = 0; 400 unsigned int sdadel_max = 0; 401 unsigned int scldel_min = 0; 402 unsigned int delay = 0; 403 int s = -1; 404 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 405 406 specs = get_specs(init->bus_rate); 407 if (!specs) { 408 DMSG("I2C speed out of bound: %"PRId32"Hz", init->bus_rate); 409 return -1; 410 } 411 412 speed_freq = specs->rate; 413 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 414 clk_error_prev = INT_MAX; 415 416 if (init->rise_time > specs->rise_max || 417 init->fall_time > specs->fall_max) { 418 DMSG("I2C rise{%"PRId32">%"PRId32"}/fall{%"PRId32">%"PRId32"}", 419 init->rise_time, specs->rise_max, 420 init->fall_time, specs->fall_max); 421 return -1; 422 } 423 424 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 425 DMSG("DNF out of bound %"PRId8"/%d", 426 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 427 return -1; 428 } 429 430 /* Analog and Digital Filters */ 431 if (init->analog_filter) { 432 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 433 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 434 } 435 dnf_delay = init->digital_filter_coef * i2cclk; 436 437 sdadel_min = specs->hddat_min + init->fall_time; 438 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 439 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 440 sdadel_min = 0; 441 442 sdadel_max = specs->vddat_max - init->rise_time; 443 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 444 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 445 sdadel_max = 0; 446 447 scldel_min = init->rise_time + specs->sudat_min; 448 449 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 450 sdadel_min, sdadel_max, scldel_min); 451 452 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 453 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 454 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 455 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 456 457 if (scldel < scldel_min) 458 continue; 459 460 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 461 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 462 463 if ((sdadel >= sdadel_min) && 464 (sdadel <= sdadel_max) && 465 (p != p_prev)) { 466 solutions[p].scldel = l; 467 solutions[p].sdadel = a; 468 solutions[p].is_saved = true; 469 p_prev = p; 470 break; 471 } 472 } 473 474 if (p_prev == p) 475 break; 476 } 477 } 478 479 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 480 DMSG("I2C no Prescaler solution"); 481 return -1; 482 } 483 484 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 485 clk_max = I2C_NSEC_PER_SEC / RATE_MIN(specs->rate); 486 clk_min = I2C_NSEC_PER_SEC / specs->rate; 487 488 /* 489 * Among prescaler possibilities discovered above figures out SCL Low 490 * and High Period. Provided: 491 * - SCL Low Period has to be higher than Low Period of the SCL Clock 492 * defined by I2C Specification. I2C Clock has to be lower than 493 * (SCL Low Period - Analog/Digital filters) / 4. 494 * - SCL High Period has to be lower than High Period of the SCL Clock 495 * defined by I2C Specification. 496 * - I2C Clock has to be lower than SCL High Period. 497 */ 498 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 499 uint32_t prescaler = (p + 1) * i2cclk; 500 501 if (!solutions[p].is_saved) 502 continue; 503 504 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 505 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 506 507 if (tscl_l < specs->l_min || 508 i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4)) 509 continue; 510 511 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 512 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 513 uint32_t tscl = tscl_l + tscl_h + 514 init->rise_time + 515 init->fall_time; 516 517 if (tscl >= clk_min && tscl <= clk_max && 518 tscl_h >= specs->h_min && i2cclk < tscl_h) { 519 int clk_error = tscl - i2cbus; 520 521 if (clk_error < 0) 522 clk_error = -clk_error; 523 524 if (clk_error < clk_error_prev) { 525 clk_error_prev = clk_error; 526 solutions[p].scll = l; 527 solutions[p].sclh = h; 528 s = p; 529 } 530 } 531 } 532 } 533 } 534 535 if (s < 0) { 536 DMSG("I2C no solution at all"); 537 return -1; 538 } 539 540 /* Finalize timing settings */ 541 *timing = I2C_SET_TIMINGR_PRESC(s) | 542 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 543 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 544 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 545 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 546 547 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%"PRIu8"/%"PRIu8, 548 s, solutions[s].scldel, solutions[s].sdadel); 549 DMSG("I2C TIMINGR (SCLH/SCLL): %"PRIu8"/%"PRIu8, 550 solutions[s].sclh, solutions[s].scll); 551 DMSG("I2C TIMINGR: 0x%"PRIx32, *timing); 552 553 return 0; 554 } 555 556 /* i2c_specs[] must be sorted by increasing rate */ 557 static bool __maybe_unused i2c_specs_is_consistent(void) 558 { 559 size_t i = 0; 560 561 COMPILE_TIME_ASSERT(ARRAY_SIZE(i2c_specs)); 562 563 for (i = 1; i < ARRAY_SIZE(i2c_specs); i++) 564 if (i2c_specs[i - 1].rate >= i2c_specs[i].rate) 565 return false; 566 567 return true; 568 } 569 570 /* 571 * @brief From requested rate, get the closest I2C rate without exceeding it, 572 * within I2C specification values defined in @i2c_specs. 573 * @param rate: The requested rate. 574 * @retval Found rate, else the lowest value supported by platform. 575 */ 576 static uint32_t get_lower_rate(uint32_t rate) 577 { 578 size_t i = 0; 579 580 for (i = ARRAY_SIZE(i2c_specs); i > 0; i--) 581 if (rate > i2c_specs[i - 1].rate) 582 return i2c_specs[i - 1].rate; 583 584 return i2c_specs[0].rate; 585 } 586 587 /* 588 * Setup the I2C device timings 589 * 590 * @hi2c: I2C handle structure 591 * @init: Ref to the initialization configuration structure 592 * @timing: Output TIMINGR register configuration value 593 * @retval 0 if OK, negative value else 594 */ 595 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 596 struct stm32_i2c_init_s *init, 597 uint32_t *timing) 598 { 599 int rc = 0; 600 unsigned long clock_src = 0; 601 602 assert(i2c_specs_is_consistent()); 603 604 clock_src = clk_get_rate(hi2c->clock); 605 if (!clock_src) { 606 DMSG("Null I2C clock rate"); 607 return -1; 608 } 609 610 /* 611 * If the timing has already been computed, and the frequency is the 612 * same as when it was computed, then use the saved timing. 613 */ 614 if (clock_src == hi2c->saved_frequency) { 615 *timing = hi2c->saved_timing; 616 return 0; 617 } 618 619 do { 620 rc = i2c_compute_timing(init, clock_src, timing); 621 if (rc) { 622 DMSG("Failed to compute I2C timings"); 623 if (init->bus_rate > I2C_STANDARD_RATE) { 624 init->bus_rate = get_lower_rate(init->bus_rate); 625 IMSG("Downgrade I2C speed to %"PRIu32"Hz)", 626 init->bus_rate); 627 } else { 628 break; 629 } 630 } 631 } while (rc); 632 633 if (rc) { 634 DMSG("Impossible to compute I2C timings"); 635 return rc; 636 } 637 638 DMSG("I2C Freq(%"PRIu32"Hz), Clk Source(%lu)", 639 init->bus_rate, clock_src); 640 DMSG("I2C Rise(%"PRId32") and Fall(%"PRId32") Time", 641 init->rise_time, init->fall_time); 642 DMSG("I2C Analog Filter(%s), DNF(%"PRIu8")", 643 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 644 645 hi2c->saved_timing = *timing; 646 hi2c->saved_frequency = clock_src; 647 648 return 0; 649 } 650 651 /* 652 * Configure I2C Analog noise filter. 653 * @hi2c: I2C handle structure 654 * @analog_filter_on: True if enabling analog filter, false otherwise 655 * Return 0 on success or a negative value 656 */ 657 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 658 bool analog_filter_on) 659 { 660 vaddr_t base = get_base(hi2c); 661 662 if (hi2c->i2c_state != I2C_STATE_READY) 663 return -1; 664 665 hi2c->i2c_state = I2C_STATE_BUSY; 666 667 /* Disable the selected I2C peripheral */ 668 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 669 670 /* Reset I2Cx ANOFF bit */ 671 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 672 673 /* Set analog filter bit if filter is disabled */ 674 if (!analog_filter_on) 675 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 676 677 /* Enable the selected I2C peripheral */ 678 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 679 680 hi2c->i2c_state = I2C_STATE_READY; 681 682 return 0; 683 } 684 685 TEE_Result stm32_i2c_get_setup_from_fdt(void *fdt, int node, 686 struct stm32_i2c_init_s *init, 687 struct stm32_pinctrl **pinctrl, 688 size_t *pinctrl_count) 689 { 690 TEE_Result res = TEE_ERROR_GENERIC; 691 const fdt32_t *cuint = NULL; 692 struct dt_node_info info = { .status = 0 }; 693 int count = 0; 694 695 /* Default STM32 specific configs caller may need to overwrite */ 696 memset(init, 0, sizeof(*init)); 697 698 fdt_fill_device_info(fdt, &info, node); 699 assert(info.reg != DT_INFO_INVALID_REG && 700 info.reg_size != DT_INFO_INVALID_REG_SIZE); 701 702 init->dt_status = info.status; 703 init->pbase = info.reg; 704 init->reg_size = info.reg_size; 705 706 res = clk_dt_get_by_index(fdt, node, 0, &init->clock); 707 if (res) 708 return res; 709 710 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 711 if (cuint) 712 init->rise_time = fdt32_to_cpu(*cuint); 713 else 714 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 715 716 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 717 if (cuint) 718 init->fall_time = fdt32_to_cpu(*cuint); 719 else 720 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 721 722 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 723 if (cuint) { 724 init->bus_rate = fdt32_to_cpu(*cuint); 725 726 if (init->bus_rate > I2C_FAST_PLUS_RATE) { 727 DMSG("Invalid bus speed (%"PRIu32" > %i)", 728 init->bus_rate, I2C_FAST_PLUS_RATE); 729 return TEE_ERROR_GENERIC; 730 } 731 } else { 732 init->bus_rate = I2C_STANDARD_RATE; 733 } 734 735 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 736 if (count <= 0) { 737 *pinctrl = NULL; 738 *pinctrl_count = count; 739 DMSG("Failed to get pinctrl: FDT errno %d", count); 740 return TEE_ERROR_GENERIC; 741 } 742 743 if (count > 2) { 744 DMSG("Too many PINCTRLs found: %zd", count); 745 return TEE_ERROR_GENERIC; 746 } 747 748 *pinctrl = calloc(count, sizeof(**pinctrl)); 749 if (!*pinctrl) 750 return TEE_ERROR_OUT_OF_MEMORY; 751 752 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 753 *pinctrl, count); 754 assert(*pinctrl_count == (unsigned int)count); 755 756 return TEE_SUCCESS; 757 } 758 759 int stm32_i2c_init(struct i2c_handle_s *hi2c, 760 struct stm32_i2c_init_s *init_data) 761 { 762 int rc = 0; 763 uint32_t timing = 0; 764 vaddr_t base = 0; 765 uint32_t val = 0; 766 767 hi2c->dt_status = init_data->dt_status; 768 hi2c->base.pa = init_data->pbase; 769 hi2c->reg_size = init_data->reg_size; 770 hi2c->clock = init_data->clock; 771 772 rc = i2c_setup_timing(hi2c, init_data, &timing); 773 if (rc) 774 return rc; 775 776 clk_enable(hi2c->clock); 777 778 base = get_base(hi2c); 779 hi2c->i2c_state = I2C_STATE_BUSY; 780 781 /* Disable the selected I2C peripheral */ 782 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 783 784 /* Configure I2Cx: Frequency range */ 785 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 786 787 /* Disable Own Address1 before set the Own Address1 configuration */ 788 io_write32(base + I2C_OAR1, 0); 789 790 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 791 if (init_data->addr_mode_10b_not_7b) 792 io_write32(base + I2C_OAR1, 793 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 794 init_data->own_address1); 795 else 796 io_write32(base + I2C_OAR1, 797 I2C_OAR1_OA1EN | init_data->own_address1); 798 799 /* Configure I2Cx: Addressing Master mode */ 800 io_write32(base + I2C_CR2, 0); 801 if (init_data->addr_mode_10b_not_7b) 802 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 803 804 /* 805 * Enable the AUTOEND by default, and enable NACK 806 * (should be disabled only during Slave process). 807 */ 808 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 809 810 /* Disable Own Address2 before set the Own Address2 configuration */ 811 io_write32(base + I2C_OAR2, 0); 812 813 /* Configure I2Cx: Dual mode and Own Address2 */ 814 if (init_data->dual_address_mode) 815 io_write32(base + I2C_OAR2, 816 I2C_OAR2_OA2EN | init_data->own_address2 | 817 (init_data->own_address2_masks << 8)); 818 819 /* Configure I2Cx: Generalcall and NoStretch mode */ 820 val = 0; 821 if (init_data->general_call_mode) 822 val |= I2C_CR1_GCEN; 823 if (init_data->no_stretch_mode) 824 val |= I2C_CR1_NOSTRETCH; 825 io_write32(base + I2C_CR1, val); 826 827 /* Enable the selected I2C peripheral */ 828 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 829 830 hi2c->i2c_err = I2C_ERROR_NONE; 831 hi2c->i2c_state = I2C_STATE_READY; 832 833 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 834 if (rc) 835 DMSG("I2C analog filter error %d", rc); 836 837 if (IS_ENABLED(CFG_STM32MP13)) { 838 size_t n = 0; 839 840 for (n = 0; n < hi2c->pinctrl_count; n++) 841 stm32_gpio_set_secure_cfg(hi2c->pinctrl[n].bank, 842 hi2c->pinctrl[n].pin, true); 843 } 844 845 clk_disable(hi2c->clock); 846 847 return rc; 848 } 849 850 /* I2C transmit (TX) data register flush sequence */ 851 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 852 { 853 vaddr_t base = get_base(hi2c); 854 855 /* 856 * If a pending TXIS flag is set, 857 * write a dummy data in TXDR to clear it. 858 */ 859 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 860 io_write32(base + I2C_TXDR, 0); 861 862 /* Flush TX register if not empty */ 863 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 864 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 865 } 866 867 /* 868 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 869 * 870 * @hi2c: I2C handle structure 871 * @bit_mask: Bit mask for the target single bit position to consider 872 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 873 * @timeout_ref: Expriation timeout reference 874 * Return 0 on success and a non-zero value on timeout 875 */ 876 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 877 unsigned int awaited_value, uint64_t timeout_ref) 878 { 879 vaddr_t isr = get_base(hi2c) + I2C_ISR; 880 881 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 882 883 /* May timeout while TEE thread is suspended */ 884 while (!timeout_elapsed(timeout_ref)) 885 if (!!(io_read32(isr) & bit_mask) == awaited_value) 886 break; 887 888 if (!!(io_read32(isr) & bit_mask) == awaited_value) 889 return 0; 890 891 notif_i2c_timeout(hi2c); 892 return -1; 893 } 894 895 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 896 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 897 { 898 vaddr_t base = get_base(hi2c); 899 900 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 901 return 0; 902 903 /* 904 * Wait until STOP Flag is reset. Use polling method. 905 * AutoEnd should be initiate after AF. 906 * Timeout may elpased while TEE thread is suspended. 907 */ 908 while (!timeout_elapsed(timeout_ref)) 909 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 910 break; 911 912 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 913 notif_i2c_timeout(hi2c); 914 return -1; 915 } 916 917 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 918 919 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 920 921 i2c_flush_txdr(hi2c); 922 923 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 924 925 hi2c->i2c_err |= I2C_ERROR_ACKF; 926 hi2c->i2c_state = I2C_STATE_READY; 927 928 return -1; 929 } 930 931 /* Wait TXIS bit is 1 in I2C_ISR register */ 932 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 933 { 934 while (!timeout_elapsed(timeout_ref)) { 935 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 936 break; 937 if (i2c_ack_failed(hi2c, timeout_ref)) 938 return -1; 939 } 940 941 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 942 return 0; 943 944 if (i2c_ack_failed(hi2c, timeout_ref)) 945 return -1; 946 947 notif_i2c_timeout(hi2c); 948 return -1; 949 } 950 951 /* Wait STOPF bit is 1 in I2C_ISR register */ 952 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 953 { 954 while (!timeout_elapsed(timeout_ref)) { 955 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 956 break; 957 958 if (i2c_ack_failed(hi2c, timeout_ref)) 959 return -1; 960 } 961 962 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 963 return 0; 964 965 if (i2c_ack_failed(hi2c, timeout_ref)) 966 return -1; 967 968 notif_i2c_timeout(hi2c); 969 return -1; 970 } 971 972 /* 973 * Load I2C_CR2 register for a I2C transfer 974 * 975 * @hi2c: I2C handle structure 976 * @dev_addr: Slave address to be transferred 977 * @size: Number of bytes to be transferred 978 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 979 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 980 * I2C_GENERATE_START_{READ|WRITE} 981 */ 982 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 983 uint32_t size, uint32_t i2c_mode, 984 uint32_t startstop) 985 { 986 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 987 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 988 (I2C_CR2_RD_WRN & 989 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 990 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 991 ((size << I2C_CR2_NBYTES_OFFSET) & 992 I2C_CR2_NBYTES) | 993 i2c_mode | startstop; 994 995 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 996 } 997 998 /* 999 * Master sends target device address followed by internal memory 1000 * address for a memory write request. 1001 * Function returns 0 on success or a negative value. 1002 */ 1003 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 1004 struct i2c_request *request, 1005 uint64_t timeout_ref) 1006 { 1007 vaddr_t base = get_base(hi2c); 1008 1009 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 1010 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 1011 1012 if (i2c_wait_txis(hi2c, timeout_ref)) 1013 return -1; 1014 1015 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 1016 /* Send memory address */ 1017 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1018 } else { 1019 /* Send MSB of memory address */ 1020 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1021 1022 if (i2c_wait_txis(hi2c, timeout_ref)) 1023 return -1; 1024 1025 /* Send LSB of memory address */ 1026 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1027 } 1028 1029 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1030 return -1; 1031 1032 return 0; 1033 } 1034 1035 /* 1036 * Master sends target device address followed by internal memory 1037 * address to prepare a memory read request. 1038 * Function returns 0 on success or a negative value. 1039 */ 1040 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 1041 struct i2c_request *request, 1042 uint64_t timeout_ref) 1043 { 1044 vaddr_t base = get_base(hi2c); 1045 1046 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 1047 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 1048 1049 if (i2c_wait_txis(hi2c, timeout_ref)) 1050 return -1; 1051 1052 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 1053 /* Send memory address */ 1054 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1055 } else { 1056 /* Send MSB of memory address */ 1057 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1058 1059 if (i2c_wait_txis(hi2c, timeout_ref)) 1060 return -1; 1061 1062 /* Send LSB of memory address */ 1063 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1064 } 1065 1066 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1067 return -1; 1068 1069 return 0; 1070 } 1071 1072 /* 1073 * Write an amount of data in blocking mode 1074 * 1075 * @hi2c: Reference to struct i2c_handle_s 1076 * @request: I2C request parameters 1077 * @p_data: Pointer to data buffer 1078 * @size: Amount of data to be sent 1079 * Return 0 on success or a negative value 1080 */ 1081 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1082 uint8_t *p_data, uint16_t size) 1083 { 1084 uint64_t timeout_ref = 0; 1085 vaddr_t base = get_base(hi2c); 1086 int rc = -1; 1087 uint8_t *p_buff = p_data; 1088 size_t xfer_size = 0; 1089 size_t xfer_count = size; 1090 1091 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1092 return -1; 1093 1094 if (hi2c->i2c_state != I2C_STATE_READY) 1095 return -1; 1096 1097 if (!p_data || !size) 1098 return -1; 1099 1100 clk_enable(hi2c->clock); 1101 1102 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1103 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1104 goto bail; 1105 1106 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1107 hi2c->i2c_err = I2C_ERROR_NONE; 1108 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1109 1110 if (request->mode == I2C_MODE_MEM) { 1111 /* In memory mode, send slave address and memory address */ 1112 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1113 goto bail; 1114 1115 if (xfer_count > MAX_NBYTE_SIZE) { 1116 xfer_size = MAX_NBYTE_SIZE; 1117 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1118 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1119 } else { 1120 xfer_size = xfer_count; 1121 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1122 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1123 } 1124 } else { 1125 /* In master mode, send slave address */ 1126 if (xfer_count > MAX_NBYTE_SIZE) { 1127 xfer_size = MAX_NBYTE_SIZE; 1128 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1129 I2C_RELOAD_MODE, 1130 I2C_GENERATE_START_WRITE); 1131 } else { 1132 xfer_size = xfer_count; 1133 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1134 I2C_AUTOEND_MODE, 1135 I2C_GENERATE_START_WRITE); 1136 } 1137 } 1138 1139 do { 1140 if (i2c_wait_txis(hi2c, timeout_ref)) 1141 goto bail; 1142 1143 io_write8(base + I2C_TXDR, *p_buff); 1144 p_buff++; 1145 xfer_count--; 1146 xfer_size--; 1147 1148 if (xfer_count && !xfer_size) { 1149 /* Wait until TCR flag is set */ 1150 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1151 goto bail; 1152 1153 if (xfer_count > MAX_NBYTE_SIZE) { 1154 xfer_size = MAX_NBYTE_SIZE; 1155 i2c_transfer_config(hi2c, request->dev_addr, 1156 xfer_size, 1157 I2C_RELOAD_MODE, 1158 I2C_NO_STARTSTOP); 1159 } else { 1160 xfer_size = xfer_count; 1161 i2c_transfer_config(hi2c, request->dev_addr, 1162 xfer_size, 1163 I2C_AUTOEND_MODE, 1164 I2C_NO_STARTSTOP); 1165 } 1166 } 1167 1168 } while (xfer_count > 0U); 1169 1170 /* 1171 * No need to Check TC flag, with AUTOEND mode the stop 1172 * is automatically generated. 1173 * Wait until STOPF flag is reset. 1174 */ 1175 if (i2c_wait_stop(hi2c, timeout_ref)) 1176 goto bail; 1177 1178 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1179 1180 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1181 1182 hi2c->i2c_state = I2C_STATE_READY; 1183 1184 rc = 0; 1185 1186 bail: 1187 clk_disable(hi2c->clock); 1188 1189 return rc; 1190 } 1191 1192 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1193 uint32_t mem_addr, uint32_t mem_addr_size, 1194 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1195 { 1196 struct i2c_request request = { 1197 .dev_addr = dev_addr, 1198 .mode = I2C_MODE_MEM, 1199 .mem_addr = mem_addr, 1200 .mem_addr_size = mem_addr_size, 1201 .timeout_ms = timeout_ms, 1202 }; 1203 1204 return i2c_write(hi2c, &request, p_data, size); 1205 } 1206 1207 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1208 uint8_t *p_data, size_t size, 1209 unsigned int timeout_ms) 1210 { 1211 struct i2c_request request = { 1212 .dev_addr = dev_addr, 1213 .mode = I2C_MODE_MASTER, 1214 .timeout_ms = timeout_ms, 1215 }; 1216 1217 return i2c_write(hi2c, &request, p_data, size); 1218 } 1219 1220 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1221 unsigned int mem_addr, uint8_t *p_data, 1222 bool write) 1223 { 1224 uint64_t timeout_ref = 0; 1225 uintptr_t base = get_base(hi2c); 1226 int rc = -1; 1227 uint8_t *p_buff = p_data; 1228 uint32_t event_mask = 0; 1229 1230 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) 1231 return -1; 1232 1233 clk_enable(hi2c->clock); 1234 1235 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1236 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1237 goto bail; 1238 1239 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1240 hi2c->i2c_err = I2C_ERROR_NONE; 1241 1242 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1243 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1244 I2C_GENERATE_START_WRITE); 1245 1246 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1247 if (i2c_wait_txis(hi2c, timeout_ref)) 1248 goto bail; 1249 1250 io_write8(base + I2C_TXDR, mem_addr); 1251 1252 if (write) 1253 event_mask = I2C_ISR_TCR; 1254 else 1255 event_mask = I2C_ISR_TC; 1256 1257 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1258 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1259 goto bail; 1260 1261 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1262 I2C_AUTOEND_MODE, 1263 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1264 1265 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1266 if (write) { 1267 if (i2c_wait_txis(hi2c, timeout_ref)) 1268 goto bail; 1269 1270 io_write8(base + I2C_TXDR, *p_buff); 1271 } else { 1272 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1273 goto bail; 1274 1275 *p_buff = io_read8(base + I2C_RXDR); 1276 } 1277 1278 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1279 if (i2c_wait_stop(hi2c, timeout_ref)) 1280 goto bail; 1281 1282 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1283 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1284 1285 hi2c->i2c_state = I2C_STATE_READY; 1286 1287 rc = 0; 1288 1289 bail: 1290 clk_disable(hi2c->clock); 1291 1292 return rc; 1293 } 1294 1295 /* 1296 * Read an amount of data in blocking mode 1297 * 1298 * @hi2c: Reference to struct i2c_handle_s 1299 * @request: I2C request parameters 1300 * @p_data: Pointer to data buffer 1301 * @size: Amount of data to be sent 1302 * Return 0 on success or a negative value 1303 */ 1304 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1305 uint8_t *p_data, uint32_t size) 1306 { 1307 vaddr_t base = get_base(hi2c); 1308 uint64_t timeout_ref = 0; 1309 int rc = -1; 1310 uint8_t *p_buff = p_data; 1311 size_t xfer_count = size; 1312 size_t xfer_size = 0; 1313 1314 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1315 return -1; 1316 1317 if (hi2c->i2c_state != I2C_STATE_READY) 1318 return -1; 1319 1320 if (!p_data || !size) 1321 return -1; 1322 1323 clk_enable(hi2c->clock); 1324 1325 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1326 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1327 goto bail; 1328 1329 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1330 hi2c->i2c_err = I2C_ERROR_NONE; 1331 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1332 1333 if (request->mode == I2C_MODE_MEM) { 1334 /* Send memory address */ 1335 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1336 goto bail; 1337 } 1338 1339 /* 1340 * Send slave address. 1341 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1342 * and generate RESTART. 1343 */ 1344 if (xfer_count > MAX_NBYTE_SIZE) { 1345 xfer_size = MAX_NBYTE_SIZE; 1346 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1347 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1348 } else { 1349 xfer_size = xfer_count; 1350 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1351 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1352 } 1353 1354 do { 1355 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, 1356 timeout_init_us(I2C_TIMEOUT_RXNE_MS * 1000))) 1357 goto bail; 1358 1359 *p_buff = io_read8(base + I2C_RXDR); 1360 p_buff++; 1361 xfer_size--; 1362 xfer_count--; 1363 1364 if (xfer_count && !xfer_size) { 1365 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1366 goto bail; 1367 1368 if (xfer_count > MAX_NBYTE_SIZE) { 1369 xfer_size = MAX_NBYTE_SIZE; 1370 i2c_transfer_config(hi2c, request->dev_addr, 1371 xfer_size, 1372 I2C_RELOAD_MODE, 1373 I2C_NO_STARTSTOP); 1374 } else { 1375 xfer_size = xfer_count; 1376 i2c_transfer_config(hi2c, request->dev_addr, 1377 xfer_size, 1378 I2C_AUTOEND_MODE, 1379 I2C_NO_STARTSTOP); 1380 } 1381 } 1382 } while (xfer_count > 0U); 1383 1384 /* 1385 * No need to Check TC flag, with AUTOEND mode the stop 1386 * is automatically generated. 1387 * Wait until STOPF flag is reset. 1388 */ 1389 if (i2c_wait_stop(hi2c, timeout_ref)) 1390 goto bail; 1391 1392 /* Clear the NACK generated at the end of the transfer */ 1393 if ((io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_NACKF)) 1394 io_write32(get_base(hi2c) + I2C_ICR, I2C_ICR_NACKCF); 1395 1396 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1397 1398 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1399 1400 hi2c->i2c_state = I2C_STATE_READY; 1401 1402 rc = 0; 1403 1404 bail: 1405 clk_disable(hi2c->clock); 1406 1407 return rc; 1408 } 1409 1410 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1411 uint32_t mem_addr, uint32_t mem_addr_size, 1412 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1413 { 1414 struct i2c_request request = { 1415 .dev_addr = dev_addr, 1416 .mode = I2C_MODE_MEM, 1417 .mem_addr = mem_addr, 1418 .mem_addr_size = mem_addr_size, 1419 .timeout_ms = timeout_ms, 1420 }; 1421 1422 return i2c_read(hi2c, &request, p_data, size); 1423 } 1424 1425 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1426 uint8_t *p_data, size_t size, 1427 unsigned int timeout_ms) 1428 { 1429 struct i2c_request request = { 1430 .dev_addr = dev_addr, 1431 .mode = I2C_MODE_MASTER, 1432 .timeout_ms = timeout_ms, 1433 }; 1434 1435 return i2c_read(hi2c, &request, p_data, size); 1436 } 1437 1438 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1439 unsigned int trials, unsigned int timeout_ms) 1440 { 1441 vaddr_t base = get_base(hi2c); 1442 unsigned int i2c_trials = 0U; 1443 bool rc = false; 1444 1445 if (hi2c->i2c_state != I2C_STATE_READY) 1446 return rc; 1447 1448 clk_enable(hi2c->clock); 1449 1450 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1451 goto bail; 1452 1453 hi2c->i2c_state = I2C_STATE_BUSY; 1454 hi2c->i2c_err = I2C_ERROR_NONE; 1455 1456 do { 1457 uint64_t timeout_ref = 0; 1458 vaddr_t isr = base + I2C_ISR; 1459 1460 /* Generate Start */ 1461 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1462 io_write32(base + I2C_CR2, 1463 ((dev_addr & I2C_CR2_SADD) | 1464 I2C_CR2_START | I2C_CR2_AUTOEND) & 1465 ~I2C_CR2_RD_WRN); 1466 else 1467 io_write32(base + I2C_CR2, 1468 ((dev_addr & I2C_CR2_SADD) | 1469 I2C_CR2_START | I2C_CR2_ADD10) & 1470 ~I2C_CR2_RD_WRN); 1471 1472 /* 1473 * No need to Check TC flag, with AUTOEND mode the stop 1474 * is automatically generated. 1475 * Wait until STOPF flag is set or a NACK flag is set. 1476 */ 1477 timeout_ref = timeout_init_us(timeout_ms * 1000); 1478 while (!timeout_elapsed(timeout_ref)) 1479 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1480 break; 1481 1482 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1483 notif_i2c_timeout(hi2c); 1484 goto bail; 1485 } 1486 1487 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1488 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1489 goto bail; 1490 1491 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1492 1493 hi2c->i2c_state = I2C_STATE_READY; 1494 1495 rc = true; 1496 goto bail; 1497 } 1498 1499 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1500 goto bail; 1501 1502 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1503 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1504 1505 if (i2c_trials == trials) { 1506 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1507 1508 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1509 goto bail; 1510 1511 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1512 } 1513 1514 i2c_trials++; 1515 } while (i2c_trials < trials); 1516 1517 notif_i2c_timeout(hi2c); 1518 1519 bail: 1520 clk_disable(hi2c->clock); 1521 1522 return rc; 1523 } 1524 1525 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1526 { 1527 if (hi2c->i2c_state == I2C_STATE_READY) 1528 return; 1529 1530 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1531 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1532 panic(); 1533 1534 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1535 1536 if (hi2c->i2c_state == I2C_STATE_RESET) { 1537 /* There is no valid I2C configuration to be loaded yet */ 1538 return; 1539 } 1540 1541 restore_cfg(hi2c, &hi2c->sec_cfg); 1542 1543 if (IS_ENABLED(CFG_STM32MP13)) { 1544 size_t n = 0; 1545 1546 for (n = 0; n < hi2c->pinctrl_count; n++) 1547 stm32_gpio_set_secure_cfg(hi2c->pinctrl[n].bank, 1548 hi2c->pinctrl[n].pin, true); 1549 } 1550 1551 hi2c->i2c_state = I2C_STATE_READY; 1552 } 1553 1554 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1555 { 1556 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1557 return; 1558 1559 if (hi2c->i2c_state != I2C_STATE_READY) 1560 panic(); 1561 1562 save_cfg(hi2c, &hi2c->sec_cfg); 1563 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1564 1565 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1566 } 1567