1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000L 157 #define I2C_TIMEOUT_BUSY_MS 25 158 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 159 160 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 161 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 162 I2C_CR2_RD_WRN) 163 164 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 165 I2C_TIMINGR_SDADEL | \ 166 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 167 168 /* 169 * I2C transfer modes 170 * I2C_RELOAD: Enable Reload mode 171 * I2C_AUTOEND_MODE: Enable automatic end mode 172 * I2C_SOFTEND_MODE: Enable software end mode 173 */ 174 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 175 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 176 #define I2C_SOFTEND_MODE 0x0 177 178 /* 179 * Start/restart/stop I2C transfer requests. 180 * 181 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 182 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 183 * I2C_GENERATE_START_READ: Generate Restart for read request. 184 * I2C_GENERATE_START_WRITE: Generate Restart for write request 185 */ 186 #define I2C_NO_STARTSTOP 0x0 187 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 188 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 189 I2C_CR2_RD_WRN) 190 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 191 192 /* Memory address byte sizes */ 193 #define I2C_MEMADD_SIZE_8BIT 1 194 #define I2C_MEMADD_SIZE_16BIT 2 195 196 /* 197 * struct i2c_spec_s - Private I2C timing specifications. 198 * @rate: I2C bus speed (Hz) 199 * @rate_min: 80% of I2C bus speed (Hz) 200 * @rate_max: 120% of I2C bus speed (Hz) 201 * @fall_max: Max fall time of both SDA and SCL signals (ns) 202 * @rise_max: Max rise time of both SDA and SCL signals (ns) 203 * @hddat_min: Min data hold time (ns) 204 * @vddat_max: Max data valid time (ns) 205 * @sudat_min: Min data setup time (ns) 206 * @l_min: Min low period of the SCL clock (ns) 207 * @h_min: Min high period of the SCL clock (ns) 208 */ 209 struct i2c_spec_s { 210 uint32_t rate; 211 uint32_t rate_min; 212 uint32_t rate_max; 213 uint32_t fall_max; 214 uint32_t rise_max; 215 uint32_t hddat_min; 216 uint32_t vddat_max; 217 uint32_t sudat_min; 218 uint32_t l_min; 219 uint32_t h_min; 220 }; 221 222 /* 223 * struct i2c_timing_s - Private I2C output parameters. 224 * @scldel: Data setup time 225 * @sdadel: Data hold time 226 * @sclh: SCL high period (master mode) 227 * @sclh: SCL low period (master mode) 228 * @is_saved: True if relating to a configuration candidate 229 */ 230 struct i2c_timing_s { 231 uint8_t scldel; 232 uint8_t sdadel; 233 uint8_t sclh; 234 uint8_t scll; 235 bool is_saved; 236 }; 237 238 static const struct i2c_spec_s i2c_specs[] = { 239 [I2C_SPEED_STANDARD] = { 240 .rate = I2C_STANDARD_RATE, 241 .rate_min = (I2C_STANDARD_RATE * 80) / 100, 242 .rate_max = (I2C_STANDARD_RATE * 120) / 100, 243 .fall_max = 300, 244 .rise_max = 1000, 245 .hddat_min = 0, 246 .vddat_max = 3450, 247 .sudat_min = 250, 248 .l_min = 4700, 249 .h_min = 4000, 250 }, 251 [I2C_SPEED_FAST] = { 252 .rate = I2C_FAST_RATE, 253 .rate_min = (I2C_FAST_RATE * 80) / 100, 254 .rate_max = (I2C_FAST_RATE * 120) / 100, 255 .fall_max = 300, 256 .rise_max = 300, 257 .hddat_min = 0, 258 .vddat_max = 900, 259 .sudat_min = 100, 260 .l_min = 1300, 261 .h_min = 600, 262 }, 263 [I2C_SPEED_FAST_PLUS] = { 264 .rate = I2C_FAST_PLUS_RATE, 265 .rate_min = (I2C_FAST_PLUS_RATE * 80) / 100, 266 .rate_max = (I2C_FAST_PLUS_RATE * 120) / 100, 267 .fall_max = 100, 268 .rise_max = 120, 269 .hddat_min = 0, 270 .vddat_max = 450, 271 .sudat_min = 50, 272 .l_min = 500, 273 .h_min = 260, 274 }, 275 }; 276 277 /* 278 * I2C request parameters 279 * @dev_addr: I2C address of the target device 280 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 281 * @mem_addr: Target memory cell accessed in device (memory mode) 282 * @mem_addr_size: Byte size of the memory cell address (memory mode) 283 * @timeout_ms: Timeout in millisenconds for the request 284 */ 285 struct i2c_request { 286 uint32_t dev_addr; 287 enum i2c_mode_e mode; 288 uint32_t mem_addr; 289 uint32_t mem_addr_size; 290 unsigned int timeout_ms; 291 }; 292 293 static vaddr_t get_base(struct i2c_handle_s *hi2c) 294 { 295 return io_pa_or_va_secure(&hi2c->base); 296 } 297 298 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 299 { 300 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 301 hi2c->i2c_state = I2C_STATE_READY; 302 } 303 304 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 305 { 306 vaddr_t base = get_base(hi2c); 307 308 stm32_clock_enable(hi2c->clock); 309 310 cfg->cr1 = io_read32(base + I2C_CR1); 311 cfg->cr2 = io_read32(base + I2C_CR2); 312 cfg->oar1 = io_read32(base + I2C_OAR1); 313 cfg->oar2 = io_read32(base + I2C_OAR2); 314 cfg->timingr = io_read32(base + I2C_TIMINGR); 315 316 stm32_clock_disable(hi2c->clock); 317 } 318 319 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 320 { 321 vaddr_t base = get_base(hi2c); 322 323 stm32_clock_enable(hi2c->clock); 324 325 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 326 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 327 io_write32(base + I2C_OAR1, cfg->oar1); 328 io_write32(base + I2C_CR2, cfg->cr2); 329 io_write32(base + I2C_OAR2, cfg->oar2); 330 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 331 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 332 333 stm32_clock_disable(hi2c->clock); 334 } 335 336 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 337 { 338 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 339 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 340 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 341 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 342 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 343 } 344 345 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 346 { 347 vaddr_t __maybe_unused base = get_base(hi2c); 348 349 stm32_clock_enable(hi2c->clock); 350 351 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 352 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 353 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 354 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 355 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 356 357 stm32_clock_disable(hi2c->clock); 358 } 359 360 /* 361 * Compute the I2C device timings 362 * 363 * @init: Ref to the initialization configuration structure 364 * @clock_src: I2C clock source frequency (Hz) 365 * @timing: Pointer to the final computed timing result 366 * Return 0 on success or a negative value 367 */ 368 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 369 uint32_t clock_src, uint32_t *timing) 370 { 371 enum i2c_speed_e mode = init->speed_mode; 372 uint32_t speed_freq = i2c_specs[mode].rate; 373 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 374 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 375 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 376 uint32_t af_delay_min = 0; 377 uint32_t af_delay_max = 0; 378 uint32_t dnf_delay = 0; 379 uint32_t tsync = 0; 380 uint32_t clk_min = 0; 381 uint32_t clk_max = 0; 382 int clk_error_prev = 0; 383 uint16_t p = 0; 384 uint16_t l = 0; 385 uint16_t a = 0; 386 uint16_t h = 0; 387 unsigned int sdadel_min = 0; 388 unsigned int sdadel_max = 0; 389 unsigned int scldel_min = 0; 390 unsigned int delay = 0; 391 int s = -1; 392 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 393 394 switch (mode) { 395 case I2C_SPEED_STANDARD: 396 case I2C_SPEED_FAST: 397 case I2C_SPEED_FAST_PLUS: 398 break; 399 default: 400 EMSG("I2C speed out of bound {%d/%d}", 401 mode, I2C_SPEED_FAST_PLUS); 402 return -1; 403 } 404 405 speed_freq = i2c_specs[mode].rate; 406 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 407 clk_error_prev = INT_MAX; 408 409 if ((init->rise_time > i2c_specs[mode].rise_max) || 410 (init->fall_time > i2c_specs[mode].fall_max)) { 411 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 412 init->rise_time, i2c_specs[mode].rise_max, 413 init->fall_time, i2c_specs[mode].fall_max); 414 return -1; 415 } 416 417 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 418 EMSG("DNF out of bound %d/%d", 419 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 420 return -1; 421 } 422 423 /* Analog and Digital Filters */ 424 if (init->analog_filter) { 425 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 426 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 427 } 428 dnf_delay = init->digital_filter_coef * i2cclk; 429 430 sdadel_min = i2c_specs[mode].hddat_min + init->fall_time; 431 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 432 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 433 sdadel_min = 0; 434 435 sdadel_max = i2c_specs[mode].vddat_max - init->rise_time; 436 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 437 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 438 sdadel_max = 0; 439 440 scldel_min = init->rise_time + i2c_specs[mode].sudat_min; 441 442 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 443 sdadel_min, sdadel_max, scldel_min); 444 445 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 446 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 447 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 448 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 449 450 if (scldel < scldel_min) 451 continue; 452 453 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 454 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 455 456 if ((sdadel >= sdadel_min) && 457 (sdadel <= sdadel_max) && 458 (p != p_prev)) { 459 solutions[p].scldel = l; 460 solutions[p].sdadel = a; 461 solutions[p].is_saved = true; 462 p_prev = p; 463 break; 464 } 465 } 466 467 if (p_prev == p) 468 break; 469 } 470 } 471 472 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 473 EMSG(" I2C no Prescaler solution"); 474 return -1; 475 } 476 477 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 478 clk_max = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_min; 479 clk_min = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_max; 480 481 /* 482 * Among prescaler possibilities discovered above figures out SCL Low 483 * and High Period. Provided: 484 * - SCL Low Period has to be higher than Low Period of the SCL Clock 485 * defined by I2C Specification. I2C Clock has to be lower than 486 * (SCL Low Period - Analog/Digital filters) / 4. 487 * - SCL High Period has to be lower than High Period of the SCL Clock 488 * defined by I2C Specification. 489 * - I2C Clock has to be lower than SCL High Period. 490 */ 491 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 492 uint32_t prescaler = (p + 1) * i2cclk; 493 494 if (!solutions[p].is_saved) 495 continue; 496 497 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 498 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 499 500 if ((tscl_l < i2c_specs[mode].l_min) || 501 (i2cclk >= 502 ((tscl_l - af_delay_min - dnf_delay) / 4))) 503 continue; 504 505 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 506 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 507 uint32_t tscl = tscl_l + tscl_h + 508 init->rise_time + 509 init->fall_time; 510 511 if ((tscl >= clk_min) && (tscl <= clk_max) && 512 (tscl_h >= i2c_specs[mode].h_min) && 513 (i2cclk < tscl_h)) { 514 int clk_error = tscl - i2cbus; 515 516 if (clk_error < 0) 517 clk_error = -clk_error; 518 519 if (clk_error < clk_error_prev) { 520 clk_error_prev = clk_error; 521 solutions[p].scll = l; 522 solutions[p].sclh = h; 523 s = p; 524 } 525 } 526 } 527 } 528 } 529 530 if (s < 0) { 531 EMSG(" I2C no solution at all"); 532 return -1; 533 } 534 535 /* Finalize timing settings */ 536 *timing = I2C_SET_TIMINGR_PRESC(s) | 537 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 538 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 539 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 540 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 541 542 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 543 s, solutions[s].scldel, solutions[s].sdadel); 544 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 545 solutions[s].sclh, solutions[s].scll); 546 DMSG("I2C TIMINGR: 0x%x", *timing); 547 548 return 0; 549 } 550 551 /* 552 * Setup the I2C device timings 553 * 554 * @hi2c: I2C handle structure 555 * @init: Ref to the initialization configuration structure 556 * @timing: Output TIMINGR register configuration value 557 * @retval 0 if OK, negative value else 558 */ 559 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 560 struct stm32_i2c_init_s *init, 561 uint32_t *timing) 562 { 563 int rc = 0; 564 uint32_t clock_src = stm32_clock_get_rate(hi2c->clock); 565 566 if (!clock_src) { 567 EMSG("Null I2C clock rate"); 568 return -1; 569 } 570 571 do { 572 rc = i2c_compute_timing(init, clock_src, timing); 573 if (rc) { 574 EMSG("Failed to compute I2C timings"); 575 if (init->speed_mode > I2C_SPEED_STANDARD) { 576 init->speed_mode--; 577 IMSG("Downgrade I2C speed to %uHz)", 578 i2c_specs[init->speed_mode].rate); 579 } else { 580 break; 581 } 582 } 583 } while (rc); 584 585 if (rc) { 586 EMSG("Impossible to compute I2C timings"); 587 return rc; 588 } 589 590 DMSG("I2C Speed Mode(%i), Freq(%i), Clk Source(%i)", 591 init->speed_mode, i2c_specs[init->speed_mode].rate, clock_src); 592 DMSG("I2C Rise(%i) and Fall(%i) Time", 593 init->rise_time, init->fall_time); 594 DMSG("I2C Analog Filter(%s), DNF(%i)", 595 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 596 597 return 0; 598 } 599 600 /* 601 * Configure I2C Analog noise filter. 602 * @hi2c: I2C handle structure 603 * @analog_filter_on: True if enabling analog filter, false otherwise 604 * Return 0 on success or a negative value 605 */ 606 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 607 bool analog_filter_on) 608 { 609 vaddr_t base = get_base(hi2c); 610 611 if (hi2c->i2c_state != I2C_STATE_READY) 612 return -1; 613 614 hi2c->i2c_state = I2C_STATE_BUSY; 615 616 /* Disable the selected I2C peripheral */ 617 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 618 619 /* Reset I2Cx ANOFF bit */ 620 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 621 622 /* Set analog filter bit if filter is disabled */ 623 if (!analog_filter_on) 624 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 625 626 /* Enable the selected I2C peripheral */ 627 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 628 629 hi2c->i2c_state = I2C_STATE_READY; 630 631 return 0; 632 } 633 634 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 635 struct stm32_i2c_init_s *init, 636 struct stm32_pinctrl **pinctrl, 637 size_t *pinctrl_count) 638 { 639 const fdt32_t *cuint = NULL; 640 struct dt_node_info info = { .status = 0 }; 641 int count = 0; 642 643 /* Default STM32 specific configs caller may need to overwrite */ 644 memset(init, 0, sizeof(*init)); 645 646 _fdt_fill_device_info(fdt, &info, node); 647 init->dt_status = info.status; 648 init->pbase = info.reg; 649 init->clock = info.clock; 650 assert(info.reg != DT_INFO_INVALID_REG && 651 info.clock != DT_INFO_INVALID_CLOCK); 652 653 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 654 if (cuint) 655 init->rise_time = fdt32_to_cpu(*cuint); 656 else 657 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 658 659 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 660 if (cuint) 661 init->fall_time = fdt32_to_cpu(*cuint); 662 else 663 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 664 665 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 666 if (cuint) { 667 switch (fdt32_to_cpu(*cuint)) { 668 case I2C_STANDARD_RATE: 669 init->speed_mode = I2C_SPEED_STANDARD; 670 break; 671 case I2C_FAST_RATE: 672 init->speed_mode = I2C_SPEED_FAST; 673 break; 674 case I2C_FAST_PLUS_RATE: 675 init->speed_mode = I2C_SPEED_FAST_PLUS; 676 break; 677 default: 678 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 679 break; 680 } 681 } else { 682 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 683 } 684 685 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 686 if (count <= 0) { 687 *pinctrl = NULL; 688 *pinctrl_count = 0; 689 return count; 690 } 691 692 if (count > 2) 693 panic("Too many PINCTRLs found"); 694 695 *pinctrl = calloc(count, sizeof(**pinctrl)); 696 if (!*pinctrl) 697 panic(); 698 699 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 700 *pinctrl, count); 701 assert(*pinctrl_count == (unsigned int)count); 702 703 return 0; 704 } 705 706 int stm32_i2c_init(struct i2c_handle_s *hi2c, 707 struct stm32_i2c_init_s *init_data) 708 { 709 int rc = 0; 710 uint32_t timing = 0; 711 vaddr_t base = 0; 712 uint32_t val = 0; 713 714 hi2c->dt_status = init_data->dt_status; 715 hi2c->base.pa = init_data->pbase; 716 hi2c->clock = init_data->clock; 717 718 rc = i2c_setup_timing(hi2c, init_data, &timing); 719 if (rc) 720 return rc; 721 722 stm32_clock_enable(hi2c->clock); 723 base = get_base(hi2c); 724 hi2c->i2c_state = I2C_STATE_BUSY; 725 726 /* Disable the selected I2C peripheral */ 727 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 728 729 /* Configure I2Cx: Frequency range */ 730 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 731 732 /* Disable Own Address1 before set the Own Address1 configuration */ 733 io_write32(base + I2C_OAR1, 0); 734 735 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 736 if (init_data->addr_mode_10b_not_7b) 737 io_write32(base + I2C_OAR1, 738 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 739 init_data->own_address1); 740 else 741 io_write32(base + I2C_OAR1, 742 I2C_OAR1_OA1EN | init_data->own_address1); 743 744 /* Configure I2Cx: Addressing Master mode */ 745 io_write32(base + I2C_CR2, 0); 746 if (init_data->addr_mode_10b_not_7b) 747 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 748 749 /* 750 * Enable the AUTOEND by default, and enable NACK 751 * (should be disabled only during Slave process). 752 */ 753 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 754 755 /* Disable Own Address2 before set the Own Address2 configuration */ 756 io_write32(base + I2C_OAR2, 0); 757 758 /* Configure I2Cx: Dual mode and Own Address2 */ 759 if (init_data->dual_address_mode) 760 io_write32(base + I2C_OAR2, 761 I2C_OAR2_OA2EN | init_data->own_address2 | 762 (init_data->own_address2_masks << 8)); 763 764 /* Configure I2Cx: Generalcall and NoStretch mode */ 765 val = 0; 766 if (init_data->general_call_mode) 767 val |= I2C_CR1_GCEN; 768 if (init_data->no_stretch_mode) 769 val |= I2C_CR1_NOSTRETCH; 770 io_write32(base + I2C_CR1, val); 771 772 /* Enable the selected I2C peripheral */ 773 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 774 775 hi2c->i2c_err = I2C_ERROR_NONE; 776 hi2c->i2c_state = I2C_STATE_READY; 777 778 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 779 if (rc) 780 EMSG("I2C analog filter error %d", rc); 781 782 stm32_clock_disable(hi2c->clock); 783 784 return rc; 785 } 786 787 /* I2C transmit (TX) data register flush sequence */ 788 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 789 { 790 vaddr_t base = get_base(hi2c); 791 792 /* 793 * If a pending TXIS flag is set, 794 * write a dummy data in TXDR to clear it. 795 */ 796 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 797 io_write32(base + I2C_TXDR, 0); 798 799 /* Flush TX register if not empty */ 800 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 801 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 802 } 803 804 /* 805 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 806 * 807 * @hi2c: I2C handle structure 808 * @bit_mask: Bit mask for the target single bit position to consider 809 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 810 * @timeout_ref: Expriation timeout reference 811 * Return 0 on success and a non-zero value on timeout 812 */ 813 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 814 unsigned int awaited_value, uint64_t timeout_ref) 815 { 816 vaddr_t isr = get_base(hi2c) + I2C_ISR; 817 818 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 819 820 /* May timeout while TEE thread is suspended */ 821 while (!timeout_elapsed(timeout_ref)) 822 if (!!(io_read32(isr) & bit_mask) == awaited_value) 823 break; 824 825 if (!!(io_read32(isr) & bit_mask) == awaited_value) 826 return 0; 827 828 notif_i2c_timeout(hi2c); 829 return -1; 830 } 831 832 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 833 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 834 { 835 vaddr_t base = get_base(hi2c); 836 837 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 838 return 0; 839 840 /* 841 * Wait until STOP Flag is reset. Use polling method. 842 * AutoEnd should be initiate after AF. 843 * Timeout may elpased while TEE thread is suspended. 844 */ 845 while (!timeout_elapsed(timeout_ref)) 846 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 847 break; 848 849 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 850 notif_i2c_timeout(hi2c); 851 return -1; 852 } 853 854 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 855 856 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 857 858 i2c_flush_txdr(hi2c); 859 860 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 861 862 hi2c->i2c_err |= I2C_ERROR_ACKF; 863 hi2c->i2c_state = I2C_STATE_READY; 864 865 return -1; 866 } 867 868 /* Wait TXIS bit is 1 in I2C_ISR register */ 869 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 870 { 871 while (!timeout_elapsed(timeout_ref)) { 872 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 873 break; 874 if (i2c_ack_failed(hi2c, timeout_ref)) 875 return -1; 876 } 877 878 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 879 return 0; 880 881 if (i2c_ack_failed(hi2c, timeout_ref)) 882 return -1; 883 884 notif_i2c_timeout(hi2c); 885 return -1; 886 } 887 888 /* Wait STOPF bit is 1 in I2C_ISR register */ 889 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 890 { 891 while (!timeout_elapsed(timeout_ref)) { 892 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 893 break; 894 895 if (i2c_ack_failed(hi2c, timeout_ref)) 896 return -1; 897 } 898 899 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 900 return 0; 901 902 if (i2c_ack_failed(hi2c, timeout_ref)) 903 return -1; 904 905 notif_i2c_timeout(hi2c); 906 return -1; 907 } 908 909 /* 910 * Load I2C_CR2 register for a I2C transfer 911 * 912 * @hi2c: I2C handle structure 913 * @dev_addr: Slave address to be transferred 914 * @size: Number of bytes to be transferred 915 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 916 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 917 * I2C_GENERATE_START_{READ|WRITE} 918 */ 919 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 920 uint32_t size, uint32_t i2c_mode, 921 uint32_t startstop) 922 { 923 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 924 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 925 (I2C_CR2_RD_WRN & 926 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 927 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 928 ((size << I2C_CR2_NBYTES_OFFSET) & 929 I2C_CR2_NBYTES) | 930 i2c_mode | startstop; 931 932 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 933 } 934 935 /* 936 * Master sends target device address followed by internal memory 937 * address for a memory write request. 938 * Function returns 0 on success or a negative value. 939 */ 940 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 941 struct i2c_request *request, 942 uint64_t timeout_ref) 943 { 944 vaddr_t base = get_base(hi2c); 945 946 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 947 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 948 949 if (i2c_wait_txis(hi2c, timeout_ref)) 950 return -1; 951 952 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 953 /* Send memory address */ 954 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 955 } else { 956 /* Send MSB of memory address */ 957 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 958 959 if (i2c_wait_txis(hi2c, timeout_ref)) 960 return -1; 961 962 /* Send LSB of memory address */ 963 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 964 } 965 966 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 967 return -1; 968 969 return 0; 970 } 971 972 /* 973 * Master sends target device address followed by internal memory 974 * address to prepare a memory read request. 975 * Function returns 0 on success or a negative value. 976 */ 977 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 978 struct i2c_request *request, 979 uint64_t timeout_ref) 980 { 981 vaddr_t base = get_base(hi2c); 982 983 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 984 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 985 986 if (i2c_wait_txis(hi2c, timeout_ref)) 987 return -1; 988 989 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 990 /* Send memory address */ 991 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 992 } else { 993 /* Send MSB of memory address */ 994 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 995 996 if (i2c_wait_txis(hi2c, timeout_ref)) 997 return -1; 998 999 /* Send LSB of memory address */ 1000 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1001 } 1002 1003 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1004 return -1; 1005 1006 return 0; 1007 } 1008 1009 /* 1010 * Write an amount of data in blocking mode 1011 * 1012 * @hi2c: Reference to struct i2c_handle_s 1013 * @request: I2C request parameters 1014 * @p_data: Pointer to data buffer 1015 * @size: Amount of data to be sent 1016 * Return 0 on success or a negative value 1017 */ 1018 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1019 uint8_t *p_data, uint16_t size) 1020 { 1021 uint64_t timeout_ref = 0; 1022 vaddr_t base = get_base(hi2c); 1023 int rc = -1; 1024 uint8_t *p_buff = p_data; 1025 size_t xfer_size = 0; 1026 size_t xfer_count = size; 1027 1028 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1029 return -1; 1030 1031 if (hi2c->i2c_state != I2C_STATE_READY) 1032 return -1; 1033 1034 if (!p_data || !size) 1035 return -1; 1036 1037 stm32_clock_enable(hi2c->clock); 1038 1039 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1040 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1041 goto bail; 1042 1043 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1044 hi2c->i2c_err = I2C_ERROR_NONE; 1045 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1046 1047 if (request->mode == I2C_MODE_MEM) { 1048 /* In memory mode, send slave address and memory address */ 1049 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1050 goto bail; 1051 1052 if (xfer_count > MAX_NBYTE_SIZE) { 1053 xfer_size = MAX_NBYTE_SIZE; 1054 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1055 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1056 } else { 1057 xfer_size = xfer_count; 1058 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1059 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1060 } 1061 } else { 1062 /* In master mode, send slave address */ 1063 if (xfer_count > MAX_NBYTE_SIZE) { 1064 xfer_size = MAX_NBYTE_SIZE; 1065 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1066 I2C_RELOAD_MODE, 1067 I2C_GENERATE_START_WRITE); 1068 } else { 1069 xfer_size = xfer_count; 1070 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1071 I2C_AUTOEND_MODE, 1072 I2C_GENERATE_START_WRITE); 1073 } 1074 } 1075 1076 do { 1077 if (i2c_wait_txis(hi2c, timeout_ref)) 1078 goto bail; 1079 1080 io_write8(base + I2C_TXDR, *p_buff); 1081 p_buff++; 1082 xfer_count--; 1083 xfer_size--; 1084 1085 if (xfer_count && !xfer_size) { 1086 /* Wait until TCR flag is set */ 1087 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1088 goto bail; 1089 1090 if (xfer_count > MAX_NBYTE_SIZE) { 1091 xfer_size = MAX_NBYTE_SIZE; 1092 i2c_transfer_config(hi2c, request->dev_addr, 1093 xfer_size, 1094 I2C_RELOAD_MODE, 1095 I2C_NO_STARTSTOP); 1096 } else { 1097 xfer_size = xfer_count; 1098 i2c_transfer_config(hi2c, request->dev_addr, 1099 xfer_size, 1100 I2C_AUTOEND_MODE, 1101 I2C_NO_STARTSTOP); 1102 } 1103 } 1104 1105 } while (xfer_count > 0U); 1106 1107 /* 1108 * No need to Check TC flag, with AUTOEND mode the stop 1109 * is automatically generated. 1110 * Wait until STOPF flag is reset. 1111 */ 1112 if (i2c_wait_stop(hi2c, timeout_ref)) 1113 goto bail; 1114 1115 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1116 1117 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1118 1119 hi2c->i2c_state = I2C_STATE_READY; 1120 1121 rc = 0; 1122 1123 bail: 1124 stm32_clock_disable(hi2c->clock); 1125 1126 return rc; 1127 } 1128 1129 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1130 uint32_t mem_addr, uint32_t mem_addr_size, 1131 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1132 { 1133 struct i2c_request request = { 1134 .dev_addr = dev_addr, 1135 .mode = I2C_MODE_MEM, 1136 .mem_addr = mem_addr, 1137 .mem_addr_size = mem_addr_size, 1138 .timeout_ms = timeout_ms, 1139 }; 1140 1141 return i2c_write(hi2c, &request, p_data, size); 1142 } 1143 1144 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1145 uint8_t *p_data, size_t size, 1146 unsigned int timeout_ms) 1147 { 1148 struct i2c_request request = { 1149 .dev_addr = dev_addr, 1150 .mode = I2C_MODE_MASTER, 1151 .timeout_ms = timeout_ms, 1152 }; 1153 1154 return i2c_write(hi2c, &request, p_data, size); 1155 } 1156 1157 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1158 unsigned int mem_addr, uint8_t *p_data, 1159 bool write) 1160 { 1161 uint64_t timeout_ref = 0; 1162 uintptr_t base = get_base(hi2c); 1163 int rc = -1; 1164 uint8_t *p_buff = p_data; 1165 uint32_t event_mask = 0; 1166 1167 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) 1168 return -1; 1169 1170 stm32_clock_enable(hi2c->clock); 1171 1172 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1173 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1174 goto bail; 1175 1176 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1177 hi2c->i2c_err = I2C_ERROR_NONE; 1178 1179 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1180 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1181 I2C_GENERATE_START_WRITE); 1182 1183 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1184 if (i2c_wait_txis(hi2c, timeout_ref)) 1185 goto bail; 1186 1187 io_write8(base + I2C_TXDR, mem_addr); 1188 1189 if (write) 1190 event_mask = I2C_ISR_TCR; 1191 else 1192 event_mask = I2C_ISR_TC; 1193 1194 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1195 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1196 goto bail; 1197 1198 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1199 I2C_AUTOEND_MODE, 1200 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1201 1202 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1203 if (write) { 1204 if (i2c_wait_txis(hi2c, timeout_ref)) 1205 goto bail; 1206 1207 io_write8(base + I2C_TXDR, *p_buff); 1208 } else { 1209 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1210 goto bail; 1211 1212 *p_buff = io_read8(base + I2C_RXDR); 1213 } 1214 1215 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1216 if (i2c_wait_stop(hi2c, timeout_ref)) 1217 goto bail; 1218 1219 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1220 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1221 1222 hi2c->i2c_state = I2C_STATE_READY; 1223 1224 rc = 0; 1225 1226 bail: 1227 stm32_clock_disable(hi2c->clock); 1228 1229 return rc; 1230 } 1231 1232 /* 1233 * Read an amount of data in blocking mode 1234 * 1235 * @hi2c: Reference to struct i2c_handle_s 1236 * @request: I2C request parameters 1237 * @p_data: Pointer to data buffer 1238 * @size: Amount of data to be sent 1239 * Return 0 on success or a negative value 1240 */ 1241 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1242 uint8_t *p_data, uint32_t size) 1243 { 1244 vaddr_t base = get_base(hi2c); 1245 uint64_t timeout_ref = 0; 1246 int rc = -1; 1247 uint8_t *p_buff = p_data; 1248 size_t xfer_count = size; 1249 size_t xfer_size = 0; 1250 1251 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1252 return -1; 1253 1254 if (hi2c->i2c_state != I2C_STATE_READY) 1255 return -1; 1256 1257 if (!p_data || !size) 1258 return -1; 1259 1260 stm32_clock_enable(hi2c->clock); 1261 1262 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1263 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1264 goto bail; 1265 1266 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1267 hi2c->i2c_err = I2C_ERROR_NONE; 1268 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1269 1270 if (request->mode == I2C_MODE_MEM) { 1271 /* Send memory address */ 1272 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1273 goto bail; 1274 } 1275 1276 /* 1277 * Send slave address. 1278 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1279 * and generate RESTART. 1280 */ 1281 if (xfer_count > MAX_NBYTE_SIZE) { 1282 xfer_size = MAX_NBYTE_SIZE; 1283 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1284 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1285 } else { 1286 xfer_size = xfer_count; 1287 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1288 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1289 } 1290 1291 do { 1292 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1293 goto bail; 1294 1295 *p_buff = io_read8(base + I2C_RXDR); 1296 p_buff++; 1297 xfer_size--; 1298 xfer_count--; 1299 1300 if (xfer_count && !xfer_size) { 1301 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1302 goto bail; 1303 1304 if (xfer_count > MAX_NBYTE_SIZE) { 1305 xfer_size = MAX_NBYTE_SIZE; 1306 i2c_transfer_config(hi2c, request->dev_addr, 1307 xfer_size, 1308 I2C_RELOAD_MODE, 1309 I2C_NO_STARTSTOP); 1310 } else { 1311 xfer_size = xfer_count; 1312 i2c_transfer_config(hi2c, request->dev_addr, 1313 xfer_size, 1314 I2C_AUTOEND_MODE, 1315 I2C_NO_STARTSTOP); 1316 } 1317 } 1318 } while (xfer_count > 0U); 1319 1320 /* 1321 * No need to Check TC flag, with AUTOEND mode the stop 1322 * is automatically generated. 1323 * Wait until STOPF flag is reset. 1324 */ 1325 if (i2c_wait_stop(hi2c, timeout_ref)) 1326 goto bail; 1327 1328 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1329 1330 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1331 1332 hi2c->i2c_state = I2C_STATE_READY; 1333 1334 rc = 0; 1335 1336 bail: 1337 stm32_clock_disable(hi2c->clock); 1338 1339 return rc; 1340 } 1341 1342 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1343 uint32_t mem_addr, uint32_t mem_addr_size, 1344 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1345 { 1346 struct i2c_request request = { 1347 .dev_addr = dev_addr, 1348 .mode = I2C_MODE_MEM, 1349 .mem_addr = mem_addr, 1350 .mem_addr_size = mem_addr_size, 1351 .timeout_ms = timeout_ms, 1352 }; 1353 1354 return i2c_read(hi2c, &request, p_data, size); 1355 } 1356 1357 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1358 uint8_t *p_data, size_t size, 1359 unsigned int timeout_ms) 1360 { 1361 struct i2c_request request = { 1362 .dev_addr = dev_addr, 1363 .mode = I2C_MODE_MASTER, 1364 .timeout_ms = timeout_ms, 1365 }; 1366 1367 return i2c_read(hi2c, &request, p_data, size); 1368 } 1369 1370 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1371 unsigned int trials, unsigned int timeout_ms) 1372 { 1373 vaddr_t base = get_base(hi2c); 1374 unsigned int i2c_trials = 0U; 1375 bool rc = false; 1376 1377 if (hi2c->i2c_state != I2C_STATE_READY) 1378 return rc; 1379 1380 stm32_clock_enable(hi2c->clock); 1381 1382 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1383 goto bail; 1384 1385 hi2c->i2c_state = I2C_STATE_BUSY; 1386 hi2c->i2c_err = I2C_ERROR_NONE; 1387 1388 do { 1389 uint64_t timeout_ref = 0; 1390 vaddr_t isr = base + I2C_ISR; 1391 1392 /* Generate Start */ 1393 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1394 io_write32(base + I2C_CR2, 1395 ((dev_addr & I2C_CR2_SADD) | 1396 I2C_CR2_START | I2C_CR2_AUTOEND) & 1397 ~I2C_CR2_RD_WRN); 1398 else 1399 io_write32(base + I2C_CR2, 1400 ((dev_addr & I2C_CR2_SADD) | 1401 I2C_CR2_START | I2C_CR2_ADD10) & 1402 ~I2C_CR2_RD_WRN); 1403 1404 /* 1405 * No need to Check TC flag, with AUTOEND mode the stop 1406 * is automatically generated. 1407 * Wait until STOPF flag is set or a NACK flag is set. 1408 */ 1409 timeout_ref = timeout_init_us(timeout_ms * 1000); 1410 while (!timeout_elapsed(timeout_ref)) 1411 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1412 break; 1413 1414 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1415 notif_i2c_timeout(hi2c); 1416 goto bail; 1417 } 1418 1419 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1420 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1421 goto bail; 1422 1423 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1424 1425 hi2c->i2c_state = I2C_STATE_READY; 1426 1427 rc = true; 1428 goto bail; 1429 } 1430 1431 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1432 goto bail; 1433 1434 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1435 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1436 1437 if (i2c_trials == trials) { 1438 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1439 1440 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1441 goto bail; 1442 1443 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1444 } 1445 1446 i2c_trials++; 1447 } while (i2c_trials < trials); 1448 1449 notif_i2c_timeout(hi2c); 1450 1451 bail: 1452 stm32_clock_disable(hi2c->clock); 1453 1454 return rc; 1455 } 1456 1457 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1458 { 1459 if (hi2c->i2c_state == I2C_STATE_READY) 1460 return; 1461 1462 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1463 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1464 panic(); 1465 1466 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1467 1468 if (hi2c->i2c_state == I2C_STATE_RESET) { 1469 /* There is no valid I2C configuration to be loaded yet */ 1470 return; 1471 } 1472 1473 restore_cfg(hi2c, &hi2c->sec_cfg); 1474 1475 hi2c->i2c_state = I2C_STATE_READY; 1476 } 1477 1478 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1479 { 1480 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1481 return; 1482 1483 if (hi2c->i2c_state != I2C_STATE_READY) 1484 panic(); 1485 1486 save_cfg(hi2c, &hi2c->sec_cfg); 1487 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1488 1489 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1490 } 1491