1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000L 157 #define I2C_TIMEOUT_BUSY_MS 25 158 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 159 160 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 161 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 162 I2C_CR2_RD_WRN) 163 164 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 165 I2C_TIMINGR_SDADEL | \ 166 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 167 168 /* 169 * I2C transfer modes 170 * I2C_RELOAD: Enable Reload mode 171 * I2C_AUTOEND_MODE: Enable automatic end mode 172 * I2C_SOFTEND_MODE: Enable software end mode 173 */ 174 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 175 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 176 #define I2C_SOFTEND_MODE 0x0 177 178 /* 179 * Start/restart/stop I2C transfer requests. 180 * 181 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 182 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 183 * I2C_GENERATE_START_READ: Generate Restart for read request. 184 * I2C_GENERATE_START_WRITE: Generate Restart for write request 185 */ 186 #define I2C_NO_STARTSTOP 0x0 187 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 188 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 189 I2C_CR2_RD_WRN) 190 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 191 192 /* Memory address byte sizes */ 193 #define I2C_MEMADD_SIZE_8BIT 1 194 #define I2C_MEMADD_SIZE_16BIT 2 195 196 /* 197 * struct i2c_spec_s - Private I2C timing specifications. 198 * @rate: I2C bus speed (Hz) 199 * @rate_min: 80% of I2C bus speed (Hz) 200 * @rate_max: 120% of I2C bus speed (Hz) 201 * @fall_max: Max fall time of both SDA and SCL signals (ns) 202 * @rise_max: Max rise time of both SDA and SCL signals (ns) 203 * @hddat_min: Min data hold time (ns) 204 * @vddat_max: Max data valid time (ns) 205 * @sudat_min: Min data setup time (ns) 206 * @l_min: Min low period of the SCL clock (ns) 207 * @h_min: Min high period of the SCL clock (ns) 208 */ 209 struct i2c_spec_s { 210 uint32_t rate; 211 uint32_t rate_min; 212 uint32_t rate_max; 213 uint32_t fall_max; 214 uint32_t rise_max; 215 uint32_t hddat_min; 216 uint32_t vddat_max; 217 uint32_t sudat_min; 218 uint32_t l_min; 219 uint32_t h_min; 220 }; 221 222 /* 223 * struct i2c_timing_s - Private I2C output parameters. 224 * @scldel: Data setup time 225 * @sdadel: Data hold time 226 * @sclh: SCL high period (master mode) 227 * @sclh: SCL low period (master mode) 228 * @is_saved: True if relating to a configuration candidate 229 */ 230 struct i2c_timing_s { 231 uint8_t scldel; 232 uint8_t sdadel; 233 uint8_t sclh; 234 uint8_t scll; 235 bool is_saved; 236 }; 237 238 static const struct i2c_spec_s i2c_specs[] = { 239 [I2C_SPEED_STANDARD] = { 240 .rate = I2C_STANDARD_RATE, 241 .rate_min = (I2C_STANDARD_RATE * 80) / 100, 242 .rate_max = (I2C_STANDARD_RATE * 120) / 100, 243 .fall_max = 300, 244 .rise_max = 1000, 245 .hddat_min = 0, 246 .vddat_max = 3450, 247 .sudat_min = 250, 248 .l_min = 4700, 249 .h_min = 4000, 250 }, 251 [I2C_SPEED_FAST] = { 252 .rate = I2C_FAST_RATE, 253 .rate_min = (I2C_FAST_RATE * 80) / 100, 254 .rate_max = (I2C_FAST_RATE * 120) / 100, 255 .fall_max = 300, 256 .rise_max = 300, 257 .hddat_min = 0, 258 .vddat_max = 900, 259 .sudat_min = 100, 260 .l_min = 1300, 261 .h_min = 600, 262 }, 263 [I2C_SPEED_FAST_PLUS] = { 264 .rate = I2C_FAST_PLUS_RATE, 265 .rate_min = (I2C_FAST_PLUS_RATE * 80) / 100, 266 .rate_max = (I2C_FAST_PLUS_RATE * 120) / 100, 267 .fall_max = 100, 268 .rise_max = 120, 269 .hddat_min = 0, 270 .vddat_max = 450, 271 .sudat_min = 50, 272 .l_min = 500, 273 .h_min = 260, 274 }, 275 }; 276 277 /* 278 * I2C request parameters 279 * @dev_addr: I2C address of the target device 280 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 281 * @mem_addr: Target memory cell accessed in device (memory mode) 282 * @mem_addr_size: Byte size of the memory cell address (memory mode) 283 * @timeout_ms: Timeout in millisenconds for the request 284 */ 285 struct i2c_request { 286 uint32_t dev_addr; 287 enum i2c_mode_e mode; 288 uint32_t mem_addr; 289 uint32_t mem_addr_size; 290 unsigned int timeout_ms; 291 }; 292 293 static vaddr_t get_base(struct i2c_handle_s *hi2c) 294 { 295 return io_pa_or_va_secure(&hi2c->base); 296 } 297 298 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 299 { 300 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 301 hi2c->i2c_state = I2C_STATE_READY; 302 } 303 304 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 305 { 306 vaddr_t base = get_base(hi2c); 307 308 stm32_clock_enable(hi2c->clock); 309 310 cfg->cr1 = io_read32(base + I2C_CR1); 311 cfg->cr2 = io_read32(base + I2C_CR2); 312 cfg->oar1 = io_read32(base + I2C_OAR1); 313 cfg->oar2 = io_read32(base + I2C_OAR2); 314 cfg->timingr = io_read32(base + I2C_TIMINGR); 315 316 stm32_clock_disable(hi2c->clock); 317 } 318 319 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 320 { 321 vaddr_t base = get_base(hi2c); 322 323 stm32_clock_enable(hi2c->clock); 324 325 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 326 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 327 io_write32(base + I2C_OAR1, cfg->oar1); 328 io_write32(base + I2C_CR2, cfg->cr2); 329 io_write32(base + I2C_OAR2, cfg->oar2); 330 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 331 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 332 333 stm32_clock_disable(hi2c->clock); 334 } 335 336 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 337 { 338 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 339 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 340 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 341 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 342 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 343 } 344 345 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 346 { 347 vaddr_t __maybe_unused base = get_base(hi2c); 348 349 stm32_clock_enable(hi2c->clock); 350 351 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 352 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 353 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 354 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 355 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 356 357 stm32_clock_disable(hi2c->clock); 358 } 359 360 /* 361 * Compute the I2C device timings 362 * 363 * @init: Ref to the initialization configuration structure 364 * @clock_src: I2C clock source frequency (Hz) 365 * @timing: Pointer to the final computed timing result 366 * Return 0 on success or a negative value 367 */ 368 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 369 uint32_t clock_src, uint32_t *timing) 370 { 371 enum i2c_speed_e mode = init->speed_mode; 372 uint32_t speed_freq = i2c_specs[mode].rate; 373 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 374 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 375 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 376 uint32_t af_delay_min = 0; 377 uint32_t af_delay_max = 0; 378 uint32_t dnf_delay = 0; 379 uint32_t tsync = 0; 380 uint32_t clk_min = 0; 381 uint32_t clk_max = 0; 382 int clk_error_prev = 0; 383 uint16_t p = 0; 384 uint16_t l = 0; 385 uint16_t a = 0; 386 uint16_t h = 0; 387 unsigned int sdadel_min = 0; 388 unsigned int sdadel_max = 0; 389 unsigned int scldel_min = 0; 390 unsigned int delay = 0; 391 int s = -1; 392 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 393 394 switch (mode) { 395 case I2C_SPEED_STANDARD: 396 case I2C_SPEED_FAST: 397 case I2C_SPEED_FAST_PLUS: 398 break; 399 default: 400 EMSG("I2C speed out of bound {%d/%d}", 401 mode, I2C_SPEED_FAST_PLUS); 402 return -1; 403 } 404 405 speed_freq = i2c_specs[mode].rate; 406 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 407 clk_error_prev = INT_MAX; 408 409 if ((init->rise_time > i2c_specs[mode].rise_max) || 410 (init->fall_time > i2c_specs[mode].fall_max)) { 411 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 412 init->rise_time, i2c_specs[mode].rise_max, 413 init->fall_time, i2c_specs[mode].fall_max); 414 return -1; 415 } 416 417 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 418 EMSG("DNF out of bound %d/%d", 419 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 420 return -1; 421 } 422 423 /* Analog and Digital Filters */ 424 if (init->analog_filter) { 425 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 426 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 427 } 428 dnf_delay = init->digital_filter_coef * i2cclk; 429 430 sdadel_min = i2c_specs[mode].hddat_min + init->fall_time; 431 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 432 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 433 sdadel_min = 0; 434 435 sdadel_max = i2c_specs[mode].vddat_max - init->rise_time; 436 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 437 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 438 sdadel_max = 0; 439 440 scldel_min = init->rise_time + i2c_specs[mode].sudat_min; 441 442 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 443 sdadel_min, sdadel_max, scldel_min); 444 445 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 446 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 447 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 448 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 449 450 if (scldel < scldel_min) 451 continue; 452 453 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 454 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 455 456 if ((sdadel >= sdadel_min) && 457 (sdadel <= sdadel_max) && 458 (p != p_prev)) { 459 solutions[p].scldel = l; 460 solutions[p].sdadel = a; 461 solutions[p].is_saved = true; 462 p_prev = p; 463 break; 464 } 465 } 466 467 if (p_prev == p) 468 break; 469 } 470 } 471 472 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 473 EMSG(" I2C no Prescaler solution"); 474 return -1; 475 } 476 477 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 478 clk_max = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_min; 479 clk_min = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_max; 480 481 /* 482 * Among prescaler possibilities discovered above figures out SCL Low 483 * and High Period. Provided: 484 * - SCL Low Period has to be higher than Low Period of the SCL Clock 485 * defined by I2C Specification. I2C Clock has to be lower than 486 * (SCL Low Period - Analog/Digital filters) / 4. 487 * - SCL High Period has to be lower than High Period of the SCL Clock 488 * defined by I2C Specification. 489 * - I2C Clock has to be lower than SCL High Period. 490 */ 491 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 492 uint32_t prescaler = (p + 1) * i2cclk; 493 494 if (!solutions[p].is_saved) 495 continue; 496 497 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 498 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 499 500 if ((tscl_l < i2c_specs[mode].l_min) || 501 (i2cclk >= 502 ((tscl_l - af_delay_min - dnf_delay) / 4))) 503 continue; 504 505 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 506 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 507 uint32_t tscl = tscl_l + tscl_h + 508 init->rise_time + 509 init->fall_time; 510 511 if ((tscl >= clk_min) && (tscl <= clk_max) && 512 (tscl_h >= i2c_specs[mode].h_min) && 513 (i2cclk < tscl_h)) { 514 int clk_error = tscl - i2cbus; 515 516 if (clk_error < 0) 517 clk_error = -clk_error; 518 519 if (clk_error < clk_error_prev) { 520 clk_error_prev = clk_error; 521 solutions[p].scll = l; 522 solutions[p].sclh = h; 523 s = p; 524 } 525 } 526 } 527 } 528 } 529 530 if (s < 0) { 531 EMSG(" I2C no solution at all"); 532 return -1; 533 } 534 535 /* Finalize timing settings */ 536 *timing = I2C_SET_TIMINGR_PRESC(s) | 537 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 538 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 539 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 540 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 541 542 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 543 s, solutions[s].scldel, solutions[s].sdadel); 544 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 545 solutions[s].sclh, solutions[s].scll); 546 DMSG("I2C TIMINGR: 0x%x", *timing); 547 548 return 0; 549 } 550 551 /* 552 * Setup the I2C device timings 553 * 554 * @hi2c: I2C handle structure 555 * @init: Ref to the initialization configuration structure 556 * @timing: Output TIMINGR register configuration value 557 * @retval 0 if OK, negative value else 558 */ 559 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 560 struct stm32_i2c_init_s *init, 561 uint32_t *timing) 562 { 563 int rc = 0; 564 uint32_t clock_src = stm32_clock_get_rate(hi2c->clock); 565 566 if (!clock_src) { 567 EMSG("Null I2C clock rate"); 568 return -1; 569 } 570 571 do { 572 rc = i2c_compute_timing(init, clock_src, timing); 573 if (rc) { 574 EMSG("Failed to compute I2C timings"); 575 if (init->speed_mode > I2C_SPEED_STANDARD) { 576 init->speed_mode--; 577 IMSG("Downgrade I2C speed to %uHz)", 578 i2c_specs[init->speed_mode].rate); 579 } else { 580 break; 581 } 582 } 583 } while (rc); 584 585 if (rc) { 586 EMSG("Impossible to compute I2C timings"); 587 return rc; 588 } 589 590 DMSG("I2C Speed Mode(%i), Freq(%i), Clk Source(%i)", 591 init->speed_mode, i2c_specs[init->speed_mode].rate, clock_src); 592 DMSG("I2C Rise(%i) and Fall(%i) Time", 593 init->rise_time, init->fall_time); 594 DMSG("I2C Analog Filter(%s), DNF(%i)", 595 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 596 597 return 0; 598 } 599 600 /* 601 * Configure I2C Analog noise filter. 602 * @hi2c: I2C handle structure 603 * @analog_filter_on: True if enabling analog filter, false otherwise 604 * Return 0 on success or a negative value 605 */ 606 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 607 bool analog_filter_on) 608 { 609 vaddr_t base = get_base(hi2c); 610 611 if (hi2c->i2c_state != I2C_STATE_READY) 612 return -1; 613 614 hi2c->i2c_state = I2C_STATE_BUSY; 615 616 /* Disable the selected I2C peripheral */ 617 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 618 619 /* Reset I2Cx ANOFF bit */ 620 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 621 622 /* Set analog filter bit if filter is disabled */ 623 if (!analog_filter_on) 624 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 625 626 /* Enable the selected I2C peripheral */ 627 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 628 629 hi2c->i2c_state = I2C_STATE_READY; 630 631 return 0; 632 } 633 634 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 635 struct stm32_i2c_init_s *init, 636 struct stm32_pinctrl **pinctrl, 637 size_t *pinctrl_count) 638 { 639 const fdt32_t *cuint = NULL; 640 struct dt_node_info info = { .status = 0 }; 641 int count = 0; 642 643 /* Default STM32 specific configs caller may need to overwrite */ 644 memset(init, 0, sizeof(*init)); 645 646 _fdt_fill_device_info(fdt, &info, node); 647 init->pbase = info.reg; 648 init->clock = info.clock; 649 assert(info.reg != DT_INFO_INVALID_REG && 650 info.clock != DT_INFO_INVALID_CLOCK); 651 652 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 653 if (cuint) 654 init->rise_time = fdt32_to_cpu(*cuint); 655 else 656 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 657 658 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 659 if (cuint) 660 init->fall_time = fdt32_to_cpu(*cuint); 661 else 662 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 663 664 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 665 if (cuint) { 666 switch (fdt32_to_cpu(*cuint)) { 667 case I2C_STANDARD_RATE: 668 init->speed_mode = I2C_SPEED_STANDARD; 669 break; 670 case I2C_FAST_RATE: 671 init->speed_mode = I2C_SPEED_FAST; 672 break; 673 case I2C_FAST_PLUS_RATE: 674 init->speed_mode = I2C_SPEED_FAST_PLUS; 675 break; 676 default: 677 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 678 break; 679 } 680 } else { 681 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 682 } 683 684 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 685 if (count <= 0) { 686 *pinctrl = NULL; 687 *pinctrl_count = 0; 688 return count; 689 } 690 691 if (count > 2) 692 panic("Too many PINCTRLs found"); 693 694 *pinctrl = calloc(count, sizeof(**pinctrl)); 695 if (!*pinctrl) 696 panic(); 697 698 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 699 *pinctrl, count); 700 assert(*pinctrl_count == (unsigned int)count); 701 702 return 0; 703 } 704 705 int stm32_i2c_init(struct i2c_handle_s *hi2c, 706 struct stm32_i2c_init_s *init_data) 707 { 708 int rc = 0; 709 uint32_t timing = 0; 710 vaddr_t base = 0; 711 uint32_t val = 0; 712 713 hi2c->base.pa = init_data->pbase; 714 hi2c->clock = init_data->clock; 715 716 rc = i2c_setup_timing(hi2c, init_data, &timing); 717 if (rc) 718 return rc; 719 720 stm32_clock_enable(hi2c->clock); 721 base = get_base(hi2c); 722 hi2c->i2c_state = I2C_STATE_BUSY; 723 724 /* Disable the selected I2C peripheral */ 725 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 726 727 /* Configure I2Cx: Frequency range */ 728 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 729 730 /* Disable Own Address1 before set the Own Address1 configuration */ 731 io_write32(base + I2C_OAR1, 0); 732 733 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 734 if (init_data->addr_mode_10b_not_7b) 735 io_write32(base + I2C_OAR1, 736 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 737 init_data->own_address1); 738 else 739 io_write32(base + I2C_OAR1, 740 I2C_OAR1_OA1EN | init_data->own_address1); 741 742 /* Configure I2Cx: Addressing Master mode */ 743 io_write32(base + I2C_CR2, 0); 744 if (init_data->addr_mode_10b_not_7b) 745 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 746 747 /* 748 * Enable the AUTOEND by default, and enable NACK 749 * (should be disabled only during Slave process). 750 */ 751 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 752 753 /* Disable Own Address2 before set the Own Address2 configuration */ 754 io_write32(base + I2C_OAR2, 0); 755 756 /* Configure I2Cx: Dual mode and Own Address2 */ 757 if (init_data->dual_address_mode) 758 io_write32(base + I2C_OAR2, 759 I2C_OAR2_OA2EN | init_data->own_address2 | 760 (init_data->own_address2_masks << 8)); 761 762 /* Configure I2Cx: Generalcall and NoStretch mode */ 763 val = 0; 764 if (init_data->general_call_mode) 765 val |= I2C_CR1_GCEN; 766 if (init_data->no_stretch_mode) 767 val |= I2C_CR1_NOSTRETCH; 768 io_write32(base + I2C_CR1, val); 769 770 /* Enable the selected I2C peripheral */ 771 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 772 773 hi2c->i2c_err = I2C_ERROR_NONE; 774 hi2c->i2c_state = I2C_STATE_READY; 775 776 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 777 if (rc) 778 EMSG("I2C analog filter error %d", rc); 779 780 stm32_clock_disable(hi2c->clock); 781 782 return rc; 783 } 784 785 /* I2C transmit (TX) data register flush sequence */ 786 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 787 { 788 vaddr_t base = get_base(hi2c); 789 790 /* 791 * If a pending TXIS flag is set, 792 * write a dummy data in TXDR to clear it. 793 */ 794 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 795 io_write32(base + I2C_TXDR, 0); 796 797 /* Flush TX register if not empty */ 798 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 799 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 800 } 801 802 /* 803 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 804 * 805 * @hi2c: I2C handle structure 806 * @bit_mask: Bit mask for the target single bit position to consider 807 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 808 * @timeout_ref: Expriation timeout reference 809 * Return 0 on success and a non-zero value on timeout 810 */ 811 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 812 unsigned int awaited_value, uint64_t timeout_ref) 813 { 814 vaddr_t isr = get_base(hi2c) + I2C_ISR; 815 816 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 817 818 /* May timeout while TEE thread is suspended */ 819 while (!timeout_elapsed(timeout_ref)) 820 if (!!(io_read32(isr) & bit_mask) == awaited_value) 821 break; 822 823 if (!!(io_read32(isr) & bit_mask) == awaited_value) 824 return 0; 825 826 notif_i2c_timeout(hi2c); 827 return -1; 828 } 829 830 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 831 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 832 { 833 vaddr_t base = get_base(hi2c); 834 835 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 836 return 0; 837 838 /* 839 * Wait until STOP Flag is reset. Use polling method. 840 * AutoEnd should be initiate after AF. 841 * Timeout may elpased while TEE thread is suspended. 842 */ 843 while (!timeout_elapsed(timeout_ref)) 844 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 845 break; 846 847 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 848 notif_i2c_timeout(hi2c); 849 return -1; 850 } 851 852 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 853 854 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 855 856 i2c_flush_txdr(hi2c); 857 858 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 859 860 hi2c->i2c_err |= I2C_ERROR_ACKF; 861 hi2c->i2c_state = I2C_STATE_READY; 862 863 return -1; 864 } 865 866 /* Wait TXIS bit is 1 in I2C_ISR register */ 867 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 868 { 869 while (!timeout_elapsed(timeout_ref)) { 870 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 871 break; 872 if (i2c_ack_failed(hi2c, timeout_ref)) 873 return -1; 874 } 875 876 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 877 return 0; 878 879 if (i2c_ack_failed(hi2c, timeout_ref)) 880 return -1; 881 882 notif_i2c_timeout(hi2c); 883 return -1; 884 } 885 886 /* Wait STOPF bit is 1 in I2C_ISR register */ 887 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 888 { 889 while (!timeout_elapsed(timeout_ref)) { 890 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 891 break; 892 893 if (i2c_ack_failed(hi2c, timeout_ref)) 894 return -1; 895 } 896 897 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 898 return 0; 899 900 if (i2c_ack_failed(hi2c, timeout_ref)) 901 return -1; 902 903 notif_i2c_timeout(hi2c); 904 return -1; 905 } 906 907 /* 908 * Load I2C_CR2 register for a I2C transfer 909 * 910 * @hi2c: I2C handle structure 911 * @dev_addr: Slave address to be transferred 912 * @size: Number of bytes to be transferred 913 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 914 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 915 * I2C_GENERATE_START_{READ|WRITE} 916 */ 917 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 918 uint32_t size, uint32_t i2c_mode, 919 uint32_t startstop) 920 { 921 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 922 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 923 (I2C_CR2_RD_WRN & 924 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 925 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 926 ((size << I2C_CR2_NBYTES_OFFSET) & 927 I2C_CR2_NBYTES) | 928 i2c_mode | startstop; 929 930 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 931 } 932 933 /* 934 * Master sends target device address followed by internal memory 935 * address for a memory write request. 936 * Function returns 0 on success or a negative value. 937 */ 938 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 939 struct i2c_request *request, 940 uint64_t timeout_ref) 941 { 942 vaddr_t base = get_base(hi2c); 943 944 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 945 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 946 947 if (i2c_wait_txis(hi2c, timeout_ref)) 948 return -1; 949 950 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 951 /* Send memory address */ 952 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 953 } else { 954 /* Send MSB of memory address */ 955 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 956 957 if (i2c_wait_txis(hi2c, timeout_ref)) 958 return -1; 959 960 /* Send LSB of memory address */ 961 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 962 } 963 964 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 965 return -1; 966 967 return 0; 968 } 969 970 /* 971 * Master sends target device address followed by internal memory 972 * address to prepare a memory read request. 973 * Function returns 0 on success or a negative value. 974 */ 975 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 976 struct i2c_request *request, 977 uint64_t timeout_ref) 978 { 979 vaddr_t base = get_base(hi2c); 980 981 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 982 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 983 984 if (i2c_wait_txis(hi2c, timeout_ref)) 985 return -1; 986 987 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 988 /* Send memory address */ 989 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 990 } else { 991 /* Send MSB of memory address */ 992 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 993 994 if (i2c_wait_txis(hi2c, timeout_ref)) 995 return -1; 996 997 /* Send LSB of memory address */ 998 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 999 } 1000 1001 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1002 return -1; 1003 1004 return 0; 1005 } 1006 1007 /* 1008 * Write an amount of data in blocking mode 1009 * 1010 * @hi2c: Reference to struct i2c_handle_s 1011 * @request: I2C request parameters 1012 * @p_data: Pointer to data buffer 1013 * @size: Amount of data to be sent 1014 * Return 0 on success or a negative value 1015 */ 1016 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1017 uint8_t *p_data, uint16_t size) 1018 { 1019 uint64_t timeout_ref = 0; 1020 vaddr_t base = get_base(hi2c); 1021 int rc = -1; 1022 uint8_t *p_buff = p_data; 1023 size_t xfer_size = 0; 1024 size_t xfer_count = size; 1025 1026 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1027 return -1; 1028 1029 if (hi2c->i2c_state != I2C_STATE_READY) 1030 return -1; 1031 1032 if (!p_data || !size) 1033 return -1; 1034 1035 stm32_clock_enable(hi2c->clock); 1036 1037 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1038 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1039 goto bail; 1040 1041 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1042 hi2c->i2c_err = I2C_ERROR_NONE; 1043 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1044 1045 if (request->mode == I2C_MODE_MEM) { 1046 /* In memory mode, send slave address and memory address */ 1047 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1048 goto bail; 1049 1050 if (xfer_count > MAX_NBYTE_SIZE) { 1051 xfer_size = MAX_NBYTE_SIZE; 1052 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1053 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1054 } else { 1055 xfer_size = xfer_count; 1056 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1057 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1058 } 1059 } else { 1060 /* In master mode, send slave address */ 1061 if (xfer_count > MAX_NBYTE_SIZE) { 1062 xfer_size = MAX_NBYTE_SIZE; 1063 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1064 I2C_RELOAD_MODE, 1065 I2C_GENERATE_START_WRITE); 1066 } else { 1067 xfer_size = xfer_count; 1068 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1069 I2C_AUTOEND_MODE, 1070 I2C_GENERATE_START_WRITE); 1071 } 1072 } 1073 1074 do { 1075 if (i2c_wait_txis(hi2c, timeout_ref)) 1076 goto bail; 1077 1078 io_write8(base + I2C_TXDR, *p_buff); 1079 p_buff++; 1080 xfer_count--; 1081 xfer_size--; 1082 1083 if (xfer_count && !xfer_size) { 1084 /* Wait until TCR flag is set */ 1085 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1086 goto bail; 1087 1088 if (xfer_count > MAX_NBYTE_SIZE) { 1089 xfer_size = MAX_NBYTE_SIZE; 1090 i2c_transfer_config(hi2c, request->dev_addr, 1091 xfer_size, 1092 I2C_RELOAD_MODE, 1093 I2C_NO_STARTSTOP); 1094 } else { 1095 xfer_size = xfer_count; 1096 i2c_transfer_config(hi2c, request->dev_addr, 1097 xfer_size, 1098 I2C_AUTOEND_MODE, 1099 I2C_NO_STARTSTOP); 1100 } 1101 } 1102 1103 } while (xfer_count > 0U); 1104 1105 /* 1106 * No need to Check TC flag, with AUTOEND mode the stop 1107 * is automatically generated. 1108 * Wait until STOPF flag is reset. 1109 */ 1110 if (i2c_wait_stop(hi2c, timeout_ref)) 1111 goto bail; 1112 1113 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1114 1115 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1116 1117 hi2c->i2c_state = I2C_STATE_READY; 1118 1119 rc = 0; 1120 1121 bail: 1122 stm32_clock_disable(hi2c->clock); 1123 1124 return rc; 1125 } 1126 1127 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1128 uint32_t mem_addr, uint32_t mem_addr_size, 1129 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1130 { 1131 struct i2c_request request = { 1132 .dev_addr = dev_addr, 1133 .mode = I2C_MODE_MEM, 1134 .mem_addr = mem_addr, 1135 .mem_addr_size = mem_addr_size, 1136 .timeout_ms = timeout_ms, 1137 }; 1138 1139 return i2c_write(hi2c, &request, p_data, size); 1140 } 1141 1142 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1143 uint8_t *p_data, size_t size, 1144 unsigned int timeout_ms) 1145 { 1146 struct i2c_request request = { 1147 .dev_addr = dev_addr, 1148 .mode = I2C_MODE_MASTER, 1149 .timeout_ms = timeout_ms, 1150 }; 1151 1152 return i2c_write(hi2c, &request, p_data, size); 1153 } 1154 1155 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1156 unsigned int mem_addr, uint8_t *p_data, 1157 bool write) 1158 { 1159 uint64_t timeout_ref = 0; 1160 uintptr_t base = get_base(hi2c); 1161 int rc = -1; 1162 uint8_t *p_buff = p_data; 1163 uint32_t event_mask = 0; 1164 1165 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) 1166 return -1; 1167 1168 stm32_clock_enable(hi2c->clock); 1169 1170 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1171 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1172 goto bail; 1173 1174 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1175 hi2c->i2c_err = I2C_ERROR_NONE; 1176 1177 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1178 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1179 I2C_GENERATE_START_WRITE); 1180 1181 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1182 if (i2c_wait_txis(hi2c, timeout_ref)) 1183 goto bail; 1184 1185 io_write8(base + I2C_TXDR, mem_addr); 1186 1187 if (write) 1188 event_mask = I2C_ISR_TCR; 1189 else 1190 event_mask = I2C_ISR_TC; 1191 1192 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1193 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1194 goto bail; 1195 1196 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1197 I2C_AUTOEND_MODE, 1198 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1199 1200 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1201 if (write) { 1202 if (i2c_wait_txis(hi2c, timeout_ref)) 1203 goto bail; 1204 1205 io_write8(base + I2C_TXDR, *p_buff); 1206 } else { 1207 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1208 goto bail; 1209 1210 *p_buff = io_read8(base + I2C_RXDR); 1211 } 1212 1213 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1214 if (i2c_wait_stop(hi2c, timeout_ref)) 1215 goto bail; 1216 1217 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1218 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1219 1220 hi2c->i2c_state = I2C_STATE_READY; 1221 1222 rc = 0; 1223 1224 bail: 1225 stm32_clock_disable(hi2c->clock); 1226 1227 return rc; 1228 } 1229 1230 /* 1231 * Read an amount of data in blocking mode 1232 * 1233 * @hi2c: Reference to struct i2c_handle_s 1234 * @request: I2C request parameters 1235 * @p_data: Pointer to data buffer 1236 * @size: Amount of data to be sent 1237 * Return 0 on success or a negative value 1238 */ 1239 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1240 uint8_t *p_data, uint32_t size) 1241 { 1242 vaddr_t base = get_base(hi2c); 1243 uint64_t timeout_ref = 0; 1244 int rc = -1; 1245 uint8_t *p_buff = p_data; 1246 size_t xfer_count = size; 1247 size_t xfer_size = 0; 1248 1249 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1250 return -1; 1251 1252 if (hi2c->i2c_state != I2C_STATE_READY) 1253 return -1; 1254 1255 if (!p_data || !size) 1256 return -1; 1257 1258 stm32_clock_enable(hi2c->clock); 1259 1260 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1261 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1262 goto bail; 1263 1264 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1265 hi2c->i2c_err = I2C_ERROR_NONE; 1266 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1267 1268 if (request->mode == I2C_MODE_MEM) { 1269 /* Send memory address */ 1270 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1271 goto bail; 1272 } 1273 1274 /* 1275 * Send slave address. 1276 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1277 * and generate RESTART. 1278 */ 1279 if (xfer_count > MAX_NBYTE_SIZE) { 1280 xfer_size = MAX_NBYTE_SIZE; 1281 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1282 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1283 } else { 1284 xfer_size = xfer_count; 1285 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1286 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1287 } 1288 1289 do { 1290 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1291 goto bail; 1292 1293 *p_buff = io_read8(base + I2C_RXDR); 1294 p_buff++; 1295 xfer_size--; 1296 xfer_count--; 1297 1298 if (xfer_count && !xfer_size) { 1299 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1300 goto bail; 1301 1302 if (xfer_count > MAX_NBYTE_SIZE) { 1303 xfer_size = MAX_NBYTE_SIZE; 1304 i2c_transfer_config(hi2c, request->dev_addr, 1305 xfer_size, 1306 I2C_RELOAD_MODE, 1307 I2C_NO_STARTSTOP); 1308 } else { 1309 xfer_size = xfer_count; 1310 i2c_transfer_config(hi2c, request->dev_addr, 1311 xfer_size, 1312 I2C_AUTOEND_MODE, 1313 I2C_NO_STARTSTOP); 1314 } 1315 } 1316 } while (xfer_count > 0U); 1317 1318 /* 1319 * No need to Check TC flag, with AUTOEND mode the stop 1320 * is automatically generated. 1321 * Wait until STOPF flag is reset. 1322 */ 1323 if (i2c_wait_stop(hi2c, timeout_ref)) 1324 goto bail; 1325 1326 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1327 1328 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1329 1330 hi2c->i2c_state = I2C_STATE_READY; 1331 1332 rc = 0; 1333 1334 bail: 1335 stm32_clock_disable(hi2c->clock); 1336 1337 return rc; 1338 } 1339 1340 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1341 uint32_t mem_addr, uint32_t mem_addr_size, 1342 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1343 { 1344 struct i2c_request request = { 1345 .dev_addr = dev_addr, 1346 .mode = I2C_MODE_MEM, 1347 .mem_addr = mem_addr, 1348 .mem_addr_size = mem_addr_size, 1349 .timeout_ms = timeout_ms, 1350 }; 1351 1352 return i2c_read(hi2c, &request, p_data, size); 1353 } 1354 1355 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1356 uint8_t *p_data, size_t size, 1357 unsigned int timeout_ms) 1358 { 1359 struct i2c_request request = { 1360 .dev_addr = dev_addr, 1361 .mode = I2C_MODE_MASTER, 1362 .timeout_ms = timeout_ms, 1363 }; 1364 1365 return i2c_read(hi2c, &request, p_data, size); 1366 } 1367 1368 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1369 unsigned int trials, unsigned int timeout_ms) 1370 { 1371 vaddr_t base = get_base(hi2c); 1372 unsigned int i2c_trials = 0U; 1373 bool rc = false; 1374 1375 if (hi2c->i2c_state != I2C_STATE_READY) 1376 return rc; 1377 1378 stm32_clock_enable(hi2c->clock); 1379 1380 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1381 goto bail; 1382 1383 hi2c->i2c_state = I2C_STATE_BUSY; 1384 hi2c->i2c_err = I2C_ERROR_NONE; 1385 1386 do { 1387 uint64_t timeout_ref = 0; 1388 vaddr_t isr = base + I2C_ISR; 1389 1390 /* Generate Start */ 1391 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1392 io_write32(base + I2C_CR2, 1393 ((dev_addr & I2C_CR2_SADD) | 1394 I2C_CR2_START | I2C_CR2_AUTOEND) & 1395 ~I2C_CR2_RD_WRN); 1396 else 1397 io_write32(base + I2C_CR2, 1398 ((dev_addr & I2C_CR2_SADD) | 1399 I2C_CR2_START | I2C_CR2_ADD10) & 1400 ~I2C_CR2_RD_WRN); 1401 1402 /* 1403 * No need to Check TC flag, with AUTOEND mode the stop 1404 * is automatically generated. 1405 * Wait until STOPF flag is set or a NACK flag is set. 1406 */ 1407 timeout_ref = timeout_init_us(timeout_ms * 1000); 1408 while (!timeout_elapsed(timeout_ref)) 1409 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1410 break; 1411 1412 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1413 notif_i2c_timeout(hi2c); 1414 goto bail; 1415 } 1416 1417 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1418 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1419 goto bail; 1420 1421 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1422 1423 hi2c->i2c_state = I2C_STATE_READY; 1424 1425 rc = true; 1426 goto bail; 1427 } 1428 1429 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1430 goto bail; 1431 1432 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1433 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1434 1435 if (i2c_trials == trials) { 1436 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1437 1438 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1439 goto bail; 1440 1441 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1442 } 1443 1444 i2c_trials++; 1445 } while (i2c_trials < trials); 1446 1447 notif_i2c_timeout(hi2c); 1448 1449 bail: 1450 stm32_clock_disable(hi2c->clock); 1451 1452 return rc; 1453 } 1454 1455 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1456 { 1457 if (hi2c->i2c_state == I2C_STATE_READY) 1458 return; 1459 1460 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1461 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1462 panic(); 1463 1464 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1465 1466 if (hi2c->i2c_state == I2C_STATE_RESET) { 1467 /* There is no valid I2C configuration to be loaded yet */ 1468 return; 1469 } 1470 1471 restore_cfg(hi2c, &hi2c->sec_cfg); 1472 1473 hi2c->i2c_state = I2C_STATE_READY; 1474 } 1475 1476 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1477 { 1478 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1479 return; 1480 1481 if (hi2c->i2c_state != I2C_STATE_READY) 1482 panic(); 1483 1484 save_cfg(hi2c, &hi2c->sec_cfg); 1485 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1486 1487 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1488 } 1489