1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000L 157 #define I2C_TIMEOUT_BUSY_MS 25U 158 159 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 160 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 161 I2C_CR2_RD_WRN) 162 163 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 164 I2C_TIMINGR_SDADEL | \ 165 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 166 167 /* 168 * I2C transfer modes 169 * I2C_RELOAD: Enable Reload mode 170 * I2C_AUTOEND_MODE: Enable automatic end mode 171 * I2C_SOFTEND_MODE: Enable software end mode 172 */ 173 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 174 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 175 #define I2C_SOFTEND_MODE 0x0 176 177 /* 178 * Start/restart/stop I2C transfer requests. 179 * 180 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 181 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 182 * I2C_GENERATE_START_READ: Generate Restart for read request. 183 * I2C_GENERATE_START_WRITE: Generate Restart for write request 184 */ 185 #define I2C_NO_STARTSTOP 0x0 186 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 187 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 188 I2C_CR2_RD_WRN) 189 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 190 191 /* Memory address byte sizes */ 192 #define I2C_MEMADD_SIZE_8BIT 1 193 #define I2C_MEMADD_SIZE_16BIT 2 194 195 /* 196 * struct i2c_spec_s - Private I2C timing specifications. 197 * @rate: I2C bus speed (Hz) 198 * @rate_min: 80% of I2C bus speed (Hz) 199 * @rate_max: 120% of I2C bus speed (Hz) 200 * @fall_max: Max fall time of both SDA and SCL signals (ns) 201 * @rise_max: Max rise time of both SDA and SCL signals (ns) 202 * @hddat_min: Min data hold time (ns) 203 * @vddat_max: Max data valid time (ns) 204 * @sudat_min: Min data setup time (ns) 205 * @l_min: Min low period of the SCL clock (ns) 206 * @h_min: Min high period of the SCL clock (ns) 207 */ 208 struct i2c_spec_s { 209 uint32_t rate; 210 uint32_t rate_min; 211 uint32_t rate_max; 212 uint32_t fall_max; 213 uint32_t rise_max; 214 uint32_t hddat_min; 215 uint32_t vddat_max; 216 uint32_t sudat_min; 217 uint32_t l_min; 218 uint32_t h_min; 219 }; 220 221 /* 222 * struct i2c_timing_s - Private I2C output parameters. 223 * @scldel: Data setup time 224 * @sdadel: Data hold time 225 * @sclh: SCL high period (master mode) 226 * @sclh: SCL low period (master mode) 227 * @is_saved: True if relating to a configuration candidate 228 */ 229 struct i2c_timing_s { 230 uint8_t scldel; 231 uint8_t sdadel; 232 uint8_t sclh; 233 uint8_t scll; 234 bool is_saved; 235 }; 236 237 static const struct i2c_spec_s i2c_specs[] = { 238 [I2C_SPEED_STANDARD] = { 239 .rate = I2C_STANDARD_RATE, 240 .rate_min = (I2C_STANDARD_RATE * 80) / 100, 241 .rate_max = (I2C_STANDARD_RATE * 120) / 100, 242 .fall_max = 300, 243 .rise_max = 1000, 244 .hddat_min = 0, 245 .vddat_max = 3450, 246 .sudat_min = 250, 247 .l_min = 4700, 248 .h_min = 4000, 249 }, 250 [I2C_SPEED_FAST] = { 251 .rate = I2C_FAST_RATE, 252 .rate_min = (I2C_FAST_RATE * 80) / 100, 253 .rate_max = (I2C_FAST_RATE * 120) / 100, 254 .fall_max = 300, 255 .rise_max = 300, 256 .hddat_min = 0, 257 .vddat_max = 900, 258 .sudat_min = 100, 259 .l_min = 1300, 260 .h_min = 600, 261 }, 262 [I2C_SPEED_FAST_PLUS] = { 263 .rate = I2C_FAST_PLUS_RATE, 264 .rate_min = (I2C_FAST_PLUS_RATE * 80) / 100, 265 .rate_max = (I2C_FAST_PLUS_RATE * 120) / 100, 266 .fall_max = 100, 267 .rise_max = 120, 268 .hddat_min = 0, 269 .vddat_max = 450, 270 .sudat_min = 50, 271 .l_min = 500, 272 .h_min = 260, 273 }, 274 }; 275 276 /* 277 * I2C request parameters 278 * @dev_addr: I2C address of the target device 279 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 280 * @mem_addr: Target memory cell accessed in device (memory mode) 281 * @mem_addr_size: Byte size of the memory cell address (memory mode) 282 * @timeout_ms: Timeout in millisenconds for the request 283 */ 284 struct i2c_request { 285 uint32_t dev_addr; 286 enum i2c_mode_e mode; 287 uint32_t mem_addr; 288 uint32_t mem_addr_size; 289 unsigned int timeout_ms; 290 }; 291 292 static vaddr_t get_base(struct i2c_handle_s *hi2c) 293 { 294 return io_pa_or_va_secure(&hi2c->base); 295 } 296 297 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 298 { 299 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 300 hi2c->i2c_state = I2C_STATE_READY; 301 } 302 303 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 304 { 305 vaddr_t base = get_base(hi2c); 306 307 stm32_clock_enable(hi2c->clock); 308 309 cfg->cr1 = io_read32(base + I2C_CR1); 310 cfg->cr2 = io_read32(base + I2C_CR2); 311 cfg->oar1 = io_read32(base + I2C_OAR1); 312 cfg->oar2 = io_read32(base + I2C_OAR2); 313 cfg->timingr = io_read32(base + I2C_TIMINGR); 314 315 stm32_clock_disable(hi2c->clock); 316 } 317 318 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 319 { 320 vaddr_t base = get_base(hi2c); 321 322 stm32_clock_enable(hi2c->clock); 323 324 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 325 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 326 io_write32(base + I2C_OAR1, cfg->oar1); 327 io_write32(base + I2C_CR2, cfg->cr2); 328 io_write32(base + I2C_OAR2, cfg->oar2); 329 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 330 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 331 332 stm32_clock_disable(hi2c->clock); 333 } 334 335 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 336 { 337 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 338 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 339 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 340 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 341 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 342 } 343 344 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 345 { 346 vaddr_t __maybe_unused base = get_base(hi2c); 347 348 stm32_clock_enable(hi2c->clock); 349 350 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 351 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 352 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 353 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 354 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 355 356 stm32_clock_disable(hi2c->clock); 357 } 358 359 /* 360 * Compute the I2C device timings 361 * 362 * @init: Ref to the initialization configuration structure 363 * @clock_src: I2C clock source frequency (Hz) 364 * @timing: Pointer to the final computed timing result 365 * Return 0 on success or a negative value 366 */ 367 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 368 uint32_t clock_src, uint32_t *timing) 369 { 370 enum i2c_speed_e mode = init->speed_mode; 371 uint32_t speed_freq = i2c_specs[mode].rate; 372 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 373 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 374 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 375 uint32_t af_delay_min = 0; 376 uint32_t af_delay_max = 0; 377 uint32_t dnf_delay = 0; 378 uint32_t tsync = 0; 379 uint32_t clk_min = 0; 380 uint32_t clk_max = 0; 381 int clk_error_prev = 0; 382 uint16_t p = 0; 383 uint16_t l = 0; 384 uint16_t a = 0; 385 uint16_t h = 0; 386 unsigned int sdadel_min = 0; 387 unsigned int sdadel_max = 0; 388 unsigned int scldel_min = 0; 389 unsigned int delay = 0; 390 int s = -1; 391 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 392 393 switch (mode) { 394 case I2C_SPEED_STANDARD: 395 case I2C_SPEED_FAST: 396 case I2C_SPEED_FAST_PLUS: 397 break; 398 default: 399 EMSG("I2C speed out of bound {%d/%d}", 400 mode, I2C_SPEED_FAST_PLUS); 401 return -1; 402 } 403 404 speed_freq = i2c_specs[mode].rate; 405 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 406 clk_error_prev = INT_MAX; 407 408 if ((init->rise_time > i2c_specs[mode].rise_max) || 409 (init->fall_time > i2c_specs[mode].fall_max)) { 410 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 411 init->rise_time, i2c_specs[mode].rise_max, 412 init->fall_time, i2c_specs[mode].fall_max); 413 return -1; 414 } 415 416 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 417 EMSG("DNF out of bound %d/%d", 418 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 419 return -1; 420 } 421 422 /* Analog and Digital Filters */ 423 if (init->analog_filter) { 424 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 425 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 426 } 427 dnf_delay = init->digital_filter_coef * i2cclk; 428 429 sdadel_min = i2c_specs[mode].hddat_min + init->fall_time; 430 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 431 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 432 sdadel_min = 0; 433 434 sdadel_max = i2c_specs[mode].vddat_max - init->rise_time; 435 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 436 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 437 sdadel_max = 0; 438 439 scldel_min = init->rise_time + i2c_specs[mode].sudat_min; 440 441 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 442 sdadel_min, sdadel_max, scldel_min); 443 444 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 445 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 446 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 447 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 448 449 if (scldel < scldel_min) 450 continue; 451 452 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 453 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 454 455 if ((sdadel >= sdadel_min) && 456 (sdadel <= sdadel_max) && 457 (p != p_prev)) { 458 solutions[p].scldel = l; 459 solutions[p].sdadel = a; 460 solutions[p].is_saved = true; 461 p_prev = p; 462 break; 463 } 464 } 465 466 if (p_prev == p) 467 break; 468 } 469 } 470 471 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 472 EMSG(" I2C no Prescaler solution"); 473 return -1; 474 } 475 476 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 477 clk_max = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_min; 478 clk_min = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_max; 479 480 /* 481 * Among prescaler possibilities discovered above figures out SCL Low 482 * and High Period. Provided: 483 * - SCL Low Period has to be higher than Low Period of the SCL Clock 484 * defined by I2C Specification. I2C Clock has to be lower than 485 * (SCL Low Period - Analog/Digital filters) / 4. 486 * - SCL High Period has to be lower than High Period of the SCL Clock 487 * defined by I2C Specification. 488 * - I2C Clock has to be lower than SCL High Period. 489 */ 490 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 491 uint32_t prescaler = (p + 1) * i2cclk; 492 493 if (!solutions[p].is_saved) 494 continue; 495 496 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 497 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 498 499 if ((tscl_l < i2c_specs[mode].l_min) || 500 (i2cclk >= 501 ((tscl_l - af_delay_min - dnf_delay) / 4))) 502 continue; 503 504 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 505 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 506 uint32_t tscl = tscl_l + tscl_h + 507 init->rise_time + 508 init->fall_time; 509 510 if ((tscl >= clk_min) && (tscl <= clk_max) && 511 (tscl_h >= i2c_specs[mode].h_min) && 512 (i2cclk < tscl_h)) { 513 int clk_error = tscl - i2cbus; 514 515 if (clk_error < 0) 516 clk_error = -clk_error; 517 518 if (clk_error < clk_error_prev) { 519 clk_error_prev = clk_error; 520 solutions[p].scll = l; 521 solutions[p].sclh = h; 522 s = p; 523 } 524 } 525 } 526 } 527 } 528 529 if (s < 0) { 530 EMSG(" I2C no solution at all"); 531 return -1; 532 } 533 534 /* Finalize timing settings */ 535 *timing = I2C_SET_TIMINGR_PRESC(s) | 536 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 537 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 538 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 539 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 540 541 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 542 s, solutions[s].scldel, solutions[s].sdadel); 543 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 544 solutions[s].sclh, solutions[s].scll); 545 DMSG("I2C TIMINGR: 0x%x", *timing); 546 547 return 0; 548 } 549 550 /* 551 * Setup the I2C device timings 552 * 553 * @hi2c: I2C handle structure 554 * @init: Ref to the initialization configuration structure 555 * @timing: Output TIMINGR register configuration value 556 * @retval 0 if OK, negative value else 557 */ 558 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 559 struct stm32_i2c_init_s *init, 560 uint32_t *timing) 561 { 562 int rc = 0; 563 uint32_t clock_src = stm32_clock_get_rate(hi2c->clock); 564 565 if (!clock_src) { 566 EMSG("Null I2C clock rate"); 567 return -1; 568 } 569 570 do { 571 rc = i2c_compute_timing(init, clock_src, timing); 572 if (rc) { 573 EMSG("Failed to compute I2C timings"); 574 if (init->speed_mode > I2C_SPEED_STANDARD) { 575 init->speed_mode--; 576 IMSG("Downgrade I2C speed to %uHz)", 577 i2c_specs[init->speed_mode].rate); 578 } else { 579 break; 580 } 581 } 582 } while (rc); 583 584 if (rc) { 585 EMSG("Impossible to compute I2C timings"); 586 return rc; 587 } 588 589 DMSG("I2C Speed Mode(%i), Freq(%i), Clk Source(%i)", 590 init->speed_mode, i2c_specs[init->speed_mode].rate, clock_src); 591 DMSG("I2C Rise(%i) and Fall(%i) Time", 592 init->rise_time, init->fall_time); 593 DMSG("I2C Analog Filter(%s), DNF(%i)", 594 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 595 596 return 0; 597 } 598 599 /* 600 * Configure I2C Analog noise filter. 601 * @hi2c: I2C handle structure 602 * @analog_filter_on: True if enabling analog filter, false otherwise 603 * Return 0 on success or a negative value 604 */ 605 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 606 bool analog_filter_on) 607 { 608 vaddr_t base = get_base(hi2c); 609 610 if (hi2c->i2c_state != I2C_STATE_READY) 611 return -1; 612 613 hi2c->i2c_state = I2C_STATE_BUSY; 614 615 /* Disable the selected I2C peripheral */ 616 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 617 618 /* Reset I2Cx ANOFF bit */ 619 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 620 621 /* Set analog filter bit if filter is disabled */ 622 if (!analog_filter_on) 623 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 624 625 /* Enable the selected I2C peripheral */ 626 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 627 628 hi2c->i2c_state = I2C_STATE_READY; 629 630 return 0; 631 } 632 633 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 634 struct stm32_i2c_init_s *init, 635 struct stm32_pinctrl **pinctrl, 636 size_t *pinctrl_count) 637 { 638 const fdt32_t *cuint = NULL; 639 struct dt_node_info info = { .status = 0 }; 640 int count = 0; 641 642 /* Default STM32 specific configs caller may need to overwrite */ 643 memset(init, 0, sizeof(*init)); 644 645 _fdt_fill_device_info(fdt, &info, node); 646 init->pbase = info.reg; 647 init->clock = info.clock; 648 assert(info.reg != DT_INFO_INVALID_REG && 649 info.clock != DT_INFO_INVALID_CLOCK); 650 651 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 652 if (cuint) 653 init->rise_time = fdt32_to_cpu(*cuint); 654 else 655 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 656 657 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 658 if (cuint) 659 init->fall_time = fdt32_to_cpu(*cuint); 660 else 661 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 662 663 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 664 if (cuint) { 665 switch (fdt32_to_cpu(*cuint)) { 666 case I2C_STANDARD_RATE: 667 init->speed_mode = I2C_SPEED_STANDARD; 668 break; 669 case I2C_FAST_RATE: 670 init->speed_mode = I2C_SPEED_FAST; 671 break; 672 case I2C_FAST_PLUS_RATE: 673 init->speed_mode = I2C_SPEED_FAST_PLUS; 674 break; 675 default: 676 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 677 break; 678 } 679 } else { 680 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 681 } 682 683 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 684 if (count <= 0) { 685 *pinctrl = NULL; 686 *pinctrl_count = 0; 687 return count; 688 } 689 690 if (count > 2) 691 panic("Too many PINCTRLs found"); 692 693 *pinctrl = calloc(count, sizeof(**pinctrl)); 694 if (!*pinctrl) 695 panic(); 696 697 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 698 *pinctrl, count); 699 assert(*pinctrl_count == (unsigned int)count); 700 701 return 0; 702 } 703 704 int stm32_i2c_init(struct i2c_handle_s *hi2c, 705 struct stm32_i2c_init_s *init_data) 706 { 707 int rc = 0; 708 uint32_t timing = 0; 709 vaddr_t base = 0; 710 uint32_t val = 0; 711 712 hi2c->base.pa = init_data->pbase; 713 hi2c->clock = init_data->clock; 714 715 rc = i2c_setup_timing(hi2c, init_data, &timing); 716 if (rc) 717 return rc; 718 719 stm32_clock_enable(hi2c->clock); 720 base = get_base(hi2c); 721 hi2c->i2c_state = I2C_STATE_BUSY; 722 723 /* Disable the selected I2C peripheral */ 724 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 725 726 /* Configure I2Cx: Frequency range */ 727 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 728 729 /* Disable Own Address1 before set the Own Address1 configuration */ 730 io_write32(base + I2C_OAR1, 0); 731 732 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 733 if (init_data->addr_mode_10b_not_7b) 734 io_write32(base + I2C_OAR1, 735 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 736 init_data->own_address1); 737 else 738 io_write32(base + I2C_OAR1, 739 I2C_OAR1_OA1EN | init_data->own_address1); 740 741 /* Configure I2Cx: Addressing Master mode */ 742 io_write32(base + I2C_CR2, 0); 743 if (init_data->addr_mode_10b_not_7b) 744 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 745 746 /* 747 * Enable the AUTOEND by default, and enable NACK 748 * (should be disabled only during Slave process). 749 */ 750 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 751 752 /* Disable Own Address2 before set the Own Address2 configuration */ 753 io_write32(base + I2C_OAR2, 0); 754 755 /* Configure I2Cx: Dual mode and Own Address2 */ 756 if (init_data->dual_address_mode) 757 io_write32(base + I2C_OAR2, 758 I2C_OAR2_OA2EN | init_data->own_address2 | 759 (init_data->own_address2_masks << 8)); 760 761 /* Configure I2Cx: Generalcall and NoStretch mode */ 762 val = 0; 763 if (init_data->general_call_mode) 764 val |= I2C_CR1_GCEN; 765 if (init_data->no_stretch_mode) 766 val |= I2C_CR1_NOSTRETCH; 767 io_write32(base + I2C_CR1, val); 768 769 /* Enable the selected I2C peripheral */ 770 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 771 772 hi2c->i2c_err = I2C_ERROR_NONE; 773 hi2c->i2c_state = I2C_STATE_READY; 774 775 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 776 if (rc) 777 EMSG("I2C analog filter error %d", rc); 778 779 stm32_clock_disable(hi2c->clock); 780 781 return rc; 782 } 783 784 /* I2C transmit (TX) data register flush sequence */ 785 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 786 { 787 vaddr_t base = get_base(hi2c); 788 789 /* 790 * If a pending TXIS flag is set, 791 * write a dummy data in TXDR to clear it. 792 */ 793 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 794 io_write32(base + I2C_TXDR, 0); 795 796 /* Flush TX register if not empty */ 797 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 798 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 799 } 800 801 /* 802 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 803 * 804 * @hi2c: I2C handle structure 805 * @bit_mask: Bit mask for the target single bit position to consider 806 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 807 * @timeout_ref: Expriation timeout reference 808 * Return 0 on success and a non-zero value on timeout 809 */ 810 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 811 unsigned int awaited_value, uint64_t timeout_ref) 812 { 813 vaddr_t isr = get_base(hi2c) + I2C_ISR; 814 815 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 816 817 /* May timeout while TEE thread is suspended */ 818 while (!timeout_elapsed(timeout_ref)) 819 if (!!(io_read32(isr) & bit_mask) == awaited_value) 820 break; 821 822 if (!!(io_read32(isr) & bit_mask) == awaited_value) 823 return 0; 824 825 notif_i2c_timeout(hi2c); 826 return -1; 827 } 828 829 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 830 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 831 { 832 vaddr_t base = get_base(hi2c); 833 834 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 835 return 0; 836 837 /* 838 * Wait until STOP Flag is reset. Use polling method. 839 * AutoEnd should be initiate after AF. 840 * Timeout may elpased while TEE thread is suspended. 841 */ 842 while (!timeout_elapsed(timeout_ref)) 843 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 844 break; 845 846 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 847 notif_i2c_timeout(hi2c); 848 return -1; 849 } 850 851 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 852 853 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 854 855 i2c_flush_txdr(hi2c); 856 857 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 858 859 hi2c->i2c_err |= I2C_ERROR_ACKF; 860 hi2c->i2c_state = I2C_STATE_READY; 861 862 return -1; 863 } 864 865 /* Wait TXIS bit is 1 in I2C_ISR register */ 866 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 867 { 868 while (!timeout_elapsed(timeout_ref)) { 869 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 870 break; 871 if (i2c_ack_failed(hi2c, timeout_ref)) 872 return -1; 873 } 874 875 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 876 return 0; 877 878 if (i2c_ack_failed(hi2c, timeout_ref)) 879 return -1; 880 881 notif_i2c_timeout(hi2c); 882 return -1; 883 } 884 885 /* Wait STOPF bit is 1 in I2C_ISR register */ 886 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 887 { 888 while (!timeout_elapsed(timeout_ref)) { 889 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 890 break; 891 892 if (i2c_ack_failed(hi2c, timeout_ref)) 893 return -1; 894 } 895 896 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 897 return 0; 898 899 if (i2c_ack_failed(hi2c, timeout_ref)) 900 return -1; 901 902 notif_i2c_timeout(hi2c); 903 return -1; 904 } 905 906 /* 907 * Load I2C_CR2 register for a I2C transfer 908 * 909 * @hi2c: I2C handle structure 910 * @dev_addr: Slave address to be transferred 911 * @size: Number of bytes to be transferred 912 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 913 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 914 * I2C_GENERATE_START_{READ|WRITE} 915 */ 916 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 917 uint32_t size, uint32_t i2c_mode, 918 uint32_t startstop) 919 { 920 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 921 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 922 (I2C_CR2_RD_WRN & 923 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 924 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 925 ((size << I2C_CR2_NBYTES_OFFSET) & 926 I2C_CR2_NBYTES) | 927 i2c_mode | startstop; 928 929 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 930 } 931 932 /* 933 * Master sends target device address followed by internal memory 934 * address for a memory write request. 935 * Function returns 0 on success or a negative value. 936 */ 937 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 938 struct i2c_request *request, 939 uint64_t timeout_ref) 940 { 941 vaddr_t base = get_base(hi2c); 942 943 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 944 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 945 946 if (i2c_wait_txis(hi2c, timeout_ref)) 947 return -1; 948 949 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 950 /* Send memory address */ 951 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 952 } else { 953 /* Send MSB of memory address */ 954 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 955 956 if (i2c_wait_txis(hi2c, timeout_ref)) 957 return -1; 958 959 /* Send LSB of memory address */ 960 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 961 } 962 963 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 964 return -1; 965 966 return 0; 967 } 968 969 /* 970 * Master sends target device address followed by internal memory 971 * address to prepare a memory read request. 972 * Function returns 0 on success or a negative value. 973 */ 974 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 975 struct i2c_request *request, 976 uint64_t timeout_ref) 977 { 978 vaddr_t base = get_base(hi2c); 979 980 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 981 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 982 983 if (i2c_wait_txis(hi2c, timeout_ref)) 984 return -1; 985 986 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 987 /* Send memory address */ 988 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 989 } else { 990 /* Send MSB of memory address */ 991 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 992 993 if (i2c_wait_txis(hi2c, timeout_ref)) 994 return -1; 995 996 /* Send LSB of memory address */ 997 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 998 } 999 1000 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1001 return -1; 1002 1003 return 0; 1004 } 1005 1006 /* 1007 * Write an amount of data in blocking mode 1008 * 1009 * @hi2c: Reference to struct i2c_handle_s 1010 * @request: I2C request parameters 1011 * @p_data: Pointer to data buffer 1012 * @size: Amount of data to be sent 1013 * Return 0 on success or a negative value 1014 */ 1015 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1016 uint8_t *p_data, uint16_t size) 1017 { 1018 uint64_t timeout_ref = 0; 1019 vaddr_t base = get_base(hi2c); 1020 int rc = -1; 1021 uint8_t *p_buff = p_data; 1022 size_t xfer_size = 0; 1023 size_t xfer_count = size; 1024 1025 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1026 return -1; 1027 1028 if (hi2c->i2c_state != I2C_STATE_READY) 1029 return -1; 1030 1031 if (!p_data || !size) 1032 return -1; 1033 1034 stm32_clock_enable(hi2c->clock); 1035 1036 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1037 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1038 goto bail; 1039 1040 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1041 hi2c->i2c_err = I2C_ERROR_NONE; 1042 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1043 1044 if (request->mode == I2C_MODE_MEM) { 1045 /* In memory mode, send slave address and memory address */ 1046 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1047 goto bail; 1048 1049 if (xfer_count > MAX_NBYTE_SIZE) { 1050 xfer_size = MAX_NBYTE_SIZE; 1051 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1052 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1053 } else { 1054 xfer_size = xfer_count; 1055 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1056 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1057 } 1058 } else { 1059 /* In master mode, send slave address */ 1060 if (xfer_count > MAX_NBYTE_SIZE) { 1061 xfer_size = MAX_NBYTE_SIZE; 1062 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1063 I2C_RELOAD_MODE, 1064 I2C_GENERATE_START_WRITE); 1065 } else { 1066 xfer_size = xfer_count; 1067 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1068 I2C_AUTOEND_MODE, 1069 I2C_GENERATE_START_WRITE); 1070 } 1071 } 1072 1073 do { 1074 if (i2c_wait_txis(hi2c, timeout_ref)) 1075 goto bail; 1076 1077 io_write8(base + I2C_TXDR, *p_buff); 1078 p_buff++; 1079 xfer_count--; 1080 xfer_size--; 1081 1082 if (xfer_count && !xfer_size) { 1083 /* Wait until TCR flag is set */ 1084 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1085 goto bail; 1086 1087 if (xfer_count > MAX_NBYTE_SIZE) { 1088 xfer_size = MAX_NBYTE_SIZE; 1089 i2c_transfer_config(hi2c, request->dev_addr, 1090 xfer_size, 1091 I2C_RELOAD_MODE, 1092 I2C_NO_STARTSTOP); 1093 } else { 1094 xfer_size = xfer_count; 1095 i2c_transfer_config(hi2c, request->dev_addr, 1096 xfer_size, 1097 I2C_AUTOEND_MODE, 1098 I2C_NO_STARTSTOP); 1099 } 1100 } 1101 1102 } while (xfer_count > 0U); 1103 1104 /* 1105 * No need to Check TC flag, with AUTOEND mode the stop 1106 * is automatically generated. 1107 * Wait until STOPF flag is reset. 1108 */ 1109 if (i2c_wait_stop(hi2c, timeout_ref)) 1110 goto bail; 1111 1112 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1113 1114 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1115 1116 hi2c->i2c_state = I2C_STATE_READY; 1117 1118 rc = 0; 1119 1120 bail: 1121 stm32_clock_disable(hi2c->clock); 1122 1123 return rc; 1124 } 1125 1126 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1127 uint32_t mem_addr, uint32_t mem_addr_size, 1128 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1129 { 1130 struct i2c_request request = { 1131 .dev_addr = dev_addr, 1132 .mode = I2C_MODE_MEM, 1133 .mem_addr = mem_addr, 1134 .mem_addr_size = mem_addr_size, 1135 .timeout_ms = timeout_ms, 1136 }; 1137 1138 return i2c_write(hi2c, &request, p_data, size); 1139 } 1140 1141 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1142 uint8_t *p_data, size_t size, 1143 unsigned int timeout_ms) 1144 { 1145 struct i2c_request request = { 1146 .dev_addr = dev_addr, 1147 .mode = I2C_MODE_MASTER, 1148 .timeout_ms = timeout_ms, 1149 }; 1150 1151 return i2c_write(hi2c, &request, p_data, size); 1152 } 1153 1154 /* 1155 * Read an amount of data in blocking mode 1156 * 1157 * @hi2c: Reference to struct i2c_handle_s 1158 * @request: I2C request parameters 1159 * @p_data: Pointer to data buffer 1160 * @size: Amount of data to be sent 1161 * Return 0 on success or a negative value 1162 */ 1163 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1164 uint8_t *p_data, uint32_t size) 1165 { 1166 vaddr_t base = get_base(hi2c); 1167 uint64_t timeout_ref = 0; 1168 int rc = -1; 1169 uint8_t *p_buff = p_data; 1170 size_t xfer_count = size; 1171 size_t xfer_size = 0; 1172 1173 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1174 return -1; 1175 1176 if (hi2c->i2c_state != I2C_STATE_READY) 1177 return -1; 1178 1179 if (!p_data || !size) 1180 return -1; 1181 1182 stm32_clock_enable(hi2c->clock); 1183 1184 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1185 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1186 goto bail; 1187 1188 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1189 hi2c->i2c_err = I2C_ERROR_NONE; 1190 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1191 1192 if (request->mode == I2C_MODE_MEM) { 1193 /* Send memory address */ 1194 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1195 goto bail; 1196 } 1197 1198 /* 1199 * Send slave address. 1200 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1201 * and generate RESTART. 1202 */ 1203 if (xfer_count > MAX_NBYTE_SIZE) { 1204 xfer_size = MAX_NBYTE_SIZE; 1205 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1206 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1207 } else { 1208 xfer_size = xfer_count; 1209 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1210 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1211 } 1212 1213 do { 1214 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1215 goto bail; 1216 1217 *p_buff = io_read8(base + I2C_RXDR); 1218 p_buff++; 1219 xfer_size--; 1220 xfer_count--; 1221 1222 if (xfer_count && !xfer_size) { 1223 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1224 goto bail; 1225 1226 if (xfer_count > MAX_NBYTE_SIZE) { 1227 xfer_size = MAX_NBYTE_SIZE; 1228 i2c_transfer_config(hi2c, request->dev_addr, 1229 xfer_size, 1230 I2C_RELOAD_MODE, 1231 I2C_NO_STARTSTOP); 1232 } else { 1233 xfer_size = xfer_count; 1234 i2c_transfer_config(hi2c, request->dev_addr, 1235 xfer_size, 1236 I2C_AUTOEND_MODE, 1237 I2C_NO_STARTSTOP); 1238 } 1239 } 1240 } while (xfer_count > 0U); 1241 1242 /* 1243 * No need to Check TC flag, with AUTOEND mode the stop 1244 * is automatically generated. 1245 * Wait until STOPF flag is reset. 1246 */ 1247 if (i2c_wait_stop(hi2c, timeout_ref)) 1248 goto bail; 1249 1250 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1251 1252 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1253 1254 hi2c->i2c_state = I2C_STATE_READY; 1255 1256 rc = 0; 1257 1258 bail: 1259 stm32_clock_disable(hi2c->clock); 1260 1261 return rc; 1262 } 1263 1264 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1265 uint32_t mem_addr, uint32_t mem_addr_size, 1266 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1267 { 1268 struct i2c_request request = { 1269 .dev_addr = dev_addr, 1270 .mode = I2C_MODE_MEM, 1271 .mem_addr = mem_addr, 1272 .mem_addr_size = mem_addr_size, 1273 .timeout_ms = timeout_ms, 1274 }; 1275 1276 return i2c_read(hi2c, &request, p_data, size); 1277 } 1278 1279 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1280 uint8_t *p_data, size_t size, 1281 unsigned int timeout_ms) 1282 { 1283 struct i2c_request request = { 1284 .dev_addr = dev_addr, 1285 .mode = I2C_MODE_MASTER, 1286 .timeout_ms = timeout_ms, 1287 }; 1288 1289 return i2c_read(hi2c, &request, p_data, size); 1290 } 1291 1292 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1293 unsigned int trials, unsigned int timeout_ms) 1294 { 1295 vaddr_t base = get_base(hi2c); 1296 unsigned int i2c_trials = 0U; 1297 bool rc = false; 1298 1299 if (hi2c->i2c_state != I2C_STATE_READY) 1300 return rc; 1301 1302 stm32_clock_enable(hi2c->clock); 1303 1304 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1305 goto bail; 1306 1307 hi2c->i2c_state = I2C_STATE_BUSY; 1308 hi2c->i2c_err = I2C_ERROR_NONE; 1309 1310 do { 1311 uint64_t timeout_ref = 0; 1312 vaddr_t isr = base + I2C_ISR; 1313 1314 /* Generate Start */ 1315 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1316 io_write32(base + I2C_CR2, 1317 ((dev_addr & I2C_CR2_SADD) | 1318 I2C_CR2_START | I2C_CR2_AUTOEND) & 1319 ~I2C_CR2_RD_WRN); 1320 else 1321 io_write32(base + I2C_CR2, 1322 ((dev_addr & I2C_CR2_SADD) | 1323 I2C_CR2_START | I2C_CR2_ADD10) & 1324 ~I2C_CR2_RD_WRN); 1325 1326 /* 1327 * No need to Check TC flag, with AUTOEND mode the stop 1328 * is automatically generated. 1329 * Wait until STOPF flag is set or a NACK flag is set. 1330 */ 1331 timeout_ref = timeout_init_us(timeout_ms * 1000); 1332 while (!timeout_elapsed(timeout_ref)) 1333 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1334 break; 1335 1336 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1337 notif_i2c_timeout(hi2c); 1338 goto bail; 1339 } 1340 1341 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1342 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1343 goto bail; 1344 1345 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1346 1347 hi2c->i2c_state = I2C_STATE_READY; 1348 1349 rc = true; 1350 goto bail; 1351 } 1352 1353 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1354 goto bail; 1355 1356 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1357 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1358 1359 if (i2c_trials == trials) { 1360 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1361 1362 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1363 goto bail; 1364 1365 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1366 } 1367 1368 i2c_trials++; 1369 } while (i2c_trials < trials); 1370 1371 notif_i2c_timeout(hi2c); 1372 1373 bail: 1374 stm32_clock_disable(hi2c->clock); 1375 1376 return rc; 1377 } 1378 1379 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1380 { 1381 if (hi2c->i2c_state == I2C_STATE_READY) 1382 return; 1383 1384 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1385 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1386 panic(); 1387 1388 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1389 1390 if (hi2c->i2c_state == I2C_STATE_RESET) { 1391 /* There is no valid I2C configuration to be loaded yet */ 1392 return; 1393 } 1394 1395 restore_cfg(hi2c, &hi2c->sec_cfg); 1396 1397 hi2c->i2c_state = I2C_STATE_READY; 1398 } 1399 1400 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1401 { 1402 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1403 return; 1404 1405 if (hi2c->i2c_state != I2C_STATE_READY) 1406 panic(); 1407 1408 save_cfg(hi2c, &hi2c->sec_cfg); 1409 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1410 1411 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1412 } 1413