1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000UL 157 #define I2C_TIMEOUT_BUSY_MS 25 158 #define I2C_TIMEOUT_BUSY_US (I2C_TIMEOUT_BUSY_MS * 1000) 159 160 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 161 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 162 I2C_CR2_RD_WRN) 163 164 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 165 I2C_TIMINGR_SDADEL | \ 166 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 167 168 /* 169 * I2C transfer modes 170 * I2C_RELOAD: Enable Reload mode 171 * I2C_AUTOEND_MODE: Enable automatic end mode 172 * I2C_SOFTEND_MODE: Enable software end mode 173 */ 174 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 175 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 176 #define I2C_SOFTEND_MODE 0x0 177 178 /* 179 * Start/restart/stop I2C transfer requests. 180 * 181 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 182 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 183 * I2C_GENERATE_START_READ: Generate Restart for read request. 184 * I2C_GENERATE_START_WRITE: Generate Restart for write request 185 */ 186 #define I2C_NO_STARTSTOP 0x0 187 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 188 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 189 I2C_CR2_RD_WRN) 190 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 191 192 /* Memory address byte sizes */ 193 #define I2C_MEMADD_SIZE_8BIT 1 194 #define I2C_MEMADD_SIZE_16BIT 2 195 196 /* Effective rate cannot be lower than 80% target rate */ 197 #define RATE_MIN(rate) (((rate) * 80U) / 100U) 198 199 /* 200 * struct i2c_spec_s - Private I2C timing specifications. 201 * @rate: I2C bus speed (Hz) 202 * @fall_max: Max fall time of both SDA and SCL signals (ns) 203 * @rise_max: Max rise time of both SDA and SCL signals (ns) 204 * @hddat_min: Min data hold time (ns) 205 * @vddat_max: Max data valid time (ns) 206 * @sudat_min: Min data setup time (ns) 207 * @l_min: Min low period of the SCL clock (ns) 208 * @h_min: Min high period of the SCL clock (ns) 209 */ 210 struct i2c_spec_s { 211 uint32_t rate; 212 uint32_t fall_max; 213 uint32_t rise_max; 214 uint32_t hddat_min; 215 uint32_t vddat_max; 216 uint32_t sudat_min; 217 uint32_t l_min; 218 uint32_t h_min; 219 }; 220 221 /* 222 * struct i2c_timing_s - Private I2C output parameters. 223 * @scldel: Data setup time 224 * @sdadel: Data hold time 225 * @sclh: SCL high period (master mode) 226 * @sclh: SCL low period (master mode) 227 * @is_saved: True if relating to a configuration candidate 228 */ 229 struct i2c_timing_s { 230 uint8_t scldel; 231 uint8_t sdadel; 232 uint8_t sclh; 233 uint8_t scll; 234 bool is_saved; 235 }; 236 237 /* This table must be sorted in increasing value for field @rate */ 238 static const struct i2c_spec_s i2c_specs[] = { 239 /* Standard - 100KHz */ 240 { 241 .rate = I2C_STANDARD_RATE, 242 .fall_max = 300, 243 .rise_max = 1000, 244 .hddat_min = 0, 245 .vddat_max = 3450, 246 .sudat_min = 250, 247 .l_min = 4700, 248 .h_min = 4000, 249 }, 250 /* Fast - 400KHz */ 251 { 252 .rate = I2C_FAST_RATE, 253 .fall_max = 300, 254 .rise_max = 300, 255 .hddat_min = 0, 256 .vddat_max = 900, 257 .sudat_min = 100, 258 .l_min = 1300, 259 .h_min = 600, 260 }, 261 /* FastPlus - 1MHz */ 262 { 263 .rate = I2C_FAST_PLUS_RATE, 264 .fall_max = 100, 265 .rise_max = 120, 266 .hddat_min = 0, 267 .vddat_max = 450, 268 .sudat_min = 50, 269 .l_min = 500, 270 .h_min = 260, 271 }, 272 }; 273 274 /* 275 * I2C request parameters 276 * @dev_addr: I2C address of the target device 277 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 278 * @mem_addr: Target memory cell accessed in device (memory mode) 279 * @mem_addr_size: Byte size of the memory cell address (memory mode) 280 * @timeout_ms: Timeout in millisenconds for the request 281 */ 282 struct i2c_request { 283 uint32_t dev_addr; 284 enum i2c_mode_e mode; 285 uint32_t mem_addr; 286 uint32_t mem_addr_size; 287 unsigned int timeout_ms; 288 }; 289 290 static vaddr_t get_base(struct i2c_handle_s *hi2c) 291 { 292 return io_pa_or_va_secure(&hi2c->base); 293 } 294 295 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 296 { 297 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 298 hi2c->i2c_state = I2C_STATE_READY; 299 } 300 301 static const struct i2c_spec_s *get_specs(uint32_t rate) 302 { 303 size_t i = 0; 304 305 for (i = 0; i < ARRAY_SIZE(i2c_specs); i++) 306 if (rate <= i2c_specs[i].rate) 307 return i2c_specs + i; 308 309 return NULL; 310 } 311 312 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 313 { 314 vaddr_t base = get_base(hi2c); 315 316 stm32_clock_enable(hi2c->clock); 317 318 cfg->cr1 = io_read32(base + I2C_CR1); 319 cfg->cr2 = io_read32(base + I2C_CR2); 320 cfg->oar1 = io_read32(base + I2C_OAR1); 321 cfg->oar2 = io_read32(base + I2C_OAR2); 322 cfg->timingr = io_read32(base + I2C_TIMINGR); 323 324 stm32_clock_disable(hi2c->clock); 325 } 326 327 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 328 { 329 vaddr_t base = get_base(hi2c); 330 331 stm32_clock_enable(hi2c->clock); 332 333 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 334 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 335 io_write32(base + I2C_OAR1, cfg->oar1); 336 io_write32(base + I2C_CR2, cfg->cr2); 337 io_write32(base + I2C_OAR2, cfg->oar2); 338 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 339 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 340 341 stm32_clock_disable(hi2c->clock); 342 } 343 344 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 345 { 346 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 347 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 348 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 349 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 350 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 351 } 352 353 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 354 { 355 vaddr_t __maybe_unused base = get_base(hi2c); 356 357 stm32_clock_enable(hi2c->clock); 358 359 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 360 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 361 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 362 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 363 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 364 365 stm32_clock_disable(hi2c->clock); 366 } 367 368 /* 369 * Compute the I2C device timings 370 * 371 * @init: Ref to the initialization configuration structure 372 * @clock_src: I2C clock source frequency (Hz) 373 * @timing: Pointer to the final computed timing result 374 * Return 0 on success or a negative value 375 */ 376 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 377 unsigned long clock_src, uint32_t *timing) 378 { 379 const struct i2c_spec_s *specs = NULL; 380 uint32_t speed_freq = 0; 381 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 382 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 383 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 384 uint32_t af_delay_min = 0; 385 uint32_t af_delay_max = 0; 386 uint32_t dnf_delay = 0; 387 uint32_t tsync = 0; 388 uint32_t clk_min = 0; 389 uint32_t clk_max = 0; 390 int clk_error_prev = 0; 391 uint16_t p = 0; 392 uint16_t l = 0; 393 uint16_t a = 0; 394 uint16_t h = 0; 395 unsigned int sdadel_min = 0; 396 unsigned int sdadel_max = 0; 397 unsigned int scldel_min = 0; 398 unsigned int delay = 0; 399 int s = -1; 400 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 401 402 specs = get_specs(init->bus_rate); 403 if (!specs) { 404 EMSG("I2C speed out of bound: %"PRId32"Hz", init->bus_rate); 405 return -1; 406 } 407 408 speed_freq = specs->rate; 409 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 410 clk_error_prev = INT_MAX; 411 412 if (init->rise_time > specs->rise_max || 413 init->fall_time > specs->fall_max) { 414 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 415 init->rise_time, specs->rise_max, 416 init->fall_time, specs->fall_max); 417 return -1; 418 } 419 420 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 421 EMSG("DNF out of bound %d/%d", 422 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 423 return -1; 424 } 425 426 /* Analog and Digital Filters */ 427 if (init->analog_filter) { 428 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 429 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 430 } 431 dnf_delay = init->digital_filter_coef * i2cclk; 432 433 sdadel_min = specs->hddat_min + init->fall_time; 434 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 435 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 436 sdadel_min = 0; 437 438 sdadel_max = specs->vddat_max - init->rise_time; 439 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 440 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 441 sdadel_max = 0; 442 443 scldel_min = init->rise_time + specs->sudat_min; 444 445 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 446 sdadel_min, sdadel_max, scldel_min); 447 448 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 449 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 450 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 451 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 452 453 if (scldel < scldel_min) 454 continue; 455 456 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 457 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 458 459 if ((sdadel >= sdadel_min) && 460 (sdadel <= sdadel_max) && 461 (p != p_prev)) { 462 solutions[p].scldel = l; 463 solutions[p].sdadel = a; 464 solutions[p].is_saved = true; 465 p_prev = p; 466 break; 467 } 468 } 469 470 if (p_prev == p) 471 break; 472 } 473 } 474 475 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 476 EMSG(" I2C no Prescaler solution"); 477 return -1; 478 } 479 480 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 481 clk_max = I2C_NSEC_PER_SEC / RATE_MIN(specs->rate); 482 clk_min = I2C_NSEC_PER_SEC / specs->rate; 483 484 /* 485 * Among prescaler possibilities discovered above figures out SCL Low 486 * and High Period. Provided: 487 * - SCL Low Period has to be higher than Low Period of the SCL Clock 488 * defined by I2C Specification. I2C Clock has to be lower than 489 * (SCL Low Period - Analog/Digital filters) / 4. 490 * - SCL High Period has to be lower than High Period of the SCL Clock 491 * defined by I2C Specification. 492 * - I2C Clock has to be lower than SCL High Period. 493 */ 494 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 495 uint32_t prescaler = (p + 1) * i2cclk; 496 497 if (!solutions[p].is_saved) 498 continue; 499 500 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 501 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 502 503 if (tscl_l < specs->l_min || 504 i2cclk >= ((tscl_l - af_delay_min - dnf_delay) / 4)) 505 continue; 506 507 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 508 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 509 uint32_t tscl = tscl_l + tscl_h + 510 init->rise_time + 511 init->fall_time; 512 513 if (tscl >= clk_min && tscl <= clk_max && 514 tscl_h >= specs->h_min && i2cclk < tscl_h) { 515 int clk_error = tscl - i2cbus; 516 517 if (clk_error < 0) 518 clk_error = -clk_error; 519 520 if (clk_error < clk_error_prev) { 521 clk_error_prev = clk_error; 522 solutions[p].scll = l; 523 solutions[p].sclh = h; 524 s = p; 525 } 526 } 527 } 528 } 529 } 530 531 if (s < 0) { 532 EMSG(" I2C no solution at all"); 533 return -1; 534 } 535 536 /* Finalize timing settings */ 537 *timing = I2C_SET_TIMINGR_PRESC(s) | 538 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 539 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 540 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 541 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 542 543 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 544 s, solutions[s].scldel, solutions[s].sdadel); 545 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 546 solutions[s].sclh, solutions[s].scll); 547 DMSG("I2C TIMINGR: 0x%x", *timing); 548 549 return 0; 550 } 551 552 /* i2c_specs[] must be sorted by increasing rate */ 553 static bool __maybe_unused i2c_specs_is_consistent(void) 554 { 555 size_t i = 0; 556 557 COMPILE_TIME_ASSERT(ARRAY_SIZE(i2c_specs)); 558 559 for (i = 1; i < ARRAY_SIZE(i2c_specs); i++) 560 if (i2c_specs[i - 1].rate >= i2c_specs[i].rate) 561 return false; 562 563 return true; 564 } 565 566 /* 567 * @brief From requested rate, get the closest I2C rate without exceeding it, 568 * within I2C specification values defined in @i2c_specs. 569 * @param rate: The requested rate. 570 * @retval Found rate, else the lowest value supported by platform. 571 */ 572 static uint32_t get_lower_rate(uint32_t rate) 573 { 574 size_t i = 0; 575 576 for (i = ARRAY_SIZE(i2c_specs); i > 0; i--) 577 if (rate > i2c_specs[i - 1].rate) 578 return i2c_specs[i - 1].rate; 579 580 return i2c_specs[0].rate; 581 } 582 583 /* 584 * Setup the I2C device timings 585 * 586 * @hi2c: I2C handle structure 587 * @init: Ref to the initialization configuration structure 588 * @timing: Output TIMINGR register configuration value 589 * @retval 0 if OK, negative value else 590 */ 591 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 592 struct stm32_i2c_init_s *init, 593 uint32_t *timing) 594 { 595 int rc = 0; 596 unsigned long clock_src = 0; 597 598 assert(i2c_specs_is_consistent()); 599 600 clock_src = stm32_clock_get_rate(hi2c->clock); 601 if (!clock_src) { 602 EMSG("Null I2C clock rate"); 603 return -1; 604 } 605 606 /* 607 * If the timing has already been computed, and the frequency is the 608 * same as when it was computed, then use the saved timing. 609 */ 610 if (clock_src == hi2c->saved_frequency) { 611 *timing = hi2c->saved_timing; 612 return 0; 613 } 614 615 do { 616 rc = i2c_compute_timing(init, clock_src, timing); 617 if (rc) { 618 EMSG("Failed to compute I2C timings"); 619 if (init->bus_rate > I2C_STANDARD_RATE) { 620 init->bus_rate = get_lower_rate(init->bus_rate); 621 IMSG("Downgrade I2C speed to %"PRIu32"Hz)", 622 init->bus_rate); 623 } else { 624 break; 625 } 626 } 627 } while (rc); 628 629 if (rc) { 630 EMSG("Impossible to compute I2C timings"); 631 return rc; 632 } 633 634 DMSG("I2C Freq(%"PRIu32"Hz), Clk Source(%lu)", 635 init->bus_rate, clock_src); 636 DMSG("I2C Rise(%i) and Fall(%i) Time", 637 init->rise_time, init->fall_time); 638 DMSG("I2C Analog Filter(%s), DNF(%i)", 639 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 640 641 hi2c->saved_timing = *timing; 642 hi2c->saved_frequency = clock_src; 643 644 return 0; 645 } 646 647 /* 648 * Configure I2C Analog noise filter. 649 * @hi2c: I2C handle structure 650 * @analog_filter_on: True if enabling analog filter, false otherwise 651 * Return 0 on success or a negative value 652 */ 653 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 654 bool analog_filter_on) 655 { 656 vaddr_t base = get_base(hi2c); 657 658 if (hi2c->i2c_state != I2C_STATE_READY) 659 return -1; 660 661 hi2c->i2c_state = I2C_STATE_BUSY; 662 663 /* Disable the selected I2C peripheral */ 664 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 665 666 /* Reset I2Cx ANOFF bit */ 667 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 668 669 /* Set analog filter bit if filter is disabled */ 670 if (!analog_filter_on) 671 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 672 673 /* Enable the selected I2C peripheral */ 674 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 675 676 hi2c->i2c_state = I2C_STATE_READY; 677 678 return 0; 679 } 680 681 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 682 struct stm32_i2c_init_s *init, 683 struct stm32_pinctrl **pinctrl, 684 size_t *pinctrl_count) 685 { 686 const fdt32_t *cuint = NULL; 687 struct dt_node_info info = { .status = 0 }; 688 int count = 0; 689 690 /* Default STM32 specific configs caller may need to overwrite */ 691 memset(init, 0, sizeof(*init)); 692 693 _fdt_fill_device_info(fdt, &info, node); 694 init->dt_status = info.status; 695 init->pbase = info.reg; 696 init->clock = info.clock; 697 assert(info.reg != DT_INFO_INVALID_REG && 698 info.clock != DT_INFO_INVALID_CLOCK); 699 700 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 701 if (cuint) 702 init->rise_time = fdt32_to_cpu(*cuint); 703 else 704 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 705 706 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 707 if (cuint) 708 init->fall_time = fdt32_to_cpu(*cuint); 709 else 710 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 711 712 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 713 if (cuint) { 714 init->bus_rate = fdt32_to_cpu(*cuint); 715 716 if (init->bus_rate > I2C_FAST_PLUS_RATE) { 717 DMSG("Invalid bus speed (%"PRIu32" > %i)", 718 init->bus_rate, I2C_FAST_PLUS_RATE); 719 return -FDT_ERR_BADVALUE; 720 } 721 } else { 722 init->bus_rate = I2C_STANDARD_RATE; 723 } 724 725 count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, NULL, 0); 726 if (count <= 0) { 727 *pinctrl = NULL; 728 *pinctrl_count = 0; 729 return count; 730 } 731 732 if (count > 2) 733 panic("Too many PINCTRLs found"); 734 735 *pinctrl = calloc(count, sizeof(**pinctrl)); 736 if (!*pinctrl) 737 panic(); 738 739 *pinctrl_count = stm32_pinctrl_fdt_get_pinctrl(fdt, node, 740 *pinctrl, count); 741 assert(*pinctrl_count == (unsigned int)count); 742 743 return 0; 744 } 745 746 int stm32_i2c_init(struct i2c_handle_s *hi2c, 747 struct stm32_i2c_init_s *init_data) 748 { 749 int rc = 0; 750 uint32_t timing = 0; 751 vaddr_t base = 0; 752 uint32_t val = 0; 753 754 hi2c->dt_status = init_data->dt_status; 755 hi2c->base.pa = init_data->pbase; 756 hi2c->clock = init_data->clock; 757 758 rc = i2c_setup_timing(hi2c, init_data, &timing); 759 if (rc) 760 return rc; 761 762 stm32_clock_enable(hi2c->clock); 763 base = get_base(hi2c); 764 hi2c->i2c_state = I2C_STATE_BUSY; 765 766 /* Disable the selected I2C peripheral */ 767 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 768 769 /* Configure I2Cx: Frequency range */ 770 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 771 772 /* Disable Own Address1 before set the Own Address1 configuration */ 773 io_write32(base + I2C_OAR1, 0); 774 775 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 776 if (init_data->addr_mode_10b_not_7b) 777 io_write32(base + I2C_OAR1, 778 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 779 init_data->own_address1); 780 else 781 io_write32(base + I2C_OAR1, 782 I2C_OAR1_OA1EN | init_data->own_address1); 783 784 /* Configure I2Cx: Addressing Master mode */ 785 io_write32(base + I2C_CR2, 0); 786 if (init_data->addr_mode_10b_not_7b) 787 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 788 789 /* 790 * Enable the AUTOEND by default, and enable NACK 791 * (should be disabled only during Slave process). 792 */ 793 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 794 795 /* Disable Own Address2 before set the Own Address2 configuration */ 796 io_write32(base + I2C_OAR2, 0); 797 798 /* Configure I2Cx: Dual mode and Own Address2 */ 799 if (init_data->dual_address_mode) 800 io_write32(base + I2C_OAR2, 801 I2C_OAR2_OA2EN | init_data->own_address2 | 802 (init_data->own_address2_masks << 8)); 803 804 /* Configure I2Cx: Generalcall and NoStretch mode */ 805 val = 0; 806 if (init_data->general_call_mode) 807 val |= I2C_CR1_GCEN; 808 if (init_data->no_stretch_mode) 809 val |= I2C_CR1_NOSTRETCH; 810 io_write32(base + I2C_CR1, val); 811 812 /* Enable the selected I2C peripheral */ 813 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 814 815 hi2c->i2c_err = I2C_ERROR_NONE; 816 hi2c->i2c_state = I2C_STATE_READY; 817 818 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 819 if (rc) 820 EMSG("I2C analog filter error %d", rc); 821 822 stm32_clock_disable(hi2c->clock); 823 824 return rc; 825 } 826 827 /* I2C transmit (TX) data register flush sequence */ 828 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 829 { 830 vaddr_t base = get_base(hi2c); 831 832 /* 833 * If a pending TXIS flag is set, 834 * write a dummy data in TXDR to clear it. 835 */ 836 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 837 io_write32(base + I2C_TXDR, 0); 838 839 /* Flush TX register if not empty */ 840 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 841 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 842 } 843 844 /* 845 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 846 * 847 * @hi2c: I2C handle structure 848 * @bit_mask: Bit mask for the target single bit position to consider 849 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 850 * @timeout_ref: Expriation timeout reference 851 * Return 0 on success and a non-zero value on timeout 852 */ 853 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 854 unsigned int awaited_value, uint64_t timeout_ref) 855 { 856 vaddr_t isr = get_base(hi2c) + I2C_ISR; 857 858 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 859 860 /* May timeout while TEE thread is suspended */ 861 while (!timeout_elapsed(timeout_ref)) 862 if (!!(io_read32(isr) & bit_mask) == awaited_value) 863 break; 864 865 if (!!(io_read32(isr) & bit_mask) == awaited_value) 866 return 0; 867 868 notif_i2c_timeout(hi2c); 869 return -1; 870 } 871 872 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 873 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 874 { 875 vaddr_t base = get_base(hi2c); 876 877 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 878 return 0; 879 880 /* 881 * Wait until STOP Flag is reset. Use polling method. 882 * AutoEnd should be initiate after AF. 883 * Timeout may elpased while TEE thread is suspended. 884 */ 885 while (!timeout_elapsed(timeout_ref)) 886 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 887 break; 888 889 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 890 notif_i2c_timeout(hi2c); 891 return -1; 892 } 893 894 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 895 896 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 897 898 i2c_flush_txdr(hi2c); 899 900 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 901 902 hi2c->i2c_err |= I2C_ERROR_ACKF; 903 hi2c->i2c_state = I2C_STATE_READY; 904 905 return -1; 906 } 907 908 /* Wait TXIS bit is 1 in I2C_ISR register */ 909 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 910 { 911 while (!timeout_elapsed(timeout_ref)) { 912 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 913 break; 914 if (i2c_ack_failed(hi2c, timeout_ref)) 915 return -1; 916 } 917 918 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 919 return 0; 920 921 if (i2c_ack_failed(hi2c, timeout_ref)) 922 return -1; 923 924 notif_i2c_timeout(hi2c); 925 return -1; 926 } 927 928 /* Wait STOPF bit is 1 in I2C_ISR register */ 929 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 930 { 931 while (!timeout_elapsed(timeout_ref)) { 932 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 933 break; 934 935 if (i2c_ack_failed(hi2c, timeout_ref)) 936 return -1; 937 } 938 939 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 940 return 0; 941 942 if (i2c_ack_failed(hi2c, timeout_ref)) 943 return -1; 944 945 notif_i2c_timeout(hi2c); 946 return -1; 947 } 948 949 /* 950 * Load I2C_CR2 register for a I2C transfer 951 * 952 * @hi2c: I2C handle structure 953 * @dev_addr: Slave address to be transferred 954 * @size: Number of bytes to be transferred 955 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 956 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 957 * I2C_GENERATE_START_{READ|WRITE} 958 */ 959 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 960 uint32_t size, uint32_t i2c_mode, 961 uint32_t startstop) 962 { 963 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 964 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 965 (I2C_CR2_RD_WRN & 966 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 967 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 968 ((size << I2C_CR2_NBYTES_OFFSET) & 969 I2C_CR2_NBYTES) | 970 i2c_mode | startstop; 971 972 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 973 } 974 975 /* 976 * Master sends target device address followed by internal memory 977 * address for a memory write request. 978 * Function returns 0 on success or a negative value. 979 */ 980 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 981 struct i2c_request *request, 982 uint64_t timeout_ref) 983 { 984 vaddr_t base = get_base(hi2c); 985 986 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 987 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 988 989 if (i2c_wait_txis(hi2c, timeout_ref)) 990 return -1; 991 992 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 993 /* Send memory address */ 994 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 995 } else { 996 /* Send MSB of memory address */ 997 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 998 999 if (i2c_wait_txis(hi2c, timeout_ref)) 1000 return -1; 1001 1002 /* Send LSB of memory address */ 1003 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1004 } 1005 1006 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1007 return -1; 1008 1009 return 0; 1010 } 1011 1012 /* 1013 * Master sends target device address followed by internal memory 1014 * address to prepare a memory read request. 1015 * Function returns 0 on success or a negative value. 1016 */ 1017 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 1018 struct i2c_request *request, 1019 uint64_t timeout_ref) 1020 { 1021 vaddr_t base = get_base(hi2c); 1022 1023 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 1024 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 1025 1026 if (i2c_wait_txis(hi2c, timeout_ref)) 1027 return -1; 1028 1029 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 1030 /* Send memory address */ 1031 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1032 } else { 1033 /* Send MSB of memory address */ 1034 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 1035 1036 if (i2c_wait_txis(hi2c, timeout_ref)) 1037 return -1; 1038 1039 /* Send LSB of memory address */ 1040 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 1041 } 1042 1043 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 1044 return -1; 1045 1046 return 0; 1047 } 1048 1049 /* 1050 * Write an amount of data in blocking mode 1051 * 1052 * @hi2c: Reference to struct i2c_handle_s 1053 * @request: I2C request parameters 1054 * @p_data: Pointer to data buffer 1055 * @size: Amount of data to be sent 1056 * Return 0 on success or a negative value 1057 */ 1058 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1059 uint8_t *p_data, uint16_t size) 1060 { 1061 uint64_t timeout_ref = 0; 1062 vaddr_t base = get_base(hi2c); 1063 int rc = -1; 1064 uint8_t *p_buff = p_data; 1065 size_t xfer_size = 0; 1066 size_t xfer_count = size; 1067 1068 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1069 return -1; 1070 1071 if (hi2c->i2c_state != I2C_STATE_READY) 1072 return -1; 1073 1074 if (!p_data || !size) 1075 return -1; 1076 1077 stm32_clock_enable(hi2c->clock); 1078 1079 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1080 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1081 goto bail; 1082 1083 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1084 hi2c->i2c_err = I2C_ERROR_NONE; 1085 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1086 1087 if (request->mode == I2C_MODE_MEM) { 1088 /* In memory mode, send slave address and memory address */ 1089 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1090 goto bail; 1091 1092 if (xfer_count > MAX_NBYTE_SIZE) { 1093 xfer_size = MAX_NBYTE_SIZE; 1094 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1095 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1096 } else { 1097 xfer_size = xfer_count; 1098 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1099 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1100 } 1101 } else { 1102 /* In master mode, send slave address */ 1103 if (xfer_count > MAX_NBYTE_SIZE) { 1104 xfer_size = MAX_NBYTE_SIZE; 1105 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1106 I2C_RELOAD_MODE, 1107 I2C_GENERATE_START_WRITE); 1108 } else { 1109 xfer_size = xfer_count; 1110 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1111 I2C_AUTOEND_MODE, 1112 I2C_GENERATE_START_WRITE); 1113 } 1114 } 1115 1116 do { 1117 if (i2c_wait_txis(hi2c, timeout_ref)) 1118 goto bail; 1119 1120 io_write8(base + I2C_TXDR, *p_buff); 1121 p_buff++; 1122 xfer_count--; 1123 xfer_size--; 1124 1125 if (xfer_count && !xfer_size) { 1126 /* Wait until TCR flag is set */ 1127 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1128 goto bail; 1129 1130 if (xfer_count > MAX_NBYTE_SIZE) { 1131 xfer_size = MAX_NBYTE_SIZE; 1132 i2c_transfer_config(hi2c, request->dev_addr, 1133 xfer_size, 1134 I2C_RELOAD_MODE, 1135 I2C_NO_STARTSTOP); 1136 } else { 1137 xfer_size = xfer_count; 1138 i2c_transfer_config(hi2c, request->dev_addr, 1139 xfer_size, 1140 I2C_AUTOEND_MODE, 1141 I2C_NO_STARTSTOP); 1142 } 1143 } 1144 1145 } while (xfer_count > 0U); 1146 1147 /* 1148 * No need to Check TC flag, with AUTOEND mode the stop 1149 * is automatically generated. 1150 * Wait until STOPF flag is reset. 1151 */ 1152 if (i2c_wait_stop(hi2c, timeout_ref)) 1153 goto bail; 1154 1155 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1156 1157 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1158 1159 hi2c->i2c_state = I2C_STATE_READY; 1160 1161 rc = 0; 1162 1163 bail: 1164 stm32_clock_disable(hi2c->clock); 1165 1166 return rc; 1167 } 1168 1169 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1170 uint32_t mem_addr, uint32_t mem_addr_size, 1171 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1172 { 1173 struct i2c_request request = { 1174 .dev_addr = dev_addr, 1175 .mode = I2C_MODE_MEM, 1176 .mem_addr = mem_addr, 1177 .mem_addr_size = mem_addr_size, 1178 .timeout_ms = timeout_ms, 1179 }; 1180 1181 return i2c_write(hi2c, &request, p_data, size); 1182 } 1183 1184 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1185 uint8_t *p_data, size_t size, 1186 unsigned int timeout_ms) 1187 { 1188 struct i2c_request request = { 1189 .dev_addr = dev_addr, 1190 .mode = I2C_MODE_MASTER, 1191 .timeout_ms = timeout_ms, 1192 }; 1193 1194 return i2c_write(hi2c, &request, p_data, size); 1195 } 1196 1197 int stm32_i2c_read_write_membyte(struct i2c_handle_s *hi2c, uint16_t dev_addr, 1198 unsigned int mem_addr, uint8_t *p_data, 1199 bool write) 1200 { 1201 uint64_t timeout_ref = 0; 1202 uintptr_t base = get_base(hi2c); 1203 int rc = -1; 1204 uint8_t *p_buff = p_data; 1205 uint32_t event_mask = 0; 1206 1207 if (hi2c->i2c_state != I2C_STATE_READY || !p_data) 1208 return -1; 1209 1210 stm32_clock_enable(hi2c->clock); 1211 1212 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1213 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1214 goto bail; 1215 1216 hi2c->i2c_state = write ? I2C_STATE_BUSY_TX : I2C_STATE_BUSY_RX; 1217 hi2c->i2c_err = I2C_ERROR_NONE; 1218 1219 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1220 write ? I2C_RELOAD_MODE : I2C_SOFTEND_MODE, 1221 I2C_GENERATE_START_WRITE); 1222 1223 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1224 if (i2c_wait_txis(hi2c, timeout_ref)) 1225 goto bail; 1226 1227 io_write8(base + I2C_TXDR, mem_addr); 1228 1229 if (write) 1230 event_mask = I2C_ISR_TCR; 1231 else 1232 event_mask = I2C_ISR_TC; 1233 1234 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1235 if (wait_isr_event(hi2c, event_mask, 1, timeout_ref)) 1236 goto bail; 1237 1238 i2c_transfer_config(hi2c, dev_addr, I2C_MEMADD_SIZE_8BIT, 1239 I2C_AUTOEND_MODE, 1240 write ? I2C_NO_STARTSTOP : I2C_GENERATE_START_READ); 1241 1242 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1243 if (write) { 1244 if (i2c_wait_txis(hi2c, timeout_ref)) 1245 goto bail; 1246 1247 io_write8(base + I2C_TXDR, *p_buff); 1248 } else { 1249 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1250 goto bail; 1251 1252 *p_buff = io_read8(base + I2C_RXDR); 1253 } 1254 1255 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_US); 1256 if (i2c_wait_stop(hi2c, timeout_ref)) 1257 goto bail; 1258 1259 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1260 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1261 1262 hi2c->i2c_state = I2C_STATE_READY; 1263 1264 rc = 0; 1265 1266 bail: 1267 stm32_clock_disable(hi2c->clock); 1268 1269 return rc; 1270 } 1271 1272 /* 1273 * Read an amount of data in blocking mode 1274 * 1275 * @hi2c: Reference to struct i2c_handle_s 1276 * @request: I2C request parameters 1277 * @p_data: Pointer to data buffer 1278 * @size: Amount of data to be sent 1279 * Return 0 on success or a negative value 1280 */ 1281 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1282 uint8_t *p_data, uint32_t size) 1283 { 1284 vaddr_t base = get_base(hi2c); 1285 uint64_t timeout_ref = 0; 1286 int rc = -1; 1287 uint8_t *p_buff = p_data; 1288 size_t xfer_count = size; 1289 size_t xfer_size = 0; 1290 1291 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1292 return -1; 1293 1294 if (hi2c->i2c_state != I2C_STATE_READY) 1295 return -1; 1296 1297 if (!p_data || !size) 1298 return -1; 1299 1300 stm32_clock_enable(hi2c->clock); 1301 1302 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1303 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1304 goto bail; 1305 1306 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1307 hi2c->i2c_err = I2C_ERROR_NONE; 1308 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1309 1310 if (request->mode == I2C_MODE_MEM) { 1311 /* Send memory address */ 1312 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1313 goto bail; 1314 } 1315 1316 /* 1317 * Send slave address. 1318 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1319 * and generate RESTART. 1320 */ 1321 if (xfer_count > MAX_NBYTE_SIZE) { 1322 xfer_size = MAX_NBYTE_SIZE; 1323 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1324 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1325 } else { 1326 xfer_size = xfer_count; 1327 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1328 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1329 } 1330 1331 do { 1332 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1333 goto bail; 1334 1335 *p_buff = io_read8(base + I2C_RXDR); 1336 p_buff++; 1337 xfer_size--; 1338 xfer_count--; 1339 1340 if (xfer_count && !xfer_size) { 1341 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1342 goto bail; 1343 1344 if (xfer_count > MAX_NBYTE_SIZE) { 1345 xfer_size = MAX_NBYTE_SIZE; 1346 i2c_transfer_config(hi2c, request->dev_addr, 1347 xfer_size, 1348 I2C_RELOAD_MODE, 1349 I2C_NO_STARTSTOP); 1350 } else { 1351 xfer_size = xfer_count; 1352 i2c_transfer_config(hi2c, request->dev_addr, 1353 xfer_size, 1354 I2C_AUTOEND_MODE, 1355 I2C_NO_STARTSTOP); 1356 } 1357 } 1358 } while (xfer_count > 0U); 1359 1360 /* 1361 * No need to Check TC flag, with AUTOEND mode the stop 1362 * is automatically generated. 1363 * Wait until STOPF flag is reset. 1364 */ 1365 if (i2c_wait_stop(hi2c, timeout_ref)) 1366 goto bail; 1367 1368 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1369 1370 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1371 1372 hi2c->i2c_state = I2C_STATE_READY; 1373 1374 rc = 0; 1375 1376 bail: 1377 stm32_clock_disable(hi2c->clock); 1378 1379 return rc; 1380 } 1381 1382 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1383 uint32_t mem_addr, uint32_t mem_addr_size, 1384 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1385 { 1386 struct i2c_request request = { 1387 .dev_addr = dev_addr, 1388 .mode = I2C_MODE_MEM, 1389 .mem_addr = mem_addr, 1390 .mem_addr_size = mem_addr_size, 1391 .timeout_ms = timeout_ms, 1392 }; 1393 1394 return i2c_read(hi2c, &request, p_data, size); 1395 } 1396 1397 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1398 uint8_t *p_data, size_t size, 1399 unsigned int timeout_ms) 1400 { 1401 struct i2c_request request = { 1402 .dev_addr = dev_addr, 1403 .mode = I2C_MODE_MASTER, 1404 .timeout_ms = timeout_ms, 1405 }; 1406 1407 return i2c_read(hi2c, &request, p_data, size); 1408 } 1409 1410 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1411 unsigned int trials, unsigned int timeout_ms) 1412 { 1413 vaddr_t base = get_base(hi2c); 1414 unsigned int i2c_trials = 0U; 1415 bool rc = false; 1416 1417 if (hi2c->i2c_state != I2C_STATE_READY) 1418 return rc; 1419 1420 stm32_clock_enable(hi2c->clock); 1421 1422 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1423 goto bail; 1424 1425 hi2c->i2c_state = I2C_STATE_BUSY; 1426 hi2c->i2c_err = I2C_ERROR_NONE; 1427 1428 do { 1429 uint64_t timeout_ref = 0; 1430 vaddr_t isr = base + I2C_ISR; 1431 1432 /* Generate Start */ 1433 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1434 io_write32(base + I2C_CR2, 1435 ((dev_addr & I2C_CR2_SADD) | 1436 I2C_CR2_START | I2C_CR2_AUTOEND) & 1437 ~I2C_CR2_RD_WRN); 1438 else 1439 io_write32(base + I2C_CR2, 1440 ((dev_addr & I2C_CR2_SADD) | 1441 I2C_CR2_START | I2C_CR2_ADD10) & 1442 ~I2C_CR2_RD_WRN); 1443 1444 /* 1445 * No need to Check TC flag, with AUTOEND mode the stop 1446 * is automatically generated. 1447 * Wait until STOPF flag is set or a NACK flag is set. 1448 */ 1449 timeout_ref = timeout_init_us(timeout_ms * 1000); 1450 while (!timeout_elapsed(timeout_ref)) 1451 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1452 break; 1453 1454 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1455 notif_i2c_timeout(hi2c); 1456 goto bail; 1457 } 1458 1459 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1460 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1461 goto bail; 1462 1463 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1464 1465 hi2c->i2c_state = I2C_STATE_READY; 1466 1467 rc = true; 1468 goto bail; 1469 } 1470 1471 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1472 goto bail; 1473 1474 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1475 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1476 1477 if (i2c_trials == trials) { 1478 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1479 1480 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1481 goto bail; 1482 1483 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1484 } 1485 1486 i2c_trials++; 1487 } while (i2c_trials < trials); 1488 1489 notif_i2c_timeout(hi2c); 1490 1491 bail: 1492 stm32_clock_disable(hi2c->clock); 1493 1494 return rc; 1495 } 1496 1497 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1498 { 1499 if (hi2c->i2c_state == I2C_STATE_READY) 1500 return; 1501 1502 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1503 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1504 panic(); 1505 1506 stm32_pinctrl_load_active_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1507 1508 if (hi2c->i2c_state == I2C_STATE_RESET) { 1509 /* There is no valid I2C configuration to be loaded yet */ 1510 return; 1511 } 1512 1513 restore_cfg(hi2c, &hi2c->sec_cfg); 1514 1515 hi2c->i2c_state = I2C_STATE_READY; 1516 } 1517 1518 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1519 { 1520 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1521 return; 1522 1523 if (hi2c->i2c_state != I2C_STATE_READY) 1524 panic(); 1525 1526 save_cfg(hi2c, &hi2c->sec_cfg); 1527 stm32_pinctrl_load_standby_cfg(hi2c->pinctrl, hi2c->pinctrl_count); 1528 1529 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1530 } 1531