1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) 2 /* 3 * Copyright (c) 2017-2019, STMicroelectronics 4 * 5 * The driver API is defined in header file stm32_i2c.h. 6 * 7 * I2C bus driver does not register to the PM framework. It is the 8 * responsibility of the bus owner to call the related STM32 I2C driver 9 * API functions when bus suspends or resumes. 10 */ 11 12 #include <arm.h> 13 #include <drivers/stm32_i2c.h> 14 #include <io.h> 15 #include <kernel/delay.h> 16 #include <kernel/dt.h> 17 #include <kernel/generic_boot.h> 18 #include <kernel/panic.h> 19 #include <libfdt.h> 20 #include <stdbool.h> 21 #include <stdlib.h> 22 #include <stm32_util.h> 23 #include <trace.h> 24 25 /* STM32 I2C registers offsets */ 26 #define I2C_CR1 0x00U 27 #define I2C_CR2 0x04U 28 #define I2C_OAR1 0x08U 29 #define I2C_OAR2 0x0CU 30 #define I2C_TIMINGR 0x10U 31 #define I2C_TIMEOUTR 0x14U 32 #define I2C_ISR 0x18U 33 #define I2C_ICR 0x1CU 34 #define I2C_PECR 0x20U 35 #define I2C_RXDR 0x24U 36 #define I2C_TXDR 0x28U 37 38 /* Bit definition for I2C_CR1 register */ 39 #define I2C_CR1_PE BIT(0) 40 #define I2C_CR1_TXIE BIT(1) 41 #define I2C_CR1_RXIE BIT(2) 42 #define I2C_CR1_ADDRIE BIT(3) 43 #define I2C_CR1_NACKIE BIT(4) 44 #define I2C_CR1_STOPIE BIT(5) 45 #define I2C_CR1_TCIE BIT(6) 46 #define I2C_CR1_ERRIE BIT(7) 47 #define I2C_CR1_DNF GENMASK_32(11, 8) 48 #define I2C_CR1_ANFOFF BIT(12) 49 #define I2C_CR1_SWRST BIT(13) 50 #define I2C_CR1_TXDMAEN BIT(14) 51 #define I2C_CR1_RXDMAEN BIT(15) 52 #define I2C_CR1_SBC BIT(16) 53 #define I2C_CR1_NOSTRETCH BIT(17) 54 #define I2C_CR1_WUPEN BIT(18) 55 #define I2C_CR1_GCEN BIT(19) 56 #define I2C_CR1_SMBHEN BIT(22) 57 #define I2C_CR1_SMBDEN BIT(21) 58 #define I2C_CR1_ALERTEN BIT(22) 59 #define I2C_CR1_PECEN BIT(23) 60 61 /* Bit definition for I2C_CR2 register */ 62 #define I2C_CR2_SADD GENMASK_32(9, 0) 63 #define I2C_CR2_RD_WRN BIT(10) 64 #define I2C_CR2_RD_WRN_OFFSET 10U 65 #define I2C_CR2_ADD10 BIT(11) 66 #define I2C_CR2_HEAD10R BIT(12) 67 #define I2C_CR2_START BIT(13) 68 #define I2C_CR2_STOP BIT(14) 69 #define I2C_CR2_NACK BIT(15) 70 #define I2C_CR2_NBYTES GENMASK_32(23, 16) 71 #define I2C_CR2_NBYTES_OFFSET 16U 72 #define I2C_CR2_RELOAD BIT(24) 73 #define I2C_CR2_AUTOEND BIT(25) 74 #define I2C_CR2_PECBYTE BIT(26) 75 76 /* Bit definition for I2C_OAR1 register */ 77 #define I2C_OAR1_OA1 GENMASK_32(9, 0) 78 #define I2C_OAR1_OA1MODE BIT(10) 79 #define I2C_OAR1_OA1EN BIT(15) 80 81 /* Bit definition for I2C_OAR2 register */ 82 #define I2C_OAR2_OA2 GENMASK_32(7, 1) 83 #define I2C_OAR2_OA2MSK GENMASK_32(10, 8) 84 #define I2C_OAR2_OA2NOMASK 0 85 #define I2C_OAR2_OA2MASK01 BIT(8) 86 #define I2C_OAR2_OA2MASK02 BIT(9) 87 #define I2C_OAR2_OA2MASK03 GENMASK_32(9, 8) 88 #define I2C_OAR2_OA2MASK04 BIT(10) 89 #define I2C_OAR2_OA2MASK05 (BIT(8) | BIT(10)) 90 #define I2C_OAR2_OA2MASK06 (BIT(9) | BIT(10)) 91 #define I2C_OAR2_OA2MASK07 GENMASK_32(10, 8) 92 #define I2C_OAR2_OA2EN BIT(15) 93 94 /* Bit definition for I2C_TIMINGR register */ 95 #define I2C_TIMINGR_SCLL GENMASK_32(7, 0) 96 #define I2C_TIMINGR_SCLH GENMASK_32(15, 8) 97 #define I2C_TIMINGR_SDADEL GENMASK_32(19, 16) 98 #define I2C_TIMINGR_SCLDEL GENMASK_32(23, 20) 99 #define I2C_TIMINGR_PRESC GENMASK_32(31, 28) 100 #define I2C_TIMINGR_SCLL_MAX (I2C_TIMINGR_SCLL + 1) 101 #define I2C_TIMINGR_SCLH_MAX ((I2C_TIMINGR_SCLH >> 8) + 1) 102 #define I2C_TIMINGR_SDADEL_MAX ((I2C_TIMINGR_SDADEL >> 16) + 1) 103 #define I2C_TIMINGR_SCLDEL_MAX ((I2C_TIMINGR_SCLDEL >> 20) + 1) 104 #define I2C_TIMINGR_PRESC_MAX ((I2C_TIMINGR_PRESC >> 28) + 1) 105 #define I2C_SET_TIMINGR_SCLL(n) ((n) & \ 106 (I2C_TIMINGR_SCLL_MAX - 1)) 107 #define I2C_SET_TIMINGR_SCLH(n) (((n) & \ 108 (I2C_TIMINGR_SCLH_MAX - 1)) << 8) 109 #define I2C_SET_TIMINGR_SDADEL(n) (((n) & \ 110 (I2C_TIMINGR_SDADEL_MAX - 1)) << 16) 111 #define I2C_SET_TIMINGR_SCLDEL(n) (((n) & \ 112 (I2C_TIMINGR_SCLDEL_MAX - 1)) << 20) 113 #define I2C_SET_TIMINGR_PRESC(n) (((n) & \ 114 (I2C_TIMINGR_PRESC_MAX - 1)) << 28) 115 116 /* Bit definition for I2C_TIMEOUTR register */ 117 #define I2C_TIMEOUTR_TIMEOUTA GENMASK_32(11, 0) 118 #define I2C_TIMEOUTR_TIDLE BIT(12) 119 #define I2C_TIMEOUTR_TIMOUTEN BIT(15) 120 #define I2C_TIMEOUTR_TIMEOUTB GENMASK_32(27, 16) 121 #define I2C_TIMEOUTR_TEXTEN BIT(31) 122 123 /* Bit definition for I2C_ISR register */ 124 #define I2C_ISR_TXE BIT(0) 125 #define I2C_ISR_TXIS BIT(1) 126 #define I2C_ISR_RXNE BIT(2) 127 #define I2C_ISR_ADDR BIT(3) 128 #define I2C_ISR_NACKF BIT(4) 129 #define I2C_ISR_STOPF BIT(5) 130 #define I2C_ISR_TC BIT(6) 131 #define I2C_ISR_TCR BIT(7) 132 #define I2C_ISR_BERR BIT(8) 133 #define I2C_ISR_ARLO BIT(9) 134 #define I2C_ISR_OVR BIT(10) 135 #define I2C_ISR_PECERR BIT(11) 136 #define I2C_ISR_TIMEOUT BIT(12) 137 #define I2C_ISR_ALERT BIT(13) 138 #define I2C_ISR_BUSY BIT(15) 139 #define I2C_ISR_DIR BIT(16) 140 #define I2C_ISR_ADDCODE GENMASK_32(23, 17) 141 142 /* Bit definition for I2C_ICR register */ 143 #define I2C_ICR_ADDRCF BIT(3) 144 #define I2C_ICR_NACKCF BIT(4) 145 #define I2C_ICR_STOPCF BIT(5) 146 #define I2C_ICR_BERRCF BIT(8) 147 #define I2C_ICR_ARLOCF BIT(9) 148 #define I2C_ICR_OVRCF BIT(10) 149 #define I2C_ICR_PECCF BIT(11) 150 #define I2C_ICR_TIMOUTCF BIT(12) 151 #define I2C_ICR_ALERTCF BIT(13) 152 153 /* Max data size for a single I2C transfer */ 154 #define MAX_NBYTE_SIZE 255U 155 156 #define I2C_NSEC_PER_SEC 1000000000L 157 #define I2C_TIMEOUT_BUSY_MS 25U 158 159 #define CR2_RESET_MASK (I2C_CR2_SADD | I2C_CR2_HEAD10R | \ 160 I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ 161 I2C_CR2_RD_WRN) 162 163 #define TIMINGR_CLEAR_MASK (I2C_TIMINGR_SCLL | I2C_TIMINGR_SCLH | \ 164 I2C_TIMINGR_SDADEL | \ 165 I2C_TIMINGR_SCLDEL | I2C_TIMINGR_PRESC) 166 167 /* 168 * I2C transfer modes 169 * I2C_RELOAD: Enable Reload mode 170 * I2C_AUTOEND_MODE: Enable automatic end mode 171 * I2C_SOFTEND_MODE: Enable software end mode 172 */ 173 #define I2C_RELOAD_MODE I2C_CR2_RELOAD 174 #define I2C_AUTOEND_MODE I2C_CR2_AUTOEND 175 #define I2C_SOFTEND_MODE 0x0 176 177 /* 178 * Start/restart/stop I2C transfer requests. 179 * 180 * I2C_NO_STARTSTOP: Don't Generate stop and start condition 181 * I2C_GENERATE_STOP: Generate stop condition (size should be set to 0) 182 * I2C_GENERATE_START_READ: Generate Restart for read request. 183 * I2C_GENERATE_START_WRITE: Generate Restart for write request 184 */ 185 #define I2C_NO_STARTSTOP 0x0 186 #define I2C_GENERATE_STOP (BIT(31) | I2C_CR2_STOP) 187 #define I2C_GENERATE_START_READ (BIT(31) | I2C_CR2_START | \ 188 I2C_CR2_RD_WRN) 189 #define I2C_GENERATE_START_WRITE (BIT(31) | I2C_CR2_START) 190 191 /* Memory address byte sizes */ 192 #define I2C_MEMADD_SIZE_8BIT 1 193 #define I2C_MEMADD_SIZE_16BIT 2 194 195 /* 196 * struct i2c_spec_s - Private I2C timing specifications. 197 * @rate: I2C bus speed (Hz) 198 * @rate_min: 80% of I2C bus speed (Hz) 199 * @rate_max: 120% of I2C bus speed (Hz) 200 * @fall_max: Max fall time of both SDA and SCL signals (ns) 201 * @rise_max: Max rise time of both SDA and SCL signals (ns) 202 * @hddat_min: Min data hold time (ns) 203 * @vddat_max: Max data valid time (ns) 204 * @sudat_min: Min data setup time (ns) 205 * @l_min: Min low period of the SCL clock (ns) 206 * @h_min: Min high period of the SCL clock (ns) 207 */ 208 struct i2c_spec_s { 209 uint32_t rate; 210 uint32_t rate_min; 211 uint32_t rate_max; 212 uint32_t fall_max; 213 uint32_t rise_max; 214 uint32_t hddat_min; 215 uint32_t vddat_max; 216 uint32_t sudat_min; 217 uint32_t l_min; 218 uint32_t h_min; 219 }; 220 221 /* 222 * struct i2c_timing_s - Private I2C output parameters. 223 * @scldel: Data setup time 224 * @sdadel: Data hold time 225 * @sclh: SCL high period (master mode) 226 * @sclh: SCL low period (master mode) 227 * @is_saved: True if relating to a configuration candidate 228 */ 229 struct i2c_timing_s { 230 uint8_t scldel; 231 uint8_t sdadel; 232 uint8_t sclh; 233 uint8_t scll; 234 bool is_saved; 235 }; 236 237 /* 238 * I2C specification values as per version 6.0, 4th of April 2014 [1], 239 * table 10 page 48: Characteristics of the SDA and SCL bus lines for 240 * Standard, Fast, and Fast-mode Plus I2C-bus devices. 241 * 242 * [1] https://www.nxp.com/docs/en/user-guide/UM10204.pdf 243 */ 244 enum i2c_speed_e { 245 I2C_SPEED_STANDARD, /* 100 kHz */ 246 I2C_SPEED_FAST, /* 400 kHz */ 247 I2C_SPEED_FAST_PLUS, /* 1 MHz */ 248 }; 249 250 #define STANDARD_RATE 100000 251 #define FAST_RATE 400000 252 #define FAST_PLUS_RATE 1000000 253 254 static const struct i2c_spec_s i2c_specs[] = { 255 [I2C_SPEED_STANDARD] = { 256 .rate = STANDARD_RATE, 257 .rate_min = (STANDARD_RATE * 80) / 100, 258 .rate_max = (STANDARD_RATE * 120) / 100, 259 .fall_max = 300, 260 .rise_max = 1000, 261 .hddat_min = 0, 262 .vddat_max = 3450, 263 .sudat_min = 250, 264 .l_min = 4700, 265 .h_min = 4000, 266 }, 267 [I2C_SPEED_FAST] = { 268 .rate = FAST_RATE, 269 .rate_min = (FAST_RATE * 80) / 100, 270 .rate_max = (FAST_RATE * 120) / 100, 271 .fall_max = 300, 272 .rise_max = 300, 273 .hddat_min = 0, 274 .vddat_max = 900, 275 .sudat_min = 100, 276 .l_min = 1300, 277 .h_min = 600, 278 }, 279 [I2C_SPEED_FAST_PLUS] = { 280 .rate = FAST_PLUS_RATE, 281 .rate_min = (FAST_PLUS_RATE * 80) / 100, 282 .rate_max = (FAST_PLUS_RATE * 120) / 100, 283 .fall_max = 100, 284 .rise_max = 120, 285 .hddat_min = 0, 286 .vddat_max = 450, 287 .sudat_min = 50, 288 .l_min = 500, 289 .h_min = 260, 290 }, 291 }; 292 293 /* 294 * I2C request parameters 295 * @dev_addr: I2C address of the target device 296 * @mode: Communication mode, one of I2C_MODE_(MASTER|MEM) 297 * @mem_addr: Target memory cell accessed in device (memory mode) 298 * @mem_addr_size: Byte size of the memory cell address (memory mode) 299 * @timeout_ms: Timeout in millisenconds for the request 300 */ 301 struct i2c_request { 302 uint32_t dev_addr; 303 enum i2c_mode_e mode; 304 uint32_t mem_addr; 305 uint32_t mem_addr_size; 306 unsigned int timeout_ms; 307 }; 308 309 static vaddr_t get_base(struct i2c_handle_s *hi2c) 310 { 311 return io_pa_or_va(&hi2c->base); 312 } 313 314 static void notif_i2c_timeout(struct i2c_handle_s *hi2c) 315 { 316 hi2c->i2c_err |= I2C_ERROR_TIMEOUT; 317 hi2c->i2c_state = I2C_STATE_READY; 318 } 319 320 static void save_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 321 { 322 vaddr_t base = get_base(hi2c); 323 324 stm32_clock_enable(hi2c->clock); 325 326 cfg->cr1 = io_read32(base + I2C_CR1); 327 cfg->cr2 = io_read32(base + I2C_CR2); 328 cfg->oar1 = io_read32(base + I2C_OAR1); 329 cfg->oar2 = io_read32(base + I2C_OAR2); 330 cfg->timingr = io_read32(base + I2C_TIMINGR); 331 332 stm32_clock_disable(hi2c->clock); 333 } 334 335 static void restore_cfg(struct i2c_handle_s *hi2c, struct i2c_cfg *cfg) 336 { 337 vaddr_t base = get_base(hi2c); 338 339 stm32_clock_enable(hi2c->clock); 340 341 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 342 io_write32(base + I2C_TIMINGR, cfg->timingr & TIMINGR_CLEAR_MASK); 343 io_write32(base + I2C_OAR1, cfg->oar1); 344 io_write32(base + I2C_CR2, cfg->cr2); 345 io_write32(base + I2C_OAR2, cfg->oar2); 346 io_write32(base + I2C_CR1, cfg->cr1 & ~I2C_CR1_PE); 347 io_setbits32(base + I2C_CR1, cfg->cr1 & I2C_CR1_PE); 348 349 stm32_clock_disable(hi2c->clock); 350 } 351 352 static void __maybe_unused dump_cfg(struct i2c_cfg *cfg __maybe_unused) 353 { 354 DMSG("CR1: 0x%" PRIx32, cfg->cr1); 355 DMSG("CR2: 0x%" PRIx32, cfg->cr2); 356 DMSG("OAR1: 0x%" PRIx32, cfg->oar1); 357 DMSG("OAR2: 0x%" PRIx32, cfg->oar2); 358 DMSG("TIM: 0x%" PRIx32, cfg->timingr); 359 } 360 361 static void __maybe_unused dump_i2c(struct i2c_handle_s *hi2c) 362 { 363 vaddr_t __maybe_unused base = get_base(hi2c); 364 365 stm32_clock_enable(hi2c->clock); 366 367 DMSG("CR1: 0x%" PRIx32, io_read32(base + I2C_CR1)); 368 DMSG("CR2: 0x%" PRIx32, io_read32(base + I2C_CR2)); 369 DMSG("OAR1: 0x%" PRIx32, io_read32(base + I2C_OAR1)); 370 DMSG("OAR2: 0x%" PRIx32, io_read32(base + I2C_OAR2)); 371 DMSG("TIM: 0x%" PRIx32, io_read32(base + I2C_TIMINGR)); 372 373 stm32_clock_disable(hi2c->clock); 374 } 375 376 /* 377 * Compute the I2C device timings 378 * 379 * @init: Ref to the initialization configuration structure 380 * @clock_src: I2C clock source frequency (Hz) 381 * @timing: Pointer to the final computed timing result 382 * Return 0 on success or a negative value 383 */ 384 static int i2c_compute_timing(struct stm32_i2c_init_s *init, 385 uint32_t clock_src, uint32_t *timing) 386 { 387 enum i2c_speed_e mode = init->speed_mode; 388 uint32_t speed_freq = i2c_specs[mode].rate; 389 uint32_t i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 390 uint32_t i2cclk = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, clock_src); 391 uint32_t p_prev = I2C_TIMINGR_PRESC_MAX; 392 uint32_t af_delay_min = 0; 393 uint32_t af_delay_max = 0; 394 uint32_t dnf_delay = 0; 395 uint32_t tsync = 0; 396 uint32_t clk_min = 0; 397 uint32_t clk_max = 0; 398 int clk_error_prev = 0; 399 uint16_t p = 0; 400 uint16_t l = 0; 401 uint16_t a = 0; 402 uint16_t h = 0; 403 unsigned int sdadel_min = 0; 404 unsigned int sdadel_max = 0; 405 unsigned int scldel_min = 0; 406 unsigned int delay = 0; 407 int s = -1; 408 struct i2c_timing_s solutions[I2C_TIMINGR_PRESC_MAX] = { 0 }; 409 410 switch (mode) { 411 case I2C_SPEED_STANDARD: 412 case I2C_SPEED_FAST: 413 case I2C_SPEED_FAST_PLUS: 414 break; 415 default: 416 EMSG("I2C speed out of bound {%d/%d}", 417 mode, I2C_SPEED_FAST_PLUS); 418 return -1; 419 } 420 421 speed_freq = i2c_specs[mode].rate; 422 i2cbus = UDIV_ROUND_NEAREST(I2C_NSEC_PER_SEC, speed_freq); 423 clk_error_prev = INT_MAX; 424 425 if ((init->rise_time > i2c_specs[mode].rise_max) || 426 (init->fall_time > i2c_specs[mode].fall_max)) { 427 EMSG(" I2C timings out of bound: Rise{%d > %d}/Fall{%d > %d}", 428 init->rise_time, i2c_specs[mode].rise_max, 429 init->fall_time, i2c_specs[mode].fall_max); 430 return -1; 431 } 432 433 if (init->digital_filter_coef > STM32_I2C_DIGITAL_FILTER_MAX) { 434 EMSG("DNF out of bound %d/%d", 435 init->digital_filter_coef, STM32_I2C_DIGITAL_FILTER_MAX); 436 return -1; 437 } 438 439 /* Analog and Digital Filters */ 440 if (init->analog_filter) { 441 af_delay_min = STM32_I2C_ANALOG_FILTER_DELAY_MIN; 442 af_delay_max = STM32_I2C_ANALOG_FILTER_DELAY_MAX; 443 } 444 dnf_delay = init->digital_filter_coef * i2cclk; 445 446 sdadel_min = i2c_specs[mode].hddat_min + init->fall_time; 447 delay = af_delay_min - ((init->digital_filter_coef + 3) * i2cclk); 448 if (SUB_OVERFLOW(sdadel_min, delay, &sdadel_min)) 449 sdadel_min = 0; 450 451 sdadel_max = i2c_specs[mode].vddat_max - init->rise_time; 452 delay = af_delay_max - ((init->digital_filter_coef + 4) * i2cclk); 453 if (SUB_OVERFLOW(sdadel_max, delay, &sdadel_max)) 454 sdadel_max = 0; 455 456 scldel_min = init->rise_time + i2c_specs[mode].sudat_min; 457 458 DMSG("I2C SDADEL(min/max): %u/%u, SCLDEL(Min): %u", 459 sdadel_min, sdadel_max, scldel_min); 460 461 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 462 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 463 for (l = 0; l < I2C_TIMINGR_SCLDEL_MAX; l++) { 464 uint32_t scldel = (l + 1) * (p + 1) * i2cclk; 465 466 if (scldel < scldel_min) 467 continue; 468 469 for (a = 0; a < I2C_TIMINGR_SDADEL_MAX; a++) { 470 uint32_t sdadel = (a * (p + 1) + 1) * i2cclk; 471 472 if ((sdadel >= sdadel_min) && 473 (sdadel <= sdadel_max) && 474 (p != p_prev)) { 475 solutions[p].scldel = l; 476 solutions[p].sdadel = a; 477 solutions[p].is_saved = true; 478 p_prev = p; 479 break; 480 } 481 } 482 483 if (p_prev == p) 484 break; 485 } 486 } 487 488 if (p_prev == I2C_TIMINGR_PRESC_MAX) { 489 EMSG(" I2C no Prescaler solution"); 490 return -1; 491 } 492 493 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 494 clk_max = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_min; 495 clk_min = I2C_NSEC_PER_SEC / i2c_specs[mode].rate_max; 496 497 /* 498 * Among prescaler possibilities discovered above figures out SCL Low 499 * and High Period. Provided: 500 * - SCL Low Period has to be higher than Low Period of the SCL Clock 501 * defined by I2C Specification. I2C Clock has to be lower than 502 * (SCL Low Period - Analog/Digital filters) / 4. 503 * - SCL High Period has to be lower than High Period of the SCL Clock 504 * defined by I2C Specification. 505 * - I2C Clock has to be lower than SCL High Period. 506 */ 507 for (p = 0; p < I2C_TIMINGR_PRESC_MAX; p++) { 508 uint32_t prescaler = (p + 1) * i2cclk; 509 510 if (!solutions[p].is_saved) 511 continue; 512 513 for (l = 0; l < I2C_TIMINGR_SCLL_MAX; l++) { 514 uint32_t tscl_l = ((l + 1) * prescaler) + tsync; 515 516 if ((tscl_l < i2c_specs[mode].l_min) || 517 (i2cclk >= 518 ((tscl_l - af_delay_min - dnf_delay) / 4))) 519 continue; 520 521 for (h = 0; h < I2C_TIMINGR_SCLH_MAX; h++) { 522 uint32_t tscl_h = ((h + 1) * prescaler) + tsync; 523 uint32_t tscl = tscl_l + tscl_h + 524 init->rise_time + 525 init->fall_time; 526 527 if ((tscl >= clk_min) && (tscl <= clk_max) && 528 (tscl_h >= i2c_specs[mode].h_min) && 529 (i2cclk < tscl_h)) { 530 int clk_error = tscl - i2cbus; 531 532 if (clk_error < 0) 533 clk_error = -clk_error; 534 535 if (clk_error < clk_error_prev) { 536 clk_error_prev = clk_error; 537 solutions[p].scll = l; 538 solutions[p].sclh = h; 539 s = p; 540 } 541 } 542 } 543 } 544 } 545 546 if (s < 0) { 547 EMSG(" I2C no solution at all"); 548 return -1; 549 } 550 551 /* Finalize timing settings */ 552 *timing = I2C_SET_TIMINGR_PRESC(s) | 553 I2C_SET_TIMINGR_SCLDEL(solutions[s].scldel) | 554 I2C_SET_TIMINGR_SDADEL(solutions[s].sdadel) | 555 I2C_SET_TIMINGR_SCLH(solutions[s].sclh) | 556 I2C_SET_TIMINGR_SCLL(solutions[s].scll); 557 558 DMSG("I2C TIMINGR (PRESC/SCLDEL/SDADEL): %i/%i/%i", 559 s, solutions[s].scldel, solutions[s].sdadel); 560 DMSG("I2C TIMINGR (SCLH/SCLL): %i/%i", 561 solutions[s].sclh, solutions[s].scll); 562 DMSG("I2C TIMINGR: 0x%x", *timing); 563 564 return 0; 565 } 566 567 /* 568 * Setup the I2C device timings 569 * 570 * @hi2c: I2C handle structure 571 * @init: Ref to the initialization configuration structure 572 * @timing: Output TIMINGR register configuration value 573 * @retval 0 if OK, negative value else 574 */ 575 static int i2c_setup_timing(struct i2c_handle_s *hi2c, 576 struct stm32_i2c_init_s *init, 577 uint32_t *timing) 578 { 579 int rc = 0; 580 uint32_t clock_src = stm32_clock_get_rate(hi2c->clock); 581 582 if (!clock_src) { 583 EMSG("Null I2C clock rate"); 584 return -1; 585 } 586 587 do { 588 rc = i2c_compute_timing(init, clock_src, timing); 589 if (rc) { 590 EMSG("Failed to compute I2C timings"); 591 if (init->speed_mode > I2C_SPEED_STANDARD) { 592 init->speed_mode--; 593 IMSG("Downgrade I2C speed to %uHz)", 594 i2c_specs[init->speed_mode].rate); 595 } else { 596 break; 597 } 598 } 599 } while (rc); 600 601 if (rc) { 602 EMSG("Impossible to compute I2C timings"); 603 return rc; 604 } 605 606 DMSG("I2C Speed Mode(%i), Freq(%i), Clk Source(%i)", 607 init->speed_mode, i2c_specs[init->speed_mode].rate, clock_src); 608 DMSG("I2C Rise(%i) and Fall(%i) Time", 609 init->rise_time, init->fall_time); 610 DMSG("I2C Analog Filter(%s), DNF(%i)", 611 init->analog_filter ? "On" : "Off", init->digital_filter_coef); 612 613 return 0; 614 } 615 616 /* 617 * Configure I2C Analog noise filter. 618 * @hi2c: I2C handle structure 619 * @analog_filter_on: True if enabling analog filter, false otherwise 620 * Return 0 on success or a negative value 621 */ 622 static int i2c_config_analog_filter(struct i2c_handle_s *hi2c, 623 bool analog_filter_on) 624 { 625 vaddr_t base = get_base(hi2c); 626 627 if (hi2c->i2c_state != I2C_STATE_READY) 628 return -1; 629 630 hi2c->i2c_state = I2C_STATE_BUSY; 631 632 /* Disable the selected I2C peripheral */ 633 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 634 635 /* Reset I2Cx ANOFF bit */ 636 io_clrbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 637 638 /* Set analog filter bit if filter is disabled */ 639 if (!analog_filter_on) 640 io_setbits32(base + I2C_CR1, I2C_CR1_ANFOFF); 641 642 /* Enable the selected I2C peripheral */ 643 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 644 645 hi2c->i2c_state = I2C_STATE_READY; 646 647 return 0; 648 } 649 650 int stm32_i2c_get_setup_from_fdt(void *fdt, int node, 651 struct stm32_i2c_init_s *init) 652 { 653 const fdt32_t *cuint = NULL; 654 struct dt_node_info info = { .status = 0 }; 655 656 /* Default STM32 specific configs caller may need to overwrite */ 657 memset(init, 0, sizeof(*init)); 658 659 _fdt_fill_device_info(fdt, &info, node); 660 init->pbase = info.reg; 661 init->clock = info.clock; 662 assert(info.reg != DT_INFO_INVALID_REG && 663 info.clock != DT_INFO_INVALID_CLOCK); 664 665 cuint = fdt_getprop(fdt, node, "i2c-scl-rising-time-ns", NULL); 666 if (cuint) 667 init->rise_time = fdt32_to_cpu(*cuint); 668 else 669 init->rise_time = STM32_I2C_RISE_TIME_DEFAULT; 670 671 cuint = fdt_getprop(fdt, node, "i2c-scl-falling-time-ns", NULL); 672 if (cuint) 673 init->fall_time = fdt32_to_cpu(*cuint); 674 else 675 init->fall_time = STM32_I2C_FALL_TIME_DEFAULT; 676 677 cuint = fdt_getprop(fdt, node, "clock-frequency", NULL); 678 if (cuint) { 679 switch (fdt32_to_cpu(*cuint)) { 680 case STANDARD_RATE: 681 init->speed_mode = I2C_SPEED_STANDARD; 682 break; 683 case FAST_RATE: 684 init->speed_mode = I2C_SPEED_FAST; 685 break; 686 case FAST_PLUS_RATE: 687 init->speed_mode = I2C_SPEED_FAST_PLUS; 688 break; 689 default: 690 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 691 break; 692 } 693 } else { 694 init->speed_mode = STM32_I2C_SPEED_DEFAULT; 695 } 696 697 return 0; 698 } 699 700 int stm32_i2c_init(struct i2c_handle_s *hi2c, 701 struct stm32_i2c_init_s *init_data) 702 { 703 int rc = 0; 704 uint32_t timing = 0; 705 vaddr_t base = 0; 706 uint32_t val = 0; 707 708 hi2c->base.pa = init_data->pbase; 709 hi2c->clock = init_data->clock; 710 711 rc = i2c_setup_timing(hi2c, init_data, &timing); 712 if (rc) 713 return rc; 714 715 stm32_clock_enable(hi2c->clock); 716 base = get_base(hi2c); 717 hi2c->i2c_state = I2C_STATE_BUSY; 718 719 /* Disable the selected I2C peripheral */ 720 io_clrbits32(base + I2C_CR1, I2C_CR1_PE); 721 722 /* Configure I2Cx: Frequency range */ 723 io_write32(base + I2C_TIMINGR, timing & TIMINGR_CLEAR_MASK); 724 725 /* Disable Own Address1 before set the Own Address1 configuration */ 726 io_write32(base + I2C_OAR1, 0); 727 728 /* Configure I2Cx: Own Address1 and ack own address1 mode */ 729 if (init_data->addr_mode_10b_not_7b) 730 io_write32(base + I2C_OAR1, 731 I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | 732 init_data->own_address1); 733 else 734 io_write32(base + I2C_OAR1, 735 I2C_OAR1_OA1EN | init_data->own_address1); 736 737 /* Configure I2Cx: Addressing Master mode */ 738 io_write32(base + I2C_CR2, 0); 739 if (init_data->addr_mode_10b_not_7b) 740 io_setbits32(base + I2C_CR2, I2C_CR2_ADD10); 741 742 /* 743 * Enable the AUTOEND by default, and enable NACK 744 * (should be disabled only during Slave process). 745 */ 746 io_setbits32(base + I2C_CR2, I2C_CR2_AUTOEND | I2C_CR2_NACK); 747 748 /* Disable Own Address2 before set the Own Address2 configuration */ 749 io_write32(base + I2C_OAR2, 0); 750 751 /* Configure I2Cx: Dual mode and Own Address2 */ 752 if (init_data->dual_address_mode) 753 io_write32(base + I2C_OAR2, 754 I2C_OAR2_OA2EN | init_data->own_address2 | 755 (init_data->own_address2_masks << 8)); 756 757 /* Configure I2Cx: Generalcall and NoStretch mode */ 758 val = 0; 759 if (init_data->general_call_mode) 760 val |= I2C_CR1_GCEN; 761 if (init_data->no_stretch_mode) 762 val |= I2C_CR1_NOSTRETCH; 763 io_write32(base + I2C_CR1, val); 764 765 /* Enable the selected I2C peripheral */ 766 io_setbits32(base + I2C_CR1, I2C_CR1_PE); 767 768 hi2c->i2c_err = I2C_ERROR_NONE; 769 hi2c->i2c_state = I2C_STATE_READY; 770 771 rc = i2c_config_analog_filter(hi2c, init_data->analog_filter); 772 if (rc) 773 EMSG("I2C analog filter error %d", rc); 774 775 stm32_clock_disable(hi2c->clock); 776 777 return rc; 778 } 779 780 /* I2C transmit (TX) data register flush sequence */ 781 static void i2c_flush_txdr(struct i2c_handle_s *hi2c) 782 { 783 vaddr_t base = get_base(hi2c); 784 785 /* 786 * If a pending TXIS flag is set, 787 * write a dummy data in TXDR to clear it. 788 */ 789 if (io_read32(base + I2C_ISR) & I2C_ISR_TXIS) 790 io_write32(base + I2C_TXDR, 0); 791 792 /* Flush TX register if not empty */ 793 if ((io_read32(base + I2C_ISR) & I2C_ISR_TXE) == 0) 794 io_setbits32(base + I2C_ISR, I2C_ISR_TXE); 795 } 796 797 /* 798 * Wait for a single target I2C_ISR bit to reach an awaited value (0 or 1) 799 * 800 * @hi2c: I2C handle structure 801 * @bit_mask: Bit mask for the target single bit position to consider 802 * @awaited_value: Awaited value of the target bit in I2C_ISR, 0 or 1 803 * @timeout_ref: Expriation timeout reference 804 * Return 0 on success and a non-zero value on timeout 805 */ 806 static int wait_isr_event(struct i2c_handle_s *hi2c, uint32_t bit_mask, 807 unsigned int awaited_value, uint64_t timeout_ref) 808 { 809 vaddr_t isr = get_base(hi2c) + I2C_ISR; 810 811 assert(IS_POWER_OF_TWO(bit_mask) && !(awaited_value & ~1U)); 812 813 /* May timeout while TEE thread is suspended */ 814 while (!timeout_elapsed(timeout_ref)) 815 if (!!(io_read32(isr) & bit_mask) == awaited_value) 816 break; 817 818 if (!!(io_read32(isr) & bit_mask) == awaited_value) 819 return 0; 820 821 notif_i2c_timeout(hi2c); 822 return -1; 823 } 824 825 /* Handle Acknowledge-Failed sequence detection during an I2C Communication */ 826 static int i2c_ack_failed(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 827 { 828 vaddr_t base = get_base(hi2c); 829 830 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) 831 return 0; 832 833 /* 834 * Wait until STOP Flag is reset. Use polling method. 835 * AutoEnd should be initiate after AF. 836 * Timeout may elpased while TEE thread is suspended. 837 */ 838 while (!timeout_elapsed(timeout_ref)) 839 if (io_read32(base + I2C_ISR) & I2C_ISR_STOPF) 840 break; 841 842 if ((io_read32(base + I2C_ISR) & I2C_ISR_STOPF) == 0) { 843 notif_i2c_timeout(hi2c); 844 return -1; 845 } 846 847 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 848 849 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 850 851 i2c_flush_txdr(hi2c); 852 853 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 854 855 hi2c->i2c_err |= I2C_ERROR_ACKF; 856 hi2c->i2c_state = I2C_STATE_READY; 857 858 return -1; 859 } 860 861 /* Wait TXIS bit is 1 in I2C_ISR register */ 862 static int i2c_wait_txis(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 863 { 864 while (!timeout_elapsed(timeout_ref)) { 865 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 866 break; 867 if (i2c_ack_failed(hi2c, timeout_ref)) 868 return -1; 869 } 870 871 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_TXIS) 872 return 0; 873 874 if (i2c_ack_failed(hi2c, timeout_ref)) 875 return -1; 876 877 notif_i2c_timeout(hi2c); 878 return -1; 879 } 880 881 /* Wait STOPF bit is 1 in I2C_ISR register */ 882 static int i2c_wait_stop(struct i2c_handle_s *hi2c, uint64_t timeout_ref) 883 { 884 while (timeout_elapsed(timeout_ref)) { 885 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 886 break; 887 888 if (i2c_ack_failed(hi2c, timeout_ref)) 889 return -1; 890 } 891 892 if (io_read32(get_base(hi2c) + I2C_ISR) & I2C_ISR_STOPF) 893 return 0; 894 895 if (i2c_ack_failed(hi2c, timeout_ref)) 896 return -1; 897 898 notif_i2c_timeout(hi2c); 899 return -1; 900 } 901 902 /* 903 * Load I2C_CR2 register for a I2C transfer 904 * 905 * @hi2c: I2C handle structure 906 * @dev_addr: Slave address to be transferred 907 * @size: Number of bytes to be transferred 908 * @i2c_mode: One of I2C_{RELOAD|AUTOEND|SOFTEND}_MODE: Enable Reload mode. 909 * @startstop: One of I2C_NO_STARTSTOP, I2C_GENERATE_STOP, 910 * I2C_GENERATE_START_{READ|WRITE} 911 */ 912 static void i2c_transfer_config(struct i2c_handle_s *hi2c, uint32_t dev_addr, 913 uint32_t size, uint32_t i2c_mode, 914 uint32_t startstop) 915 { 916 uint32_t clr_value = I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | 917 I2C_CR2_AUTOEND | I2C_CR2_START | I2C_CR2_STOP | 918 (I2C_CR2_RD_WRN & 919 (startstop >> (31U - I2C_CR2_RD_WRN_OFFSET))); 920 uint32_t set_value = (dev_addr & I2C_CR2_SADD) | 921 ((size << I2C_CR2_NBYTES_OFFSET) & 922 I2C_CR2_NBYTES) | 923 i2c_mode | startstop; 924 925 io_clrsetbits32(get_base(hi2c) + I2C_CR2, clr_value, set_value); 926 } 927 928 /* 929 * Master sends target device address followed by internal memory 930 * address for a memory write request. 931 * Function returns 0 on success or a negative value. 932 */ 933 static int i2c_request_mem_write(struct i2c_handle_s *hi2c, 934 struct i2c_request *request, 935 uint64_t timeout_ref) 936 { 937 vaddr_t base = get_base(hi2c); 938 939 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 940 I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); 941 942 if (i2c_wait_txis(hi2c, timeout_ref)) 943 return -1; 944 945 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 946 /* Send memory address */ 947 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 948 } else { 949 /* Send MSB of memory address */ 950 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 951 952 if (i2c_wait_txis(hi2c, timeout_ref)) 953 return -1; 954 955 /* Send LSB of memory address */ 956 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 957 } 958 959 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 960 return -1; 961 962 return 0; 963 } 964 965 /* 966 * Master sends target device address followed by internal memory 967 * address to prepare a memory read request. 968 * Function returns 0 on success or a negative value. 969 */ 970 static int i2c_request_mem_read(struct i2c_handle_s *hi2c, 971 struct i2c_request *request, 972 uint64_t timeout_ref) 973 { 974 vaddr_t base = get_base(hi2c); 975 976 i2c_transfer_config(hi2c, request->dev_addr, request->mem_addr_size, 977 I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); 978 979 if (i2c_wait_txis(hi2c, timeout_ref)) 980 return -1; 981 982 if (request->mem_addr_size == I2C_MEMADD_SIZE_8BIT) { 983 /* Send memory address */ 984 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 985 } else { 986 /* Send MSB of memory address */ 987 io_write8(base + I2C_TXDR, (request->mem_addr & 0xFF00U) >> 8); 988 989 if (i2c_wait_txis(hi2c, timeout_ref)) 990 return -1; 991 992 /* Send LSB of memory address */ 993 io_write8(base + I2C_TXDR, request->mem_addr & 0x00FFU); 994 } 995 996 if (wait_isr_event(hi2c, I2C_ISR_TC, 1, timeout_ref)) 997 return -1; 998 999 return 0; 1000 } 1001 1002 /* 1003 * Write an amount of data in blocking mode 1004 * 1005 * @hi2c: Reference to struct i2c_handle_s 1006 * @request: I2C request parameters 1007 * @p_data: Pointer to data buffer 1008 * @size: Amount of data to be sent 1009 * Return 0 on success or a negative value 1010 */ 1011 static int i2c_write(struct i2c_handle_s *hi2c, struct i2c_request *request, 1012 uint8_t *p_data, uint16_t size) 1013 { 1014 uint64_t timeout_ref = 0; 1015 vaddr_t base = get_base(hi2c); 1016 int rc = -1; 1017 uint8_t *p_buff = p_data; 1018 size_t xfer_size = 0; 1019 size_t xfer_count = size; 1020 1021 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1022 return -1; 1023 1024 if (hi2c->i2c_state != I2C_STATE_READY) 1025 return -1; 1026 1027 if (!p_data || !size) 1028 return -1; 1029 1030 stm32_clock_enable(hi2c->clock); 1031 1032 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1033 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1034 goto bail; 1035 1036 hi2c->i2c_state = I2C_STATE_BUSY_TX; 1037 hi2c->i2c_err = I2C_ERROR_NONE; 1038 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1039 1040 if (request->mode == I2C_MODE_MEM) { 1041 /* In memory mode, send slave address and memory address */ 1042 if (i2c_request_mem_write(hi2c, request, timeout_ref)) 1043 goto bail; 1044 1045 if (xfer_count > MAX_NBYTE_SIZE) { 1046 xfer_size = MAX_NBYTE_SIZE; 1047 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1048 I2C_RELOAD_MODE, I2C_NO_STARTSTOP); 1049 } else { 1050 xfer_size = xfer_count; 1051 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1052 I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); 1053 } 1054 } else { 1055 /* In master mode, send slave address */ 1056 if (xfer_count > MAX_NBYTE_SIZE) { 1057 xfer_size = MAX_NBYTE_SIZE; 1058 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1059 I2C_RELOAD_MODE, 1060 I2C_GENERATE_START_WRITE); 1061 } else { 1062 xfer_size = xfer_count; 1063 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1064 I2C_AUTOEND_MODE, 1065 I2C_GENERATE_START_WRITE); 1066 } 1067 } 1068 1069 do { 1070 if (i2c_wait_txis(hi2c, timeout_ref)) 1071 goto bail; 1072 1073 io_write8(base + I2C_TXDR, *p_buff); 1074 p_buff++; 1075 xfer_count--; 1076 xfer_size--; 1077 1078 if (xfer_count && !xfer_size) { 1079 /* Wait until TCR flag is set */ 1080 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1081 goto bail; 1082 1083 if (xfer_count > MAX_NBYTE_SIZE) { 1084 xfer_size = MAX_NBYTE_SIZE; 1085 i2c_transfer_config(hi2c, request->dev_addr, 1086 xfer_size, 1087 I2C_RELOAD_MODE, 1088 I2C_NO_STARTSTOP); 1089 } else { 1090 xfer_size = xfer_count; 1091 i2c_transfer_config(hi2c, request->dev_addr, 1092 xfer_size, 1093 I2C_AUTOEND_MODE, 1094 I2C_NO_STARTSTOP); 1095 } 1096 } 1097 1098 } while (xfer_count > 0U); 1099 1100 /* 1101 * No need to Check TC flag, with AUTOEND mode the stop 1102 * is automatically generated. 1103 * Wait until STOPF flag is reset. 1104 */ 1105 if (i2c_wait_stop(hi2c, timeout_ref)) 1106 goto bail; 1107 1108 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1109 1110 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1111 1112 hi2c->i2c_state = I2C_STATE_READY; 1113 1114 rc = 0; 1115 1116 bail: 1117 stm32_clock_disable(hi2c->clock); 1118 1119 return rc; 1120 } 1121 1122 int stm32_i2c_mem_write(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1123 uint32_t mem_addr, uint32_t mem_addr_size, 1124 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1125 { 1126 struct i2c_request request = { 1127 .dev_addr = dev_addr, 1128 .mode = I2C_MODE_MEM, 1129 .mem_addr = mem_addr, 1130 .mem_addr_size = mem_addr_size, 1131 .timeout_ms = timeout_ms, 1132 }; 1133 1134 return i2c_write(hi2c, &request, p_data, size); 1135 } 1136 1137 int stm32_i2c_master_transmit(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1138 uint8_t *p_data, size_t size, 1139 unsigned int timeout_ms) 1140 { 1141 struct i2c_request request = { 1142 .dev_addr = dev_addr, 1143 .mode = I2C_MODE_MASTER, 1144 .timeout_ms = timeout_ms, 1145 }; 1146 1147 return i2c_write(hi2c, &request, p_data, size); 1148 } 1149 1150 /* 1151 * Read an amount of data in blocking mode 1152 * 1153 * @hi2c: Reference to struct i2c_handle_s 1154 * @request: I2C request parameters 1155 * @p_data: Pointer to data buffer 1156 * @size: Amount of data to be sent 1157 * Return 0 on success or a negative value 1158 */ 1159 static int i2c_read(struct i2c_handle_s *hi2c, struct i2c_request *request, 1160 uint8_t *p_data, uint32_t size) 1161 { 1162 vaddr_t base = get_base(hi2c); 1163 uint64_t timeout_ref = 0; 1164 int rc = -1; 1165 uint8_t *p_buff = p_data; 1166 size_t xfer_count = size; 1167 size_t xfer_size = 0; 1168 1169 if (request->mode != I2C_MODE_MASTER && request->mode != I2C_MODE_MEM) 1170 return -1; 1171 1172 if (hi2c->i2c_state != I2C_STATE_READY) 1173 return -1; 1174 1175 if (!p_data || !size) 1176 return -1; 1177 1178 stm32_clock_enable(hi2c->clock); 1179 1180 timeout_ref = timeout_init_us(I2C_TIMEOUT_BUSY_MS * 1000); 1181 if (wait_isr_event(hi2c, I2C_ISR_BUSY, 0, timeout_ref)) 1182 goto bail; 1183 1184 hi2c->i2c_state = I2C_STATE_BUSY_RX; 1185 hi2c->i2c_err = I2C_ERROR_NONE; 1186 timeout_ref = timeout_init_us(request->timeout_ms * 1000); 1187 1188 if (request->mode == I2C_MODE_MEM) { 1189 /* Send memory address */ 1190 if (i2c_request_mem_read(hi2c, request, timeout_ref)) 1191 goto bail; 1192 } 1193 1194 /* 1195 * Send slave address. 1196 * Set NBYTES to write and reload if xfer_count > MAX_NBYTE_SIZE 1197 * and generate RESTART. 1198 */ 1199 if (xfer_count > MAX_NBYTE_SIZE) { 1200 xfer_size = MAX_NBYTE_SIZE; 1201 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1202 I2C_RELOAD_MODE, I2C_GENERATE_START_READ); 1203 } else { 1204 xfer_size = xfer_count; 1205 i2c_transfer_config(hi2c, request->dev_addr, xfer_size, 1206 I2C_AUTOEND_MODE, I2C_GENERATE_START_READ); 1207 } 1208 1209 do { 1210 if (wait_isr_event(hi2c, I2C_ISR_RXNE, 1, timeout_ref)) 1211 goto bail; 1212 1213 *p_buff = io_read8(base + I2C_RXDR); 1214 p_buff++; 1215 xfer_size--; 1216 xfer_count--; 1217 1218 if (xfer_count && !xfer_size) { 1219 if (wait_isr_event(hi2c, I2C_ISR_TCR, 1, timeout_ref)) 1220 goto bail; 1221 1222 if (xfer_count > MAX_NBYTE_SIZE) { 1223 xfer_size = MAX_NBYTE_SIZE; 1224 i2c_transfer_config(hi2c, request->dev_addr, 1225 xfer_size, 1226 I2C_RELOAD_MODE, 1227 I2C_NO_STARTSTOP); 1228 } else { 1229 xfer_size = xfer_count; 1230 i2c_transfer_config(hi2c, request->dev_addr, 1231 xfer_size, 1232 I2C_AUTOEND_MODE, 1233 I2C_NO_STARTSTOP); 1234 } 1235 } 1236 } while (xfer_count > 0U); 1237 1238 /* 1239 * No need to Check TC flag, with AUTOEND mode the stop 1240 * is automatically generated. 1241 * Wait until STOPF flag is reset. 1242 */ 1243 if (i2c_wait_stop(hi2c, timeout_ref)) 1244 goto bail; 1245 1246 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1247 1248 io_clrbits32(base + I2C_CR2, CR2_RESET_MASK); 1249 1250 hi2c->i2c_state = I2C_STATE_READY; 1251 1252 rc = 0; 1253 1254 bail: 1255 stm32_clock_disable(hi2c->clock); 1256 1257 return rc; 1258 } 1259 1260 int stm32_i2c_mem_read(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1261 uint32_t mem_addr, uint32_t mem_addr_size, 1262 uint8_t *p_data, size_t size, unsigned int timeout_ms) 1263 { 1264 struct i2c_request request = { 1265 .dev_addr = dev_addr, 1266 .mode = I2C_MODE_MEM, 1267 .mem_addr = mem_addr, 1268 .mem_addr_size = mem_addr_size, 1269 .timeout_ms = timeout_ms, 1270 }; 1271 1272 return i2c_read(hi2c, &request, p_data, size); 1273 } 1274 1275 int stm32_i2c_master_receive(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1276 uint8_t *p_data, size_t size, 1277 unsigned int timeout_ms) 1278 { 1279 struct i2c_request request = { 1280 .dev_addr = dev_addr, 1281 .mode = I2C_MODE_MASTER, 1282 .timeout_ms = timeout_ms, 1283 }; 1284 1285 return i2c_read(hi2c, &request, p_data, size); 1286 } 1287 1288 bool stm32_i2c_is_device_ready(struct i2c_handle_s *hi2c, uint32_t dev_addr, 1289 unsigned int trials, unsigned int timeout_ms) 1290 { 1291 vaddr_t base = get_base(hi2c); 1292 unsigned int i2c_trials = 0U; 1293 bool rc = false; 1294 1295 if (hi2c->i2c_state != I2C_STATE_READY) 1296 return rc; 1297 1298 stm32_clock_enable(hi2c->clock); 1299 1300 if (io_read32(base + I2C_ISR) & I2C_ISR_BUSY) 1301 goto bail; 1302 1303 hi2c->i2c_state = I2C_STATE_BUSY; 1304 hi2c->i2c_err = I2C_ERROR_NONE; 1305 1306 do { 1307 uint64_t timeout_ref = 0; 1308 vaddr_t isr = base + I2C_ISR; 1309 1310 /* Generate Start */ 1311 if ((io_read32(base + I2C_OAR1) & I2C_OAR1_OA1MODE) == 0) 1312 io_write32(base + I2C_CR2, 1313 ((dev_addr & I2C_CR2_SADD) | 1314 I2C_CR2_START | I2C_CR2_AUTOEND) & 1315 ~I2C_CR2_RD_WRN); 1316 else 1317 io_write32(base + I2C_CR2, 1318 ((dev_addr & I2C_CR2_SADD) | 1319 I2C_CR2_START | I2C_CR2_ADD10) & 1320 ~I2C_CR2_RD_WRN); 1321 1322 /* 1323 * No need to Check TC flag, with AUTOEND mode the stop 1324 * is automatically generated. 1325 * Wait until STOPF flag is set or a NACK flag is set. 1326 */ 1327 timeout_ref = timeout_init_us(timeout_ms * 1000); 1328 while (!timeout_elapsed(timeout_ref)) 1329 if (io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) 1330 break; 1331 1332 if ((io_read32(isr) & (I2C_ISR_STOPF | I2C_ISR_NACKF)) == 0) { 1333 notif_i2c_timeout(hi2c); 1334 goto bail; 1335 } 1336 1337 if ((io_read32(base + I2C_ISR) & I2C_ISR_NACKF) == 0U) { 1338 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1339 goto bail; 1340 1341 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1342 1343 hi2c->i2c_state = I2C_STATE_READY; 1344 1345 rc = true; 1346 goto bail; 1347 } 1348 1349 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1350 goto bail; 1351 1352 io_write32(base + I2C_ICR, I2C_ISR_NACKF); 1353 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1354 1355 if (i2c_trials == trials) { 1356 io_setbits32(base + I2C_CR2, I2C_CR2_STOP); 1357 1358 if (wait_isr_event(hi2c, I2C_ISR_STOPF, 1, timeout_ref)) 1359 goto bail; 1360 1361 io_write32(base + I2C_ICR, I2C_ISR_STOPF); 1362 } 1363 1364 i2c_trials++; 1365 } while (i2c_trials < trials); 1366 1367 notif_i2c_timeout(hi2c); 1368 1369 bail: 1370 stm32_clock_disable(hi2c->clock); 1371 1372 return rc; 1373 } 1374 1375 void stm32_i2c_resume(struct i2c_handle_s *hi2c) 1376 { 1377 if (hi2c->i2c_state == I2C_STATE_READY) 1378 return; 1379 1380 if ((hi2c->i2c_state != I2C_STATE_RESET) && 1381 (hi2c->i2c_state != I2C_STATE_SUSPENDED)) 1382 panic(); 1383 1384 if (hi2c->i2c_state == I2C_STATE_RESET) { 1385 /* This is no valid I2C configuration loaded yet */ 1386 return; 1387 } 1388 1389 restore_cfg(hi2c, &hi2c->sec_cfg); 1390 1391 hi2c->i2c_state = I2C_STATE_READY; 1392 } 1393 1394 void stm32_i2c_suspend(struct i2c_handle_s *hi2c) 1395 { 1396 if (hi2c->i2c_state == I2C_STATE_SUSPENDED) 1397 return; 1398 1399 if (hi2c->i2c_state != I2C_STATE_READY) 1400 panic(); 1401 1402 save_cfg(hi2c, &hi2c->sec_cfg); 1403 1404 hi2c->i2c_state = I2C_STATE_SUSPENDED; 1405 } 1406